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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

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Exploring heterogeneous mobile architectures with a high-level programming model 29

Exploring heterogeneous mobile architectures with a high-lev...

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29th international symposium on computer architecture and high performance computing SBAC-PAD

作者： de Carvalho, Wilson Andrade, Guilherme Caldeira, Pedro Utsch, Renato Ferreira, Renato Rocha, Leonardo Carvalho, Renan Nasser, Millas Univ Fed Minas Gerais Belo Horizonte MG Brazil Univ Fed Sao Joao del Rei Sao Joao Del Rei MG Brazil

ISBN: (纸本)9781509012336

The development of new technologies is setting a new era characterized, among other factors, by the rise of sophisticated mobile devices containing CPUs and GPUs. This emerging scenario of heterogeneous mobile architectures brings challenging issues regarding the use of the available computing resources. Such issues are mainly related to the intrinsic complexity of coordinating these processors in order to increase application performance. In this sense, this paper presents a high-level programming model to implement parallel patterns that can be executed in a coordinate way by heterogeneous mobile architectures. A comparative analysis of performance and programming complexity is presented, contrasting code generated automatically from the proposed programming model with low-level manually-optimized implementations.

关键词： Program processors

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Processing Neocognitron of Face Recognition on high performance Environment Based on GPU with CUDA architecture

Processing Neocognitron of Face Recognition on High Performa...

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20th international symposium on computer architecture and high performance computing

作者： Poli, Gustavo Saito, Jose Hiroki Mari, Joao F. Zorzan, Marcelo R. Univ Fed Sao Carlos Dept Comp BR-13560 Sao Carlos SP Brazil

ISBN: (纸本)9780769534237

This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an artificial neural network, proposed by Fukushima and collaborators, constituted of several hierarchical stages of neuron layers, organized in. two-dimensional matrices called cellular planes. For the high performance computation of Face Recognition application using Neocognitron it was used CUDA (Compute Unified Device architecture) as API (Application Programming Interface) between the CPU and the GPU, from GeForce 8800 GTX of NVIDIA company, with 128 ALU's. As face image databases it was used a face database created at UFS-Car and the CMU-PIE (Carnegie Mellon University Pose, Illumination and Expression) database. The load balancing was achieved through the use of cellular connections as threads organized in blocks, following the CUDA philosophy), of development. The results showed the feasibility of this type of device as a massively parallel data processing tool, and that smaller the granularity and the data dependency of the parallel processing, better is its performance.

关键词： Graphics processing unit

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Speeding Up Stencil Computations with Kernel Convolution 28

Speeding Up Stencil Computations with Kernel Convolution

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Januario, Guilherme C. Rosenburg, Bryan S. Park, Yoonho Perrone, Michael Moreira, Jose Carvalho, Tereza C. M. B. IBM Corp TJ Watson Res Ctr Yorktown Hts NY 10598 USA Univ Sao Paulo Polytech Sch Lab Sustainabil Sao Paulo SP Brazil

ISBN: (纸本)9781509061082

A technique to speed up stencil computation is introduced. Computation and data reuse schemes are developed for its application to 1- and 3-dimensional stencils. The approach traverses the data domain fewer times than a state-of-the-art, straightforward iterative stencil implementation would. performance results are shown for a variety of platforms, exemplifying how it can be straightforwardly applied with existing techniques and frameworks. The technique, named Aggregate Stencil-Loop Iteration (ASLI), works by applying a stencil obtained by the original stencil operator convolved with itself one or more times. This more complex operator creates new opportunities for in-register data reuse and increases the FLOPs-to-load ratio. The total number of FLOPs decreases for 1D but increases for 2D and 3D star-shaped stencils. In both scenarios, speed-up relative to the state-of-the-art is achieved. ASLI is relatively easy to implement and works synergistically with existing methods to optimize stencil computations.

关键词： high-performance computing Numeric kernels optimization stencil computation

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RAID-x: A new distributed disk array for I/O-centric cluster computing 9

RAID-x: A new distributed disk array for I/O-centric cluster...

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9th ieee international symposium on high performance Distributed computing

作者： Hwang, K Jin, H Ho, R Univ So Calif Los Angeles CA 90089 USA

ISBN: (纸本)0769507832;0769507840

A new RAID-x (redundant array of inexpensive disks at level x) architecture is presented for distributed I/O processing on a serverless cluster of computers. The RAID-x architecture is based on a new concept of orthogonal striping and mirroring (OSM) across all distributed disks in the cluster. The primary advantages of this OSM approach lie in: (1) a significant improvement in parallel I/O bandwidth, (2) hiding disk mirroring overhead in the background, and (3) greatly enhanced scalability and reliability in cluster computing applications. All claimed advantages are substantiated with benchmark performance results on the Trojans cluster built at USC in 1999. Throughout the paper, we discuss the issues of scalable I/O performance, enhanced system reliability, and striped checkpointing on distributed RAID-x in serverless cluster environment.

关键词： Bandwidth Checkpointing computer applications computer architecture Concurrent computing Distributed computing Linux Packaging Reliability Scalability

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I/O performance of multiscale finite element simulations on HPC environments 34

I/O performance of multiscale finite element simulations on ...

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34th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Boito, Francieli Gomes, Antonio Tadeu A. Peyrondet, Louis Teylo, Luan Univ Bordeaux LaBRI INRIA Bordeaux INPCNRSUMR 5800 F-33400 Talence France Lab Nacl Comp Cient LNCC Av Getulio Vargas 333 BR-25651075 Petropolis RJ Brazil

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

In this paper, we present MSLIO, a code to mimic the I/O behavior of multiscale simulations. Such an I/O kernel is useful for HPC research, as it can be executed more easily and more efficiently than the full simulations when researchers are interested in the I/O load only. We validate MSLIO by comparing it to the I/O performance of an actual simulation, and we then use it to test some possible improvements to the output routine of the MHM (Multiscale Hybrid Mixed) library.

关键词： high-performance computing parallel I/O numeric library I/O kernel mini-app multiscale simulation

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Assessing Time Predictability Features of ARM *** Multicores 30

Assessing Time Predictability Features of ARM *** Multicores

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Fernandez, Gabriel Cazorla, Francisco J. Abella, Jaume Girbal, Sylvain BSC Barcelona Spain CSIC IAAA Madrid Spain UPC Barcelona Spain THALES Res & Technol TRT Palaiseau France

ISBN: (纸本)9781538677698

The increasing performance needs in critical real-time embedded systems (CRTES), such as for instance the automotive domain, push for the adoption of high-performance hardware from the consumer electronics domain. However, their time-predictability features are quite unexplored. The ARM *** architecture is a good candidate for adoption in the CRTES market (i.e. in the automotive market it has already started being used). In this paper we study ARM ***'s capabilities to meet CRTES requirements. In particular, we perform a qualitative and quantitative assessment of its timing characteristics, focusing on shared multicore resources, and how this architecture can be reliably used in CRTES.

关键词： Program processors computer architecture Timing Real-time systems Monitoring Task analysis Benchmark testing

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SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution 29

SpecFaaS: Accelerating Serverless Applications with Speculat...

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29th ieee international symposium on high-performance computer architecture (HPCA)

作者： Stojkovic, Jovan Xu, Tianyin Franke, Hubertus Torrellas, Josep Univ Illinois Urbana IL 61801 USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9781665476522

Serverless computing has emerged as a popular cloud computing paradigm. Serverless environments are convenient to users and efficient for cloud providers. However, they can induce substantial application execution overheads, especially in applications with many functions. In this paper, we propose to accelerate serverless applications with a novel approach based on software-supported speculative execution of functions. Our proposal is termed Speculative Function-as-a-Service (SpecFaaS). It is inspired by out-of-order execution in modern processors, and is grounded in a characterization analysis of FaaS applications. In SpecFaaS, functions in an application are executed early, speculatively, before their control and data dependences are resolved. Control dependences are predicted like in pipeline branch prediction, and data dependences are speculatively satisfied with memoization. With this support, the execution of downstream functions is overlapped with that of upstream functions, substantially reducing the end-to-end execution time of applications. We prototype SpecFaaS on Apache OpenWhisk, an open-source serverless computing platform. For a set of applications in a warmed-up environment, SpecFaaS attains an average speedup of 4.6x. Further, on average, the application throughput increases by 3.9x and the tail latency decreases by 58.7%.

关键词： Cloud computing Serverless computing Function-as-a-Service

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Enterprise IT trends and implications for architecture research

Enterprise IT trends and implications for architecture resea...

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11th international symposium on high-performance computer architecture

作者： Ranganathan, P Jouppi, N Hewlett Packard Labs ISSL MMSL Palo Alto CA USA

ISBN: (纸本)0769522750

The last decade has seen several changes in the structure and emphasis of enterprise IT systems. Specific infrastructure trends have included the emergence of large consolidated data centers, the adoption of virtualization and modularization, and an increased commoditization of hardware. At the application level, both the workload mix and usage patterns have evolved to an increased emphasis on service-centric computing and SLA-driven performance tuning. These, often dramatic, changes in the enterprise IT landscape motivate equivalent changes in the emphasis of architecture research. In this paper, we summarize some recent trends in enterprise IT systems and discuss the implications for architecture research, suggesting some high-level challenges and open questions for the community to address.

关键词： computer architecture

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Enabling microservices management for Deep Learning applications across the Edge-Cloud Continuum 33

Enabling microservices management for Deep Learning applicat...

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33rd ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Houmani, Zeina Balouek-Thomert, Daniel Caron, Eddy Parashar, Manish Univ Lyon Inria Avalon Team LIP Lab UMR CNRS ENS Lyon Lyon France Univ Utah Sci Comp Imaging SCI Inst Salt Lake City UT 84112 USA

ISBN: (纸本)9781665443012

Deep Learning has shifted the focus of traditional batch workflows to data-driven feature engineering on streaming data. In particular, the execution of Deep Learning workflows presents expectations of near-real-time results with user-defined acceptable accuracy. Meeting the objectives of such applications across heterogeneous resources located at the edge of the network, the core, and in-between requires managing trade-offs between the accuracy and the urgency of the results. However, current data analysis rarely manages the entire Deep Learning pipeline along the data path, making it complex for developers to implement strategies in real-world deployments. Driven by an object detection use case, this paper presents an architecture for time-critical Deep Learning workflows by providing a data-driven scheduling approach to distribute the pipeline across Edge to Cloud resources. Furthermore, it adopts a data management strategy that reduces the resolution of incoming data when potential trade-off optimizations are available. We illustrate the system's viability through a performance evaluation of the object detection use case on the Grid'5000 testbed. We demonstrate that in a multi-user scenario, with a standard frame rate of 25 frames per second, the system speed-up data analysis up to 54.4% compared to a Cloud-only-based scenario with an analysis accuracy higher than a fixed threshold.

关键词： Cloud computing Edge computing Microservices Task allocation Real-time processing computing Continuum Deep Learning

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The What's Next Intermittent computing architecture 25

The What's Next Intermittent Computing Architecture

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25th ieee international symposium on high performance computer architecture (HPCA)

作者： Ganesan, Karthik San Miguel, Joshua Jerger, Natalie Enright Univ Toronto Toronto ON Canada Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781728114446

Energy-harvesting devices operate under extremely tight energy constraints. Ensuring forward progress under frequent power outages is paramount. Applications running on these devices are typically amenable to approximation, offering new opportunities to provide better forward progress between power outages. We propose What's Next (WN), a set of anytime approximation techniques for energy harvesting: subword pipelining, subword vectorization and skim points. Skim points fundamentally decouple the checkpoint location from the recovery location upon a power outage. Ultimately, WN transforms processing on energy-harvesting devices from all-or-nothing to as-is computing. We enable an approximate (yet acceptable) result sooner and proceed to the next task when power is restored rather than resume processing from a checkpoint to yield the perfect output. WN yields speedups of 2.26x and 3.02x on non-volatile and checkpoint-based volatile processors, while still producing high-quality outputs.

关键词： energy harvesting intermittent computing approximate computing

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