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2025 ieee international Conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Li, Bohan Wang, Hankun Zhang, Situo Guo, Yiwei Yu, Kai MoE Key Lab of Artificial Intelligence AI Institute X-LANCE Lab Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9798350368741

The auto-regressive (AR) architecture, exemplified by models such as GPT, is extensively utilized in modern Text-to-Speech (TTS) systems. However, it often leads to considerable inference delays, primarily due to the challenges associated with next-token prediction in long speech sequences. In this work, we introduce VADUSA, one of the first approaches to accelerate AR-based TTS through speculative decoding. Our findings demonstrate that VADUSA not only delivers a significant reduction in inference time but also enhances TTS quality by employing draft heads to predict future speech tokens in an auto-regressive manner. Additionally, the incorporation of a tolerance mechanism during the sampling process further boosts performance, yielding approximately a 3× speedup in AR TTS. Moreover, our approach exhibits strong generalization across diverse datasets and various speech token types. © 2025 ieee.

关键词： inference speedup speculative decoding text-to-speech

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Anaheim: architecture and Algorithms for Processing Fully Homomorphic Encryption in Memory

Anaheim: Architecture and Algorithms for Processing Fully Ho...

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ieee symposium on high-performance computer architecture

作者： Jongmin Kim Sungmin Yun Hyesung Ji Wonseok Choi Sangpyo Kim Jung Ho Ahn Seoul National University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Fully homomorphic encryption (FHE) is a promising solution for privacy-preserving cloud computing as it enables computations on sensitive data without any risk of data leakage. Despite the significant attention FHE has received, substantial computation and memory demands make it hardly practical for real-world applications. We propose a readily available and practical hardware solution to tackle this problem by using GPUs. GPUs have adequate computational and memory resources to handle complex operations in FHE, including number-theoretic transform (NTT), on which most prior work has deeply focused. However, through detailed analyses, we discover that the performance bottleneck on GPUs is primarily due to simpler element-wise operations, which are limited by off-chip memory (DRAM) bandwidth. Motivated by these observations, we develop Anaheim, a processing-in-memory (PIM) architecture for FHE. We develop optimized FHE execution flows and an end-toend software framework for using PIM with GPUs. Also, we design a versatile PIM unit that handles various modular integer arithmetic PIM instructions, along with an efficient data mapping and associated PIM execution algorithms that minimize data access overhead by leveraging the internal structure of DRAM. Our concerted efforts substantially enhance the performance and energy efficiency of various FHE workloads on GPUs.

关键词： Software algorithms Layout Random access memory computer architecture Bandwidth Transforms Software Energy efficiency Hardware Homomorphic encryption

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GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerators

GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerato...

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ieee symposium on high-performance computer architecture

作者： Siling Yang Shuibing He Wenjiong Wang Yanlong Yin Tong Wu Weijian Chen Xuechen Zhang Xian-He Sun Dan Feng The State Key Laboratory of Blockchain and Data Security Zhejiang University Zhejiang Lab Hangzhou High-Tech Zone (Binjiang) Institute of Blockchain and Data Security Zhejiang Key Laboratory of Big Data Intelligent Computing Washington State University Vancouver Illinois Institute of Technology Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Graph convolutional networks (GCNs) are popular for a variety of graph learning tasks. ReRAM-based processing-in-memory (PIM) accelerators are promising to expedite GCN training owing to their in-situ computing capability. However, existing accelerators can be severely underutilized even with pipelines, due to the oversight of the skewed execution times of various GCN stages and the ignorance of skewed degrees of graph vertices. In this work, we propose GOPIM, a GCN-oriented pipeline optimization for PIM accelerators to expedite GCN training. First, GOPIM proposes an ML-based scheme that allocates crossbar resources to the most needed stages to streamline the overall pipeline. Second, GOPIM utilizes a selective vertex updating technique that evenly distributes vertices on crossbars by interleaved mapping. These techniques collectively reduce the overall execution time without losing much accuracy. We also provide a practical architecture design for GOPIM. Our experimental results show that, GoPIM achieves up to 191 × speedup and 16.1 × energy saving, compared to the state-of-the-art work.

关键词： Training Accuracy Graph convolutional networks Pipelines Energy conservation computer architecture Machine learning Parallel processing Optimization

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Reuse-Aware Compilation for Zoned Quantum architectures Based on Neutral Atoms

Reuse-Aware Compilation for Zoned Quantum Architectures Base...

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ieee symposium on high-performance computer architecture

作者： Wan-Hsuan Lin Daniel Bochen Tan Jason Cong University of California Los Angeles Department of Physics Harvard University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Quantum computing architectures based on neutral atoms offer large scales and high-fidelity operations. They can be heterogeneous, with different zones for storage, entangling operations, and readout. Zoned architectures improve computation fidelity by shielding idling qubits in storage from side-effect noise, unlike monolithic architectures where all operations occur in a single zone. However, supporting these flexible architectures with efficient compilation remains challenging. In this paper, we propose ZAC, a scalable compiler for zoned architectures. ZAC minimizes data movement overhead between zones with qubit reuse, i.e., keeping them in the entanglement zone if an immediate entangling operation is pending. Other innovations include novel data placement and instruction scheduling strategies in ZAC, a flexible specification of zoned architectures, and an intermediate representation for zoned architectures, ZAIR. Our evaluation shows that zoned architectures equipped with ZAC achieve a 22x improvement in fidelity compared to monolithic architectures. Moreover, ZAC is shown to have a 10% fidelity gap on average compared to the ideal solution. This significant performance enhancement enables more efficient and reliable quantum circuit execution, enabling advancements in quantum algorithms and applications. ZAC is open source at https://***/UCLAVAST/ZAC

关键词： Technological innovation Quantum algorithm Program processors Scheduling algorithms Qubit computer architecture Atoms Parallel processing Integrated circuit reliability Quantum circuit

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ER-DCIM: Error-Resilient Digital CIM architecture with Run-Time MAC-Cell Error Correction

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-T...

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ieee symposium on high-performance computer architecture

作者： Zhen He Yiqi Wang Zihan Wu Shaojun Wei Yang Hu Fengbin Tu Shouyi Yin School of Integrated Circuits BNRist Tsinghua University Beijing China The Hong Kong University of Science and Technology Hong Kong China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Digital computing-in-memory (CIM) is an emerging solution to break through the limitations of memory wall by integrating digital logic into SRAM, which is able to achieve high area and energy efficiency with no accuracy loss. Digital CIM’s SRAM cells are still prone to errors like conventional SRAM due to noise and variation, especially under low-voltage operation for high energy efficiency. The SRAM cell errors cause multiplyaccumulation (MAC) result errors, which may seriously damage the neural network inference accuracy. However, traditional SRAM’s error correcting code (ECC) that corrects errors in one read-out row is incompatible with digital CIM, which reads out multiple rows simultaneously for computation. Detecting and correcting computational MAC errors and SRAM cell errors (i.e., MAC-cell errors) in digital CIM remain largely *** address digital CIM’s unique MAC-cell error resilience needs, we propose ER-DCIM, an error-resilient digital CIM with run-time MAC-cell error correction to guarantee computation correctness. The proposed residue code-based MAC error correction mechanism is the first to correct additive errors in the MAC result in real time during DCIM computation. Then, we propose a progressive cell error correction mechanism to correct underlying cell error in a timely manner, avoiding performance loss due to stalling computation. Further, we design a mode switcher to repurpose redundant error-resilient logic reserved for low-voltage mode to improve performance in high-voltage mode. Experimental results show that the proposed techniques enable digital CIM to maintain high throughput and energy efficiency without accuracy loss in both low-voltage and high-voltage modes.

关键词： Low voltage Accuracy Microprocessors high-voltage techniques In-memory computing SRAM cells Energy efficiency Common Information Model (computing) Error correction codes Resilience

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LSQCA: Resource-Efficient Load/Store architecture for Limited-Scale Fault-Tolerant Quantum computing

LSQCA: Resource-Efficient Load/Store Architecture for Limite...

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ieee symposium on high-performance computer architecture

作者： Takumi Kobori Yasunari Suzuki Yosuke Ueno Teruo Tanimoto Synge Todo Yuuki Tokunaga The University of Tokyo NTT Corporation RIKEN Kyushu University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Current fault-tolerant quantum computer (FTQC) architectures utilize several encoding techniques to enable reliable logical operations with restricted qubit connectivity. However, such logical operations demand additional memory overhead to ensure fault tolerance. Since the main obstacle to practical quantum computing is the limited qubit count, our primary mission is to design floorplans that can reduce memory overhead without compromising computational capability. Despite extensive efforts to explore FTQC architectures, even the current state-of-the-art floorplan strategy devotes 50% of memory space to this overhead, not to data storage, to guarantee unit-time random access to all logical qubits. In this paper, we propose an FTQC architecture based on a novel floorplan strategy, Load/Store Quantum computer architecture (LSQCA), which can achieve almost 100% memory density. The idea behind our architecture is to separate the whole memory regions into small computational space called Computational Registers (CR) and space-efficient memory space called Scan-Access Memory (SAM). We define an instruction set for these abstract structures and provide concrete designs named point-SAM and line-SAM architectures. With this design, we can improve the memory density by allowing variable-latency memory access while concealing the latency with other bottlenecks. We also propose optimization techniques to exploit properties of quantum programs observed in our static analysis, such as access locality in memory reference timestamps. Our numerical results indicate that LSQCA successfully leverages this idea. In a resource-restricted situation, a specific benchmark shows that we can achieve approximately 90% memory density with 5% increase in the execution time compared to a conventional floorplan, which achieves at most 50% memory density for unit-time random access. Our design is defined as an abstract form, making this principle ubiquitous and applicable to a wide range of quant

关键词： Fault tolerance Quantum advantage Instruction sets Qubit Fault tolerant systems Memory architecture computer architecture Static analysis Registers Optimization

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Gemina: A Coordinated and high-performance Memory Deduplication Engine

Gemina: A Coordinated and High-Performance Memory Deduplicat...

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ieee symposium on high-performance computer architecture

作者： Zhehua Zhang Suzhen Wu Wenyan You Chunfeng Du Bo Mao Xiamen Key Laboratory of Intelligent Storage and Computing School of Informatics Xiamen University Xiamen Fujian China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Memory deduplication is widely used to effectively reduce the memory footprint in operating systems, while huge pages are employed to enhance access performance by increasing TLB hit rates. Unfortunately, duplicate huge pages are very rare in memory, leading to most huge pages being split into base pages during deduplication, which degrades access performance by up to $\mathbf{4 3 \%}$. Although asynchronous huge page promotion attempts to elevate multiple base pages to huge pages to maximize performance, deduplication disrupts the uniformity of page attributes, limiting the effectiveness of such promotions. To address this problem, we designed Gemina, a new memory deduplication scheme that coordinates huge page management. Gemina employs a fine-grained detector to distinguish pages, redundancy and hotness, a distributor to process pages conservatively and avoid frequent switches, and an adapter to organize memory for fast conversion. This approach balances the trade-off between performance and space efficiency in memory management. Experimental evaluations show that, compared to the naive KSM-based deduplication scheme, Gemina can achieve $96.1 \%$ of the memory savings of KSM while also improving memory access performance by $\mathbf{4 3. 1 \%}$ in random access.

关键词： Limiting Operating systems Memory management Redundancy Detectors Protection Engines

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Hydra: Scale-out FHE Accelerator architecture for Secure Deep Learning on FPGA

Hydra: Scale-out FHE Accelerator Architecture for Secure Dee...

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ieee symposium on high-performance computer architecture

作者： Yinghao Yang Xicheng Xu Haibin Zhang Jie Song Xin Tang Hang Lu Xiaowei Li State Key Laboratory of Processors Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China Zhongguancun Laboratory Beijing China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Deep learning, including Convolutional Neural Network (CNN) and Large Language Model (LLM), under Fully Homomorphic Encryption (FHE) is very computationally intensive because of the burdensome computations like ciphertext convolution and matrix multiplication, non-linear layers, and bootstrapping. Existing FHE accelerators focus on the high throughput computational units, stacking parallelized clusters to maximize ciphertext inference performance. Nevertheless, this design philosophy cannot leverage the substantial parallelism at the application level and is not scalable for further performance enhancement by simply adding additional compute nodes to cope with the ever-increasing model sizes in the future. In this paper, we propose the high-performance FHE acceleration architecture in a “scale-out” manner for secure deep learning, termed as Hydra. It supports the multi-server scaling and arbitrary computational nodes theoretically, each handling a portion of the deep learning model governed by the central scheduling mechanism on the host server. Hydra exhibits excellent scalability and delivers outstanding performance across a range of compute resource sizes. We highlight the following results: (1) up to $74 \times$ and $160 \times$ speedup over the SOTA single card accelerator Poseidon and FAB; (2) outperforms 8-card FAB-2 by $12 \times$ to $21 \times$ for FHE-based CNNs and LLMs; (3) outperforms SOTA ASIC accelerators, CraterLake and SHARP, by $8.1 \times$ and $2.5 \times$ for LLM OPT-6.7B, and achieves comparable or superior energy efficiency under the same chip technology.

关键词： Deep learning Computational modeling System performance Scalability Stacking Accelerator architectures Throughput Convolutional neural networks Synchronization Servers

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Introduction to the special issue on the 18th international symposium on computer architecture and high performance computing

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international JOURNAL OF PARALLEL PROGRAMMING 2008年第2期36卷 163-165页

作者： De Souza, Alberto F. Buyya, Rajkumar Univ Fed Espirito Santo Dept Informat Lab Comp Alto Desemmpenho Vitoria ES Brazil Univ Melbourne Dept Comp Sci & Software Engn Grid Comp & Distributed Syst Lab Carlton Vic Australia

The article discusses various reports published within the issue, including one on a dual-thread speculation system and another on a parallel version of the Tricluster algorithm.

关键词： computer systems computer algorithms

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Enterprise Class Modular Cache Hierarchy

Enterprise Class Modular Cache Hierarchy

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ieee symposium on high-performance computer architecture

作者： Craig Walters Deanna Berger Robert Sonnelitter Alper Buyuktosunoglu IBM Infrastructure IBM Research

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The IBM Z® platform is optimized for processing vast amounts of data and transactions with low latency in a highly virtualized and secured environment. The platform and its microprocessor chip are designed to deliver consistent system performance, throughput, and response latencies with sustained processor utilization of over $\mathbf{9 0 \%}$ under all workload conditions. The IBM Telum® and IBM Telum® ${ }^{\circledR}$ II designs introduced a novel modular and scalable cache hierarchy to the industry that is extendable to future platform generations, the adoption of emerging technologies, and new architecture enhancements, all of which are required to meet the continuously evolving needs of the mission critical workloads that run on the platform. This paper demonstrates the flow of processor fetch events and how the adaptive horizontal cache persistence algorithms work in this novel design. It explores the performance and system effects of cache size changes in this architecture. Finally, the paper explores how the resulting application of solutions leveraging these effects enhances the robustness of the next generation IBM Z caching solution embedded in the IBM Telum® II Processor, which improves mission critical workload performance while simultaneously enabling the generative AI capability.

关键词： performance evaluation System performance Microprocessor chips Switched mode power supplies Mission critical systems Systems architecture computer architecture Throughput Robustness Next generation networking

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