检索结果-内蒙古大学图书馆

ieee symposium on high-performance computer architecture

作者： Ziming Yuan Lei Dai Wen Li Jie Zhang Shengwen Liang Ying Wang Cheng Liu Huawei Li Xiaowei Li Jiafeng Guo Peng Wang Renhai Chen Gong Zhang State Key Lab of Processors Institute of Computing TechnologyCAS University of Chinese Academy of Sciences School of Computer and Information Technology Shanxi University School of Computer Science Peking University Zhongguancun National Laboratory Beijing Key Lab of Network Data Science and Technology Institute of Computing Technology CAS Huawei Technologies Co. Ltd. China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Neural Vector Search (NVS) has exhibited superior search quality over traditional key-based strategies for information retrieval tasks. An effective NVS architecture requires high recall, low latency, and high throughput to enhance user experience and cost-efficiency. However, implementing NVS on existing neural network accelerators and vector search accelerators is sub-optimal due to the separation between the embedding stage and vector search stage at both algorithm and architecture levels. Fortunately, we unveil that Product Quantization (PQ) opens up an opportunity to break separation. However, existing PQ algorithms and accelerators still focus on either the embedding stage or the vector search stage, rather than both simultaneously. Simply combining existing solutions still follows the beaten track of separation and suffers from insufficient parallelization, frequent data access conflicts, and the absence of scheduling, thus failing to reach optimal recall, latency, and throughput. To this end, we propose a unified and efficient NVS accelerator dubbed NeuVSA based on algorithm and architecture co-design philosophy. Specifically, on the algorithm level, we propose a learned PQ-based unified NVS algorithm that consolidates two separate stages into the same computing and memory access paradigm. It integrates an end-to-end joint training strategy to learn the optimal codebook and index for enhanced recall and reduced PQ complexity, thus achieving smoother acceleration. On the architecture level, we customize a homogeneous NVS accelerator based on the unified NVS algorithm. Each sub-accelerator is optimized to exploit all parallelism exposed by unified NVS, incorporating a structured index assignment strategy and an elastic on-chip buffer to alleviate buffer conflicts for reduced latency. All sub-accelerators are coordinated using a hardware-aware scheduling strategy for boosted throughput. Experimental results show that the joint training strategy improves recall

关键词： Training Quantization (signal) Philosophical considerations Graphics processing units computer architecture Throughput Vectors User experience System-on-chip Indexes

来源：评论

学校读者我要写书评

暂无评论

Implementation of InceptionV3 Model for Skin Disease Detection and Classification 6

Implementation of InceptionV3 Model for Skin Disease Detecti...

引用

6th international Conference on Mobile computing and Sustainable Informatics, ICMCSI 2025

作者： Reddy, Kunam Subba Ayyavaraiah, Monelli Lalithadevi, B. Mohanadevi, A. Sagili, Sreenivas Reddy Bharathi, V.C. Department of CSE Rajeev Gandhi Memorial College of Engineering& Technology Nandyal India Department of Computer Science and Engineering Sathyabama Institute of Science and Technology Chennai India Department of IT Kongunadu College of Engineering and Technology India Department of computer science Rochester Institute Of Technology 1 Lomb Memorial Drive RochesterNY14623 United States School of Computer Science and Engineering VIT-AP University Andhra Pradesh Amaravati India

ISBN: (纸本)9798331522667

Skin disorders represent a significant worldwide health issue, and timely diagnosis and classification are necessary for effective treatment. In this work, we present an improved approach for the identification and recognition of skin illnesses using a DL based system. Using the powerful Inception V3 convolutional neural network architecture, we propose a new method. The novel work specifies in the diagnosis and classification of a broad variety of skin disorders, counting normal skin as well as rashes, melanoma, keloid, measles, chickenpox, monkeypox, and basal cell carcinoma. The Inception V3 model is trained using a dataset that contains annotated samples of diverse skin conditions. Images of skin lesions are then preprocessed to add more features. The pretrained Inception V3 network is transfer learning-tuned to our specific task, enabling it to learn the discriminative characteristics required for skin condition identification. During the training phase, the algorithm learned to extract complicated patterns and information from photographs of skin lesions, which allows it to identify between various skin illnesses with excellent accuracy. We employ techniques like proposed data augmentation to expand the representation capability to simplify while lowering overfitting. Various test datasets are utilized for validation in direction to assess the trained representation accuracy in real-world scenarios. Our tests' results demonstrate how effectively the recommended approach may accurately diagnose and classify a range of skin problems. Among the notable performance measures the algorithm achieves across a range of classes are high accuracy, sensitivity, and specificity. The model is shown to have superior performance and shows potential for clinical applications through cross-validation and comparison with existing methods to evaluate its resilience. © 2025 ieee.

关键词： Convolutional neural networks

来源：评论

学校读者我要写书评

暂无评论

The Importance of Generalizability in Machine Learning for Systems

The Importance of Generalizability in Machine Learning for S...

引用

ieee symposium on high-performance computer architecture

作者： Varun Gohil Sundar Dev Gaurang Upasani David Lo Parthasarathy Ranganathan Christina Delimitrou Massachusetts Institute of Technology USA Google USA

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Using machine learning (ML) to tackle computer systems tasks is gaining popularity. One of the shortcomings of such ML-based approaches is the inability of models to generalize to out-ofdistribution data i.e., data whose distribution is different than the training dataset. We showcase that this issue exists in cloud environments by analyzing various ML models used to improve resource balance in Google’s fleet. We discuss the trade-offs associated with different techniques used to detect out-of-distribution data. Finally, we propose and demonstrate the efficacy of using Bayesian models to detect the model’s confidence in its output when used to improve cloud server resource balance.

关键词： Training Analytical models Computational modeling Machine learning computer architecture Data models Bayes methods Servers

来源：评论

学校读者我要写书评

暂无评论

Interleaved Logical Qubits in Atom Arrays

Interleaved Logical Qubits in Atom Arrays

引用

ieee symposium on high-performance computer architecture

作者： Joshua Viszlai Sophia Lin Siddharth Dangwal Conor Bradley Vikram Ramesh Jonathan Baker Hannes Bernien Frederic T. Chong University of Chicago University of Texas Austin

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Neutral atom arrays have seen exciting progress as a platform for quantum computation. However, as we move towards the regime of fault-tolerance, the large-scale impact of fundamental features in these systems is not well-studied. In this work we point out that the use of movement in neutral atom arrays may set an unavoidable constraint on the speed of computation, erasing potential quantum advantage. As one solution, we propose a movement-free QEC architecture based on groups of interleaved surface codes. Our architecture enables fast, high-fidelity transversal CNOTs on surface codes in the same group. We also introduce interleaved lattice surgery to create high-capacity routing channels between groups. We validate our architecture through detailed numerical simulations of the underlying circuits and we evaluate its scalability through compilation of key benchmark applications. In regimes of high parallelism, we find our architecture leads to a $\sim 3 \times$ reduction in compute time. Our architecture leverages experimentally demonstrated dualspecies atom arrays which exhibit asymmetric interaction strengths that scale with $1 / r^architecture$ for interspecies interactions and with $1 / r^architecture$ for standard, intraspecies interactions. We examine how such scalings enable interleaving with high fidelity and propose how error rates required for QEC could be achieved. We also evaluate the tolerance of our architecture to two-qubit gate fidelities. We find the advantage of interleaving admits sizable tolerances of $\sim 1 \times$ to $3 \times$ increase in error rates. We conclude the benefits of our proposed interleaved architecture grants strong motivation for future experimental efforts targeting longer range dual-species gates.

关键词： Codes Qubit Surgery Lattices computer architecture Logic gates Parallel processing Routing Standards Logic arrays

来源：评论

学校读者我要写书评

暂无评论

UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing architectures

UniNDP: A Unified Compilation and Simulation Tool for Near D...

引用

ieee symposium on high-performance computer architecture

作者： Tongxin Xie Zhenhua Zhu Bing Li Yukai He Cong Li Guangyu Sun Huazhong Yang Yuan Xie Yu Wang Dept. of EE BNRist Tsinghua University HKUST Institute of Microelectronics Chinese Academy of Sciences Capital Normal University Peking University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Near DRAM Processing (NDP) architectures have emerged to be a promising solution for commercializing in-memory computing and addressing the “memory wall” problem, especially for the memory-intensive machine learning (ML) workloads. In NDP architectures, the Processing Units (PUs) are distributed next to different memory units to exploit the high internal bandwidth. Therefore, in order to fully utilize the bandwidth advantage of NDP architectures for ML applications, meticulous evaluations and optimizations of data placement in DRAM and workload scheduling among different PUs are required. However, existing simulation and compilation tools face two insuperable obstacles to achieving these targets. On the one hand, tools for traditional von Neumann architectures only focus on the data access behaviors between the host and DRAM and treat DRAM as a whole part, which cannot support NDP architectures with multiple independent processing and memory units working simultaneously. On the other hand, existing NDP simulators and compilers are designed for specific DRAM technology and NDP architecture, lacking compatibility for various NDP architectures. In order to overcome these challenges and optimize data mapping and workload scheduling for different NDP architectures, we propose UniNDP, a unified NDP compilation and simulation tool for ML applications. Firstly, we propose a unified tree-based NDP hardware abstraction and the corresponding instruction set, enabling the support for various NDP architectures based on different DRAM technologies. Secondly, we design a cycle-accurate and instruction-driven NDP simulator to evaluate hardware performance by accurately tracking the working status of memory elements and PUs. The accurate simulation can provide effective guidance for compilation. Thirdly, we design an NDP compiler that optimizes data partition, mapping, and workload scheduling in different DRAM hierarchies. Furthermore, to enhance the compilation efficiency, we propo

关键词： Hands Instruction sets Random access memory computer architecture Bandwidth Machine learning In-memory computing Hardware Timing Optimization

来源：评论

学校读者我要写书评

暂无评论

Edge-Centric IoT Health Monitoring: Optimizing Real-Time Responsiveness, Data Privacy, and Energy Efficiency 6

Edge-Centric IoT Health Monitoring: Optimizing Real-Time Res...

引用

6th international Conference on Mobile computing and Sustainable Informatics, ICMCSI 2025

作者： Swathi, B. Veerabomma, Supraja Archana, M. Bhadru, Dharavath Somu, Naga Lakshmi Bhavsingh, M. Dept of CSE G Pulla Reddy Engineering College A.P. Kurnool India Department of ECE G Pullaiah College of Engineering and Technology A.P. Kurnool India Department of Computer Science and Engineering CVR College of Engineering Vasthunagar Hyderabad India CSE Department NarSimha Reddy Engineering college Telangana Maisammaguda India Shri Jagdishprasad Jhabarmal Tibrewala University Rajasthan Jhunjhunu India Department of CSE Ashoka Women’s Engineering College Andhra Pradesh Kurnool India

ISBN: (纸本)9798331522667

The innovation of IoT and edge computing has significantly advanced real-time health monitoring systems by providing timely data processing, improved responsiveness, and enhanced data privacy. This study introduces the Edge-Centric IoT Health Monitoring System (EC-HMS), which overcomes limitations observed in cloud-based and hybrid models, including high latency, data privacy vulnerabilities, and excessive energy consumption. EC-HMS leverages localized edge processing to reduce latency, safeguard sensitive data, and optimize energy efficiency, thereby enabling real-time health interventions. The proposed architecture integrates data acquisition, filtering, and anomaly detection at the edge layer, facilitating immediate decision-making and secure data transmission. Experimental evaluations highlight that EC-HMS achieves a 50 ms average latency, consumes 40% less energy compared to cloud-based systems, and ensures robust privacy through localized data handling. This research contributes to the advancement of scalable, responsive, and secure healthcare monitoring frameworks suitable for remote and resource-constrained environments. Future enhancements aim to incorporate predictive analytics and synchronization mechanisms to improve performance and adaptability further. © 2025 ieee.

关键词： Electronic health record

来源：评论

学校读者我要写书评

暂无评论

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Spa...

引用

ieee symposium on high-performance computer architecture

作者： Fangxin Liu Shiyuan Huang Ning Yang Zongwu Wang Haomin Li Li Jiang Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai Qi Zhi Institute

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

As deep learning models continue to grow larger and more complex, exploiting sparsity is becoming one of the most critical areas for enhancing efficiency and scalability. Several methods for leveraging sparsity have been proposed to more effectively balance the trade-off between compression ratio and accuracy. While these methods offer algorithmic advantages, they also introduce significant hardware overhead due to index-based encoding and decoding. In this paper, we propose CROSS, an end-to-end compilation optimization technique to achieve sparse DNN acceleration using GPU computation kernels. The key insight behind CROSS is to exploit parameter distribution locality and reconcile the “sparse” DNN computation with the high-performance “dense” computation kernels. Specifically, we perform an in-depth analysis of sparse operations in mainstream DNN computing frameworks. We then decompose the sparse workload into multiple components to create highly efficient, specialized operators with different sparsity levels. Additionally, we introduce a novel sparse graph translation technique to facilitate computation kernel processing of the sparse workload. The resulting CROSS framework can accommodate various sparsity patterns and optimization techniques, delivering an average $2.03 \times$ speedup on inference latency compared to seven state-of-the-art solutions with smaller memory footprints across various models and datasets.

关键词： Translation Scalability Graphics processing units performance gain Hardware Encoding Computational efficiency Sparse matrices Kernel Optimization

来源：评论

学校读者我要写书评

暂无评论

A Heterogeneous System With computing in Memory Processing Elements to Accelerate CNN Inference

引用

ieee TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Wang, Jinkai Chen, Youxiang Wang, Zekun Gu, Zhengkun Zhang, Bojun Qiu, Haiming Zhang, Kun Zhao, Weisheng Zhang, Yue Beihang Univ Fert Beijing Inst Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China Beihang Univ Hefei Innovat Res Inst Nanoelect Sci & Technol Ctr Hefei 230013 Peoples R China

computing in memory (CIM) is one of the promising solutions to improve computing performance by integrating logic in memory. This work presents an efficient heterogeneous system based on the ultrafast CIM architecture (HS-CIM) to accelerate convolutional neural network (CNN) inference. First, an ultrafast CIM architecture is proposed based on the static random access memory (SRAM) by utilizing the novel total input and full digital scheme to implement multiply-and-accumulate (MAC) operation, which effectively addresses the high delay issue caused by high-precision computing in CIM architecture. Second, a heterogeneous system based on the proposed CIM architecture (HS-CIM) has been constructed with an aligned global cache and an adaptive pruning scheme to eliminate performance degradation and accuracy loss caused by input data bandwidth limitations. Meanwhile, efficient input data and weight data mapping schemes are proposed to minimize the delay and energy caused by input data transmission from the cache to the CIM architecture, thus realizing efficient CNN inference in the HS-CIM system. Finally, we analyze the performance of HS-CIM at the layout level by implementing the LeNet-5 and VGG models of CNN to recognize the image of MNIST and CIFAR-10 datasets, respectively. Results show that the energy efficiency of the proposed CIM architecture achieves 58.32 TOPS/W with 8-bit input/weight precision. Meanwhile, the inference accuracy of the HS-CIM system for MNIST and CIFAR-10 is 99.25% and 92.34%, respectively.

关键词： computer architecture Common Information Model (computing) Delays Voltage Discharges (electric) Convolutional neural networks Random access memory Convolution Transistors performance evaluation computing in memory (CIM) heterogeneous system SRAM CNN

来源：评论

学校读者我要写书评

暂无评论

MeHyper: Accelerating Hypergraph Neural Networks by Exploring Implicit Dataflows

MeHyper: Accelerating Hypergraph Neural Networks by Explorin...

引用

ieee symposium on high-performance computer architecture

作者： Wenju Zhao Pengcheng Yao Dan Chen Long Zheng Xiaofei Liao Qinggang Wang Shaobo Ma Yu Li Haifeng Liu Wenjing Xiao Yufei Sun Bing Zhu Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computing National University of Singapore Singapore School of Computer Electronics and Information Guangxi University NanNing China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Hypergraph Neural Networks (HGNNs) are increasingly utilized to analyze complex inter-entity relationships. Traditional HGNN systems, based on a hyperedge-centric dataflow model, independently process aggregation tasks for hyperedges and vertices, leading to significant computational redundancy. This redundancy arises from recalculating shared information across different tasks. For the first time, we identify and harness implicit dataflows (i.e., dependencies) within HGNNs, introducing the microedge concept to effectively capture and reuse intricate shared information among aggregation tasks, thereby minimizing redundant computations. We have developed a new microedge-centric dataflow model that processes shared information as fine-grained microedge aggregation tasks. This dataflow model is supported by the Read-Process-Activate-Generate execution model, which aims to optimize parallelism among these tasks. Furthermore, our newly developed MeHyper, a microedge-centric HGNN accelerator, incorporates a decoupled pipeline for improved computational parallelism and a hierarchical feature management strategy to reduce off-chip memory accesses for large volumes of intermediate feature vectors generated. Our evaluation demonstrates that MeHyper substantially outperforms the leading CPUbased system PyG-CPU and the GPU-based system HyperGef, delivering performance improvements of $1,032.23 \times$ and $10.51 \times$, and energy efficiencies of $1,169.03 \times$ and $9.96 \times$, respectively.

关键词： Computational modeling Neural networks Redundancy Pipelines Memory management Parallel processing Vectors Energy efficiency Hardware acceleration

来源：评论

学校读者我要写书评

暂无评论

Are GAFs All you Need for BCIs?

Are GAFs All you Need for BCIs?

引用

ieee international symposium on Biomedical Imaging

作者： Hernandez Gomez A. Nieto N. Podesta M. O. Felix F. Munoz L. A. School of Engineering and Sciences Tec de Monterrey Monterrey N.L. México

ISBN: (数字)9798331520526

ISBN: (纸本)9798331520533

This study presents a proposal of Learnable Gramian Angular Fields (LGAFs), for Brain-computer Interface (BCI) performance in visual-motor intention classification. We introduce LGAFs with a convolutional neural network (CNN), achieving 93.06% accuracy across six hand movements. The architecture transforms time-series EEG data into optimized two-dimensional representations while utilizing CNNs' efficiency for real-time applications. Through experimentation on four subjects, we validate the model's capability to maintain consistent classification accuracy across movement types. The results demonstrate the LGAF-CNN combination's high performance and potential computational efficiency, establishing its potential for practical BCI applications. Through ablation studies and performance analysis, the architecture achieved comparable accuracy with only three optimally selected channels.

关键词： Electric potential Accuracy computer architecture Transforms Electroencephalography Brain-computer interfaces Real-time systems performance analysis Convolutional neural networks Proposals

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：