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检索条件"任意字段=IEEE International Symposium on Computer-Aided Control System Design"

共 7946 条记录，以下是151-160 订阅

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Edge Cache and Computing Resource Migration Strategy for New Power systems 5

Edge Cache and Computing Resource Migration Strategy for New...

引用

5th international Conference on Artificial Intelligence and computer Engineering, ICAICE 2024

作者： Xu, Yuefei Jia, Fengru Chen, Yunlong Xu, Yinfei Hangzhou Electric Power Equipment Manufacturing Co. Ltd Hangzhou China

ISBN: (纸本)9798331528911

With the development of power system with new energy as the main body, the characteristics of distribution are obvious, and the number of terminal equipment increases sharply. The scheduling and control of massive power loads are faced with problems such as high delay and insufficient computing efficiency. It is urgent to build an efficient communication network to effectively improve the operating efficiency and reliability of the power system. The existing work focuses on the integration of edge computing technology and power system, but does not consider the joint optimization of service cache and VM migration in edge network resource management. In order to solve these problems, a three-layer edge network architecture consisting of multiple devices, edge servers and power cloud centers is proposed by considering the factors of device transmission power, server computing and storage resources. Meanwhile, based on the task unloading model, service cache model and VM migration model, a resource allocation strategy combining service cache and VM migration is proposed to improve the system performance. Aiming at the coupling problem of service cache and VM migration joint optimization, the original problem was decoupled into two sub-problems for iterative solution, so as to achieve better resource allocation effect. The simulation results further prove that the proposed strategy has better performance and can obtain lower task processing delay compared with other schemes. © 2024 ieee.

关键词： Power systems computer aided design

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HAAC: A Hardware-Software Co-design to Accelerate Garbled Circuits 23

HAAC: A Hardware-Software Co-Design to Accelerate Garbled Ci...

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50th Annual international symposium on computer Architecture (ISCA)

作者： Mo, Jianqiao Gopinath, Jayanth Reagen, Brandon NYU New York NY 10003 USA

ISBN: (纸本)9798400700958

Privacy and security have rapidly emerged as priorities in system design. One powerful solution for providing both is privacy-preserving computation, where functions are computed directly on encrypted data and control can be provided over how data is used. Garbled circuits (GCs) are a PPC technology that provide both confidential computing and control over how data is used. The challenge is that they incur significant performance overheads compared to plaintext. This paper proposes a novel garbled circuits accelerator and compiler, named HAAC, to mitigate performance overheads and make privacy-preserving computation more practical. HAAC is a hardware-software co-design. GCs are exemplars of co-design as programs are completely known at compile time, i.e., all dependence, memory accesses, and control flow are fixed. The design philosophy of HAAC is to keep hardware simple and efficient, maximizing area devoted to our proposed custom execution units and other circuits essential for high performance (e.g., on-chip storage). The compiler can leverage its program understanding to realize hardware's performance potential by generating effective instruction schedules, data layouts, and orchestrating off-chip events. In taking this approach we can achieve ASIC performance/efficiency without sacrificing generality. Insights of our approach include how co-design enables expressing arbitrary GCs programs as streams, which simplifies hardware and enables complete memory-compute decoupling, and the development of a scratchpad that captures data reuse by tracking program execution, eliminating the need for costly hardware managed caches and tagging logic. We evaluate HAAC with VIP-Bench and achieve an average speedup of 589x with DDR4 (2,627x with HBM2) in 4.3mm(2) of area.

关键词： cryptography hardware acceleration

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Multi-Level Intelligent control system For Inter-Vehicle Communication Between Smart Traffic Lights With computer Vision and Autonomous Electric Vehicles

Multi-Level Intelligent Control System For Inter-Vehicle Com...

引用

2024 international symposium on Sensing and Instrumentation in 5G and IoT Era, ISSI 2024

作者： Mansurova, Madina Belgibayev, Baurzhan Abdrakhim, Sanzhar Didar, Moldakhmetov Baigarayeva, Zhanel Sarsembayeva, Talshyn Boltaboyeva, Assiya Al-Farabi Kazakh National University Artificial Intelligence and Big Data Almaty Kazakhstan The Hong Kong Polytechnoc University Hong Kong Hong Kong

ISBN: (纸本)9798350378689

The article presents materials, methods, and results obtained from the modernization and improvement of the Abay/Saina transport interchange in the metropolis of Almaty to the level of an IoT (Internet of Things) transport object with AI (Artificial Intelligence). This approach is an important practical and relevant task within the framework of the Smart City Almaty concept. The developed hardware and software complex (HSC) allows transforming the existing hybrid analog-digital system for monitoring and telemetric control of traffic lights on Abay Avenue into a modern digital intelligent control system. The presented software and circuit design solutions allow creating a neuro-physical digital twin of the Abay/Saina interchange. The semi-industrial prototype of the mobile PC (Personal computer) server and traffic light objects with streaming neural video vision have significant practical importance for the widespread implementation of electric taxis with autopilots into the transport infrastructure of the Republic of Kazakhstan. © 2024 ieee.

关键词： Personal computers

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FPGA-based Implementation for Industrial Motion control system

FPGA-based Implementation for Industrial Motion Control Syst...

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1st international Conference on Smart Energy systems and Artificial Intelligence (SESAI)

作者： Rubattu, Claudio Ledda, Antonio Ratto, Francesco Jugade, Chaitanya Goswami, Dip Palumbo, Francesca Univ Sassari I-07100 Sassari Italy Univ Cagliari I-09123 Cagliari Italy Eindhoven Univ Technol NL-5612 AZ Eindhoven Netherlands

ISBN: (纸本)9798350364613;9798350364606

In these years of severe chip shortage, it is even more important to improve the efficiency of chip manufacturing. As is well known, manufacturing phases rely on increasingly intelligent production machinery, which must ensure high quality and large volumes. That is true also for die-bonding machines, which are required to satisfy very high standards of speed and accuracy. For this purpose, such devices have started to evaluate the possibility of adopting computer vision algorithms for automatic recognition of wafer positioning and die size. This paper proposes an FPGA accelerated implementation of one of these algorithms, demonstrating the advantages of using this technology to this end and paving the way towards a larger adoption of this kind of acceleration platform for the different tasks composing modern industrial motion control systems. At the state of the art, such systems are typically managed with software-oriented solutions, which may not be sufficient in the case of highly restrictive requirements in terms of execution time. For this reason, the design flow considered the use of high-level hardware design, which offers a more software-friendly solution to developers without in-depth hardware knowledge. The proposed solution is a state-of-the-art implementation for execution time and resources of prograimnable logic, while enabling higher precision in terms of die position estimation.

关键词： FPGA High-Level Synthesis Industrial Motion control system MPSoCs

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Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective control using Secure Fingerprint Template 36

Fault Secured JPEG-Codec Hardware Accelerator with Piracy De...

引用

36th ieee international symposium on Defect and Fault Tolerance in VLSI and Nanotechnology systems, DFT 2023

作者： Chaurasia, Rahul Reddy Asireddy, Abhinav Sengupta, Anirban Indian Institute of Technology Computer Science and Engineering Indore India Indian Institute of Technology Department of Computer Science and Engineering Indore India Indian Statistical Institute Advanced Computing and Microelectronics Unit Kolkata India

ISBN: (纸本)9798350315004

This paper presents a novel methodology to design fault secured JPEG-compression-decompression (codec) hardware accelerator with piracy detective control using secure fingerprint template of intellectual property (IP) vendor. In the proposed approach, firstly, the fault secured schedule for JPEG-codec design is generated from its behavioral description. Subsequently, in order to enable detective control against piracy, secure digital template corresponding to fingerprint biometric of IP vendor is generated and implanted into the design. In order to do so, firstly, fingerprint features are transformed based on IP vendor specified key-set. Subsequently, the generated secure fingerprint template in the form of encoded hardware security constraints is implanted into the design during behavioral/ high-level synthesis phase of integrated circuit (IC) design. The implanted hardware security constraints thereby ensure the seamless detection and isolation of fake/pirated design versions during piracy detection process, before their conjunction into system on chip (SoC) of electronic systems. The proposed approach achieves the following: i) fault secured hardware accelerator for JPEG-codec with integrated piracy detective control at negligible design cost overhead ii) higher resiliency against tampering attack and iii) lower probability of coincidence (indicating definitive proof of ownership for genuine IP vendor). © 2023 ieee.

关键词： Fault detection

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Substructure-Preserving Generalization for on-site robotic construction planning 9

Substructure-Preserving Generalization for on-site robotic c...

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9th international symposium on computer and Information Processing Technology, ISCIPT 2024

作者： Yi, Yang Lu, Yu Zhu, Wenjun Zhang, Mengyi Mu, Yimin Chellali, Ryad Nanjing Tech University College of Electrical Engineering and Control Science Nanjing China

ISBN: (纸本)9798350388404

Generalizing construction task planning is crucial for autonomous robots entering onsite environments and working efficiently. Yet a fundamental question for applications is how the generalizing of a learned model to universe tasks and environment settings. We proposed a generalized construction planning approach based on offline reinforcement learning. The idea is to learn unified shape connections and semi-stable substructures to realize composition generalization. We demonstrated the usefulness of incorporating sub-graphs to edge-wise features for semi-stable sub-structure segmentation. By sampling in the spaces of the tasks prior, the conditional distribution of context information is modeled by leveraging a causally masked Transformer. We tackle the issue that a robot autonomously learns to design and construct a bridge from varying-sized blocks and random construction requirements. It maintains a high success rate (86%) of task planning in unseen contexts as well as rearrangement ability to increase an automated system's effectiveness. © 2024 ieee.

关键词： Reinforcement learning

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design of a Virtual-Physical Hybrid Simulation system for FANET 4

Design of a Virtual-Physical Hybrid Simulation System for FA...

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4th international symposium on computer Technology and Information Science, ISCTIS 2024

作者： Wang, Dalun Li, Xu Beijing Jiaotong University School of Electronic and Information Engineering Beijing China

ISBN: (纸本)9798350354560

Unmanned swarms are intelligent systems composed of various unmanned systems, control systems, and human-machine interfaces, achieving coordinated tasks through information interaction and feedback. They are widely used in disaster rescue, field exploration, resource surveying, anti-piracy operations, and military applications. The Flying Ad Hoc Network (FANET) communication protocol is fundamental to the coordination of unmanned swarms but requires reliability validation before deployment. Current simulation and physical validation methods have limitations: simulation validation is cost-effective but less credible, while physical validation is highly credible but costly and complex. Hybrid simulation validation systems, combining virtual simulation with a few physical tests, leverage the advantages of both methods for efficient validation. This paper proposes a hybrid validation platform for FANET communication protocols, investigating key technologies such as hybrid message management and time synchronization. The platform's credibility is tested by implementing the MAC layer protocol. © 2024 ieee.

关键词： Ad hoc networks

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LSTM Neural Network Based on Moving Average Filtering Optimization Assisted Navigation Methods

LSTM Neural Network Based on Moving Average Filtering Optimi...

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2023 international Conference on computer Applications Technology, CCAT 2023

作者： Zhu, Xinyu Li, Yitong Aviation Electronics and Electrical Engineering Institute Civil Aviation Flight University of China Chengdu China

ISBN: (纸本)9798350301540

Strapdown Inertial Navigation (SINS) systems used by civil aircraft usually integrate global positioning system (GPS) integrated navigation, but when GPS signals are missing, continuous aircraft track information will be lost. To solve this problem, this paper proposes a long and short term memory network (LSTM) aided navigation method based on moving average filtering optimization. This method can predict aircraft tracks independently of the navigation system. design simulation experiments and control experiments to test the network performance. The experimental results show that the LSTM neural network aided navigation method based on moving average filtering optimization has a promising application prospect. © 2023 ieee.

关键词： Global positioning system

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Secure two-way communications between UAVs and control center in IoV 5G communication 27

Secure two-way communications between UAVs and control cente...

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27th international Workshop on computer aided Modeling and design of Communication Links and Networks (CAMAD)

作者： Andreou, Andreas Mavromoustakis, Constandinos X. Batalla, Jordi Mongay Markakis, Evangelos Mastorakis, George Pallis, Evangelos Univ Nicosia Dept Comp Sci Nicosia Cyprus Univ Nicosia Res Fdn Nicosia Cyprus Warsaw Univ Technol Warsaw Poland Hellen Mediterranean Univ Dept Elect & Comp Engn Iraklion Greece Hellen Mediterranean Univ Dept Management Sci & Technol Iraklion Greece Univ West Attica Sch Engn Dept Ind Design & Prod Engn Athens Greece

ISBN: (数字)9781665461290

ISBN: (纸本)9781665461290

Integration of UAVs into the fifth generation (5G) cellular networks as aerial base stations would be a promising technology to achieve several goals, namely ubiquitous accessibility, robust navigation, ease of monitoring and management. Real-time distribution of critical information must be embedded throughout transport infrastructure. The ability of Unmanned Aerial Vehicles (UAVs) with high agility, mobility, and flexibility to offload data traffic from terrestrial base stations and Road Side Units (RSUs) by providing additional access points enables swift, accurate, timely and actionable decisions in Intelligent Transportation system (ITS) based on data-driven insights. However, we must ensure secure data exchange when multi-purpose RSU is deployed for confidential data acquisition and distribution. It is a prerequisite for data sovereignty in the Internet of Vehicles (IoV) network to be facilitated by secure data exchange between trusted parties. Therefore, we propose a robust encryption method to incentivize data exchange within the ITS ecosystem to enable confidential data sharing in IoV communication. In addition, the novel encryption method we present enables realtime, encryption and decryption for ciphertexts containing confidential information between UAVs and the control center.

关键词： UAV cryptography IoV Intelligent Transportation system ITS

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design of High Reliable Bus Communication for a Dual Redundancy Servo control Driver 7

Design of High Reliable Bus Communication for a Dual Redunda...

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2023 7th international symposium on computer Science and Intelligent control, ISCSIC 2023

作者： He, Yufeng Sun, Sixian Lin, Qiangqiang Han, Shuyue Li, Zhiguo Li, Zhenshan Beijing Research Institute of Precise Mechatronic Controls Beijing China

ISBN: (纸本)9798350342987

In servo control drivers with high reliability requirements, redundancy design is an important factor in ensuring system reliability, and a reasonable communication scheme is the key to maximizing the effectiveness of the redundancy channels. This article designs a communication scheme based on 1553B and FlexRay two-layer buses for a dual redundancy six channels servo control driver, and provides a detailed introduction to the ideas and protocol implementation of using FlexRay bus as secondary bus communication. The feasibility, real-Time performance, and reliability of this communication scheme have been proven through communication testing on the FlexRay bus. This communication scheme provides a new idea for the redundancy design of highly reliable servo control drivers, and also provides a successful case for the application of Flexray bus protocol in the servo field. © 2023 ieee.

关键词： Redundancy

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