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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Assessing the Role of Communication in Scalable Multi-core Quantum Architectures 17

Assessing the Role of Communication in Scalable Multi-Core Q...

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17th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2024

作者： Palesi, Maurizio Russo, Enrico Patti, Davide Ascia, Giuseppe Catania, Vincenzo University of Catania Catania Italy

ISBN: (纸本)9798331530471

Multi-core quantum architectures offer a solution to the scalability limitations of traditional monolithic designs. However, dividing the system into multiple chips introduces a critical bottleneck: communication between cores. This paper introduces qcomm, a simulation tool designed to assess the impact of communication on the performance of scalable multi-core quantum architectures. Qcomm allows users to adjust various architectural and physical parameters of the system, and outputs various communication metrics. We use qcomm to perform a preliminary study on how these parameters affect communication performance in a multi-core quantum system. © 2024 ieee.

关键词： Quantum computers

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Leveraging On-chip DRAM Stacking in an embedded 3D Multi-core DSP system

Leveraging On-chip DRAM Stacking in an Embedded 3D Multi-Cor...

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54th ieee international Midwest symposium on Circuits and systems (MWSCAS)

作者： Zhang, Tao Hsu, Po-Yang Lo, Wei-Heng Tseng, Shau-Yin Wu, Yi-Ta Liu, Chuan-Nan Yeh, Jen-Chieh Hwang, Tingting Xie, Yuan Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Natl Tsing Hua Univ Dept Comp Sci & Engn Hsinchu 30013 Taiwan ITRI Hsinchu Taiwan

ISBN: (纸本)9781612848570

embedded multi-core systems are gaining popularity for many embedded applications. Compared to the multi-core design for general purpose high performance computing, the memory design for an embedded multi-core processor should be customized and adapt to embedded application's characteristics, because it usually has significant impact on the system performance. In this paper, we study a 3D embedded multi-core DSP processor called 3D-iSPA, which is targeted for multimedia applications with two unique design features and leverages 3D DRAM stacking to improve performance. many memory controller and wider memory data bus are proposed to make better use of the vertical through-silicon-via ( TSV). The experimental results shows that duplicating memory controller can provide 10X speedup. The pure wider memory bus, however, has weak impact on the performance due to the limitation of on-chip interconnect.(1)

关键词： 3D DRAM stacking 3D-iSPA DRAM chips Encoding Multimedia communication Random access memory Stacking Three dimensional displays Through-silicon vias Vehicles digital signal processing chips embedded 3D multicore DSP system embedded multicore processor multimedia applications multiprocessing systems on-chip DRAM stacking three-dimensional integrated circuits through-silicon-via

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Modular Memory system for RISC-V Based MPSoCs on Xilinx FPGAs 13

Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGA...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Kamaleldin, Ahmed Ali, Muhammad Rad, Pedram Amini Gottschalk, Marcus Gohringer, Diana Tech Univ Dresden Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781728148823

Current application domains, like mobile robotics, or internet of things require high computational power associated with low energy consumption. Therefore, MPSoCs are widely used as an adequate platform for high performance embedded computation. Recently, the emergence of RISC-V instruction set architecture drives SoC designers to adopt it in the design of MPSoCs as a cost-free, modular processor and suitable to be implemented in different hardware platforms. Furthermore, these characteristics make the RISC-V an interesting candidate for an FPGA soft-core processor. In this paper, we present a modular hybrid memory system for a lightweight RISC-V based MPSoC architecture. The implementation of the hybrid memory consists of a global scratchpad on-chip shared memory for both instruction and data for the purpose of communication and synchronization between the processing elements. In addition to a tightly coupled memory associated with each processing element for low latency memory access for private computation. Moreover, the complete MPSoC architecture is scalable and configurable, in terms of the number of PEs, shared/private memory sizes and the number of memory mapped peripherals. A benchmarking environment is developed to evaluate the performance of the proposed hybrid memory system in terms of memory access latency and memory bandwidth and their impact on the computation time. The complete MPSoC architecture is implemented and tested on a Xilinx Zynq 7000 FPGA device.

关键词： Multiprocessor system-on-chip (MPSoC) RISC-V Field Programmable Gate Array (FPGA) Tightly Coupled Memory (TCM)

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A cost/power efficient storage system with directly connected FPGA and SATA disks 16

A cost/power efficient storage system with directly connecte...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Niwase, Ryohei Harasawa, Hikaru Yamaguchi, Yoshiki Kaijie, Wei Amano, Hideharu Univ Tsukuba 1-1-1 Ten Ou Dai Tsukuba Ibaraki 3058573 Japan Kumamoto Univ 2-39-1 Kurokami Chuo Ku Kumamoto Kumamoto 8608555 Japan Keio Univ 3-14-1 Hiyoshi Kohoku Ku Yokohama Kanagawa 2228522 Japan

ISBN: (纸本)9798350393613

Providing large storage on Multi-Access Edge (MEC) devices has various advantages: A large amount of bare data that cannot transfer to the cloud without anonymization can be kept easily. Preprocessing in the MEC devices is a hopeful approach for making "well-selected data" for training AI algorithms on the cloud. By distributing big data across numerous base stations, it is possible to prevent data loss during times of disaster. For such purpose, we propose the Trefoil storage subsystem supports cost and power-efficient stand-alone storage by connecting FPGA boards and up to 32 SATA Solid-State Drives (SSDs) directly. We introduced LiteX, an open-source FPGA system integration tool, to design the storage system. Various LiteX IP cores, including soft CPU cores(VexRISCv), memory controllers (LiteDRAM), and FPGA interconnect controllers (LiteICLink), are combined as well as the SATA controller(LiteSATA). We built an example evaluation system and evaluated a storage system's performance and power consumption with multiple SATA disks. Our evaluation results show that the designed SATA system can best use the SATA disk's maximum bandwidth, 569.1MB/sec for write operations and 523.8MB/sec for read operations. Striping data access with multiple disks demonstrates almost no overhead for a read operation, while a slight speed decrease of 4.24MB/sec per unit was observed for the write operation. Only 3W for the disk unit is needed during disk access. As an example application, a quantum computer simulation is briefly introduced.

关键词： FPGA Serial ATA LiteX. Scalable Storage

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A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-time Scheduling 12

A Novel Task-to-Processor Assignment Approach for Optimal Mu...

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Duy, Doan Tanaka, Kiyofumi Japan Adv Inst Sci & Technol Sch Informat Sci Nomi Ishikawa Japan

ISBN: (纸本)9781538666890

Recent decades have recognized the popularization of multiprocessor architectures in real time embedded systems. Real-time task scheduling in such systems has become a challenging problem as a result. In this paper, we are presenting an optimal scheduling algorithm, which can successfully schedule any task sets with no deadline miss if the total utilization of tasks does not exceed the capacity of the involved system The proposed algorithm called LLA introduces a so called fixed task scheduling plan for every time interval that is defined as the time period between two consecutive job releases. At the beginning of each interval, LAA makes the scheduling plan by predicting tasks requested amount of execution tune within the interval and then arranging these amounts to processors appropriately respecting to require merits of scheduling. By this approach, LAA can extremely reduce the number of scheduler invocations to the number of job releases. Furthermore, simulation results show that our algorithm has lower time complexity while retaining the schedulabihty, task preemption, and task migration competitive to the existing optimal scheduling algorithms.

关键词： real-time operating system scheduling algorithm multiprocessor runtime overhead

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Enabling Scalable and Fine-Grained Nested Parallelism on embedded many-cores 9

Enabling Scalable and Fine-Grained Nested Parallelism on Emb...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Capotondi, Alessandro Marongiu, Andrea Benini, Luca Univ Bologna DEI I-40126 Bologna Italy Univ Bologna IIS I-40126 Bologna Italy Swiss Fed Inst Technol Zurich ETHZ Zurich Switzerland

ISBN: (纸本)9781479986705

Current high-end embedded systems are designed as heterogeneous systems-on-chip (SoCs), where a general-purpose host processor is coupled to a programmable manycore accelerator (PMCA). Such PMCAs typically leverage hierarchical interconnect and distributed memory with non-uniform access (NUMA). Nested parallelism is a convenient programming abstraction for large-scale cc-NUMA systems, which allows to hierarchically (and dynamically) create multiple levels of fine-grained parallelism whenever it is available. Available implementations for cc-NUMA systems introduce large overheads for nested parallelism management, which cannot be tolerated due to the extremely fine-grained nature of embedded parallel workloads. In particular, creating a team of parallel threads has a cost that increases linearly with the number of threads, which is inherently non scalable. This work presents a software cache mechanism for frequently-used parallel team configurations to speed up parallel thread creation overheads in PMCA systems. When a configuration is found in the cache the cost for parallel team creation has a constant time, providing a scalable mechanism. We evaluated our support on the STMicroelectronics STHORM many-core. Compared to the state-of-the art, our solution shows that: i) the cost for parallel team creation is reduced by up to 67%;ii) the tangible effect on real ultra-fine-grained parallel kernels is a speedup of up to 80%.

关键词： cache storage embedded systems multiprocessing systems parallel programming system-on-chip PMCA STMicroelectronics STHORM many-core SoC distributed memory with nonuniform access embedded many-cores fine-grained parallelism heterogeneous systems-on-chip nested parallelism parallel team configuration parallel thread creation overhead programmable manycore accelerator programming abstraction software cache mechanism Fabrics Instruction sets Message systems Parallel processing Programming Recruitment embedded many-core Architectures OpenMP Parallel Programming Models embedded systems Computer based information systems Parallel programming instruction sets system-on-chip Multiprocessing systems cache storage PARALLEL PROCESSING (COMPUTERS) Programming Textile fabrics parallelism fabric Synclitism THREADS Parallel Lines

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Survey of Network-on-chip (NoC) for Heterogeneous multicore systems 17

Survey of Network-on-Chip (NoC) for Heterogeneous Multicore ...

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17th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2024

作者： Biglari, Siamak Hosseini, Farahnaz Upadhyay, Aadesh Zhao, Hui University of North Texas Department of Computer Science and Engineering United States

ISBN: (纸本)9798331530471

In recent years, Network-on-chip (NoC) has emerged as a promising solution for addressing a critical performance bottleneck encountered in designing large-scale multi-core systems, i.e., data communication. With advancements in chip manufacturing technologies and the increasing complexity of system designs, the task of designing the communication subsystems has become increasingly challenging. The emergence of hardware accelerators, such as GPUs, FPGAs and ASICs, together with heterogeneous system integration of the CPUs and the accelerators creates new challenges in NoC design. Conventional NoC architectures developed for CPU-based multi-core systems are not able to satisfy the traffic demands of heterogeneous systems. In recent years, numerous research efforts have been dedicated to exploring the various aspects of NoC design in hardware accelerators and heterogeneous systems. However, there is a need for a comprehensive understanding of the current state-of-the-art research in this emerging research area. This paper aims to provide a summary of research work conducted in heterogeneous NoC design. Through this survey, we aim to present a comprehensive overview of the current related research, highlighting key findings, challenges, and future directions in this field. © 2024 ieee.

关键词： Network-on-chip

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Design and research of self-balancing bicycle control system 17

Design and research of self-balancing bicycle control system

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17th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2024

作者： Lei, Miao Niguidula, Jasmin Caballero, Jonathan M. Huainan Normal University College of Mechanical and Electrical Engineering Huainan China Technological University of the Philippines College of Industrial Education Manila Philippines

ISBN: (纸本)9798331530471

Aiming at the problem of bicycle self-balancing control, a bicycle self-balancing control system based on momentum wheel is designed and adopted. Firstly, the research status of bicycle self-balancing control system is briefly introduced. Then, the mechanical model of the bicycle system based on inertia wheel is established by Lagrange method, and the cascade PID(Proportional-Integral-Derivative) controller is designed for self-balancing control. The mechanical model and cascade PID controller were simulated by Simulink. The simulation results show that the model is reliable and the cascade PID controller can realize the requirements of bicycle self-balancing control. © 2024 ieee.

关键词： Lagrange multipliers

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Multi-objective Optimisation of RISC-V CV32A6 for ML application 16

Multi-objective Optimisation of RISC-V CV32A6 for ML applica...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hubert, Bastien Hammami, Omar ENSTA Paris Comp Sci & Syst Engn Lab U2IS Palaiseau France

ISBN: (纸本)9798350393613

RISC-V architectures are rapidly gaining in popularity in embedded systems, in which each mW counts. Since AI-related applications such as image recognition or neural networks tend to be highly energy consuming, low-power techniques are required to optimise the autonomy of systems using SoCs to run such applications. However, the trade-off between energy consumption, application performance and resource use requires a multi-objective optimisation with a potentially very important number of optimisation parameters to be performed on the SoC. As they rely on heuristics that are likely to only return locally optimal solutions, empirical methods must be excluded. To address this issue, a technology-agnostic mathematical model is introduced to represent how optimisations are applied to a SoC, and a workflow designed to perform an intelligent exhaustive exploration of the optimisation space has been developed to highlight a subset of optimal processor configurations. Optimisation of the ARIANE/CV32A6 RISC-V processor, running a CNN propagation on a Xilinx Zynq 7020 FPGA, has shown very encouraging results using low degree configurations, and is likely to perform even better with higher degree configurations.

关键词： RISC-V low-power design embedded systems multi-objective optimisation mathematical model floorplanning FPGA simulation

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MITRACA: a next-gen heterogeneous architecture 13

MITRACA: a next-gen heterogeneous architecture

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ben Abdelhamid, Riadh Yamaguchi, Yoshiki Boku, Taisuke Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki Japan Univ Tsukuba Fac Engn Informat & Syst Tsukuba Ibaraki Japan Univ Tsukuba Ctr Comp Sci Tsukuba Ibaraki Japan

ISBN: (纸本)9781728148823

GPU (Graphics Processing Unit) and CPU (Central Processing Unit) possess a sufficient and appropriate performance to compute massively parallel applications like AI, Big data, and material sciences. However, their real performance is far lower than those theoretical ones. The primary reason for the performance degradation is that they suffer from limited memory bandwidth and inefficient interconnection topology not optimized for these types of applications. Thus, from the viewpoint of real computational performance called computational efficiency, FPGA (Field Programmable Gate Array) is now becoming an attractive chip for these types of applications with massively parallel computation. FPGA can efficiently propose optimized communication and bridge different computing accelerators as customized hardware. In other words, FPGA-based hardware accelerators offer a convenient solution for both high performance and high memory bandwidth. However, one serious concern is usability. For example, the FPGA design using hardware description language is a meticulous task and requires specialized skill sets as well as a long time to market. An overlay architecture will become an appropriate candidate that can resolve this issue because it offers a software layer that simplifies FPGA programmability by abstracting the fabric resources. Thus, this article proposes an overlay architecture based on a tightly-connected many-core-based CGRA (Coarse-Grained Reconfigurable Architecture). It will help software engineers on seamlessly implementing their applications. Our final goal is not on the current fine-grained FPGAs but new middle-to-course-grained programmable chips. If an ASIC (Application-Specific Integrated Circuit) implementation was adopted, the performance would achieve at least ten times higher compared with the current FPGA implementation because of the working frequency. In this article, the proposed overlay system provides a programmable interface that virtualizes FPGA res

关键词： FPGA many-core overlay VLIW SIMD CGRA 3D Torus double-precision floating-point

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