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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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A Performance Evaluation of Multi-Programming Model on a multicore system with Virtual Machines 8

A Performance Evaluation of Multi-Programming Model on a Mul...

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8th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Ueno, Hitoshi Cc Ures Off Atsugi Kanagawa Japan

ISBN: (纸本)9781479943050

For a lot of equipment like industrial equipment, automotive or consumer electrical appliances, embedded computers are widely used. many computers are embedded in the equipment because it has excellent features and their controls are more complex. Recently, general purpose microcomputer has been made to have multicore CPUs to achieve high performance. multicore CPU is also expected to be used widely because of embedded computers, but it is not clear how to use the computer. Virtual machine technology is proposed and used as the solution to the problem, as it makes possible the integration of some control computers into a high-performance embedded computer. However, it is not simple for engineers to design the performance of the system because the characteristics of virtual machines are different compared with real machines. In this article, the performance characteristics of multicore embedded computers with virtual machines are analyzed, with an assumption that the control programs are developed by multi-programming model using process or thread of Linux OS. For the evaluations, a benchmark program is designed. The results show a performance difference of 5%-10% between process cases and thread cases, regardless whether real machine or virtual machine is used. In performance comparison of real machine and virtual machine, 13%-88% performance differences are realized, which depend on the number of CPU cores. Furthermore, some unprecedented phenomena in performance are found in cases where the number of CPU cores exceeds the number of parallel executions of process/thread. The measured results are useful and can serve as a guide in designing system performance for multicore embedded computers.

关键词： virtual machine multicore multi-programming process thread Linux performance evaluation supervisor mode

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DRAC: A Dynamically Reconfigurable Active L1 Cache Model for Hybrid Prototyping of multicore embedded systems 25

DRAC: A Dynamically Reconfigurable Acti...

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25th ieee international symposium on Rapid system Prototyping (RSP) - Shortening the Path from Specification to Prototype / embedded systems Week

作者： Barzegar, Ali Saboori, Ehsan Abdi, Samar Concordia Univ Dept Elect & Comp Engn Montreal PQ Canada

ISBN: (纸本)9781479968510

This paper presents a novel dynamically reconfigurable active L1 cache model for hybrid prototyping, called DRAC. The hybrid prototyping technique simulates a multicore embedded system using an emulation kernel on top of a single physical instance of a core. We extend hybrid prototyping by supporting memory hierarchy modeling with DRAC. The presented cache model is a standalone cycle accurate model that is further customized for multicore emulation. DRAC run-time configurability enables the embedded system designer to simulate and explore different multicore design options without the need for full FPGA prototyping. Our experimental results show 2.78% average error and 5.06% worst case error when DRAC is used as a standalone cache model in a single core design. We also observed 100% relative accuracy and less than 13% absolute worst case error in timing estimation when DRAC is used for hybrid prototyping of multicore designs.

关键词： L1 cache modeling multicore Design FPGA Prototyping embedded systems Design

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Portability of Vectorization-aware Performance Tuning Expertise across system Generations 14

Portability of Vectorization-aware Performance Tuning Expert...

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14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Sugawara, Shunpei Shimomura, Yoichi Egawa, Ryusuke Takizawa, Hiroyuki Tohoku Univ Grad Sch Informat Sci Sendai Miyagi Japan Tohoku Univ Cybersci Ctr Sendai Miyagi Japan Tokyo Denki Univ Sendai Miyagi Japan

ISBN: (纸本)9781665438605

Even HPC expert programmers need to invest considerable time and effort in empirically establishing effective performance tuning strategies for their target systems. When the target system is changed and/or updated, it is thus preferable for expert programmers if their performance tuning expertise can be ported to the new system as much as possible. In this paper, we focus on multiple generations of NEC SX series vector systems. We have documented the performance tuning expertise for the previous generations and built a machine-usable database of performance tuning cases. Therefore, this paper investigates how much the recorded expertise in the database can contribute to performance tuning for the latest generation, NEC SX-Aurora TSUBASA (SX-AT). Since the system architecture as well as the software stack such as compilers are totally renewed for SX-AT, this paper discusses the differences in performance tuning across system generations. In addition, this paper also discusses how to express performance tuning techniques in a machine-usable way. The case study in this paper indicates that the Xevolver's approach of using user-defined code transformations can express most of the vectorization-aware performance tuning techniques, and is thus promising for recording the performance tuning expertise in a future-proof fashion.

关键词： Code transformation framework Performance tuning expertise Vector processor Vectorization

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Adaptive Time-Based Least Memory Intensive scheduling 9

Adaptive Time-Based Least Memory Intensive scheduling

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Elhelw, Amr S. El-Moursy, Ali Fahmy, Hossam A. H. Egyptian Financial Supervisory Author Informat Syst Sect Cairo Egypt Univ Sharjah Elect & Comp Engn Dept Sharjah U Arab Emirates Cairo Univ Elect & Commun Dept Cairo Egypt

ISBN: (纸本)9781479986705

DRAM memory is a major resource shared in multi-core system, hence memory requests from different applications interfere with each other. Therefore, different applications running together on the same chip can experience extremely different memory system performance: one application can experience a severe slowdown or starvation while another is unfairly prioritized by the memory scheduler. Existing memory access scheduling techniques try to optimize the overall multi-core system performance and fairness. This paper proposes an effective memory access scheduler, called Adaptive Time-Based Least Memory Intensive scheduling (Adaptive TB-LMI). The goal of the proposed scheduler is to increase the overall system performance and fairness. Adaptive TB-LMI showed an average increase in performance and fairness by 2.5% and 10.2% respectively compared to Time-Based Least Memory Intensive scheduling (TB-LMI) (previous work providing the best system throughput and fairness). Adaptive TB-LMI showed a maximum increase in performance and fairness by 9.65% and 22.16% respectively compared to TB-LMI.

关键词： DRAM chips multiprocessing systems processor scheduling DRAM memory adaptive TB-LMI adaptive time-based least memory intensive scheduling application interfere memory access scheduling techniques memory requests memory system performance multicore system overall multicore system fairness overall multicore system performance system throughput Benchmark testing Hardware Instruction sets Memory management Registers Scheduling Scheduling algorithms Memory Controller Memory Interference Multi-core Shared Resources instruction sets Memory Controller Benchmark testing DRAM chips Multiprocessing systems scheduling of multiprocessor Store management Scheduling algorithms system performance Registers Memory Memory Computer hardware time bases Self tuning

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XGRID: A Scalable many-core embedded Processor 17

XGRID: A Scalable Many-Core Embedded Processor

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2015 ieee 17th international Conference on High Performance Computing and Communications (HPCC)

作者： Gunes, Volkan Givargis, Tony Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)9781479989379

The demand for compute cycles needed by embedded systems is rapidly increasing. In this paper, we introduce the XGRID embedded many-core system-on-chip architecture. XGRID makes use of a novel, FPGA-like, programmable interconnect infrastructure, offering scalability and deterministic communication using hardware supported message passing among cores. Our experiments with XGRID are very encouraging. A number of parallel benchmarks are evaluated on the XGRID processor using the application mapping technique described in this work. We have validated our scalability claim by running our benchmarks on XGRID varying in core count. We have also validated our assertions on XGRID architecture by comparing XGRID against the Graphite many-core architecture and have shown that XGRID outperforms Graphite in performance.

关键词： Multi-core many-core embedded Processors system-on-chip Architectures

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FPU Speedup Estimation for Task Placement Optimization on Asymmetric multicore Designs 9

FPU Speedup Estimation for Task Placement Optimization on As...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Aminot, Alexandre Lhuillier, Yves Castagnetti, Andrea Charles, Henri-Pierre CEA LIST Minatec Campus F-91191 Gif Sur Yvette France Univ Grenoble Alpes F-38000 Grenoble France

ISBN: (纸本)9781479986705

The number of cores is increasing in processor designs. By having the same duplicated core increases dark silicon and reduces the scalability of multicore/many-core designs. Asymmetric distribution of ISA specialized units (i.e. FPU and SIMD units) in multicore designs can bring new opportunities for performance gain, area and energy savings. Basically, the task placement is driven by the requirement of the specialized resources. To improve task-mapping flexibility, solutions such as code-versioning or binary translation allow the OS to place any task on any type of core. However, a specialized execution unit such as FPU is able to speedup some part up to 1000x compared to the same function emulated with Integer execution units. On one hand, mapping all tasks on the core with the FPU creates a bottleneck, and on the other hand, mapping a high FPU-usage application on a core without FPU drastically degrades the performance. To allow a smarter placement, the OS needs to know the potential advantage of using the FPU for each thread. In this paper, we demonstrate that only using the trivial percentage utilization is not enough to have an accurate estimation. We propose a finer grain solution to estimate the speedup of the FPU at runtime. The average of the absolute error is 14 %, which is 4.8 times better than the trivial coarse estimation. Then we characterize the different types of FPU-usage through a set of common benchmarks and show the variability of the utilization during the execution.

关键词： coprocessors multiprocessing systems resource allocation FPU speedup estimation asymmetric multicore designs task placement optimization Acceleration Benchmark testing Degradation Emulation Estimation multicore processing Registers Coprocessors Benchmark testing Multiprocessing systems simulating Registers Resource utilization Speeding core acceleration Multi-core processors Legal Executions asymmetric distribution

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MLDPBS: A Machine Learning based Dynamic Partitioning Buddy system for Efficient Memory Allocation in embedded systems 17

MLDPBS: A Machine Learning based Dynamic Partitioning Buddy ...

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17th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2024

作者： Kumari, Sweta Mishra, Dhruv Sharma, Aaradhy Somani, Archit Shiv Nadar Institution of Eminence Department of Computer Science and Engineering Greater Noida India

ISBN: (纸本)9798331530471

The Buddy system is a memory management technique used in operating systems to allocate memory blocks. Traditional Buddy system partitions the memory block in the power of 2 until the system finds the smallest available block to accommodate the memory allocation request. These systems suffer from efficient memory allocation and *** propose a novel approach called Machine Learning based Dynamic Partitioning Buddy system (MLDPBS) for the efficient memory allocation and fragmentation. Our propose MLDPBS enhances traditional Buddy systems by leveraging Machine Learning (ML) for efficient memory allocation. Instead of relying on fixed partition sizes, we dynamically adjust memory partitions based on predicted memory usage through ML model, significantly reducing fragmentation and improving overall efficiency compared to conventional memory allocation techniques like First Fit and Best Fit. To improve the performance of MLDPBS, we propose a multi-threaded lock-free model that minimizes the overhead caused by partitioning and merging memory blocks, a common issue in traditional Buddy *** experiments demonstrate that the proposed MLDPBS achieves 1.5x and 1.76x average speedup over the traditional memory allocation techniques and state-of-the-art Buddy systems, respectively, for embedded systems red on various benchmarks. © 2024 ieee.

关键词： Locks (fasteners)

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A multicore Architecture for High-Performance Scientific Computing using FPGAs 8

A Multicore Architecture for High-Performance Scientific Com...

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8th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Cobos Carrascosa, J. P. Aparicio del Moral, B. Ramos, J. L. Lopez Jimenez, A. C. del Toro Iniesta, J. C. CSIC Inst Astrofis Andalucia Granada Spain

ISBN: (纸本)9781479943050

A multicomputer architecture is proposed in order to achieve high performance in floating point using FPGA devices. This architecture is used in the system prototype of an instrument that carries out a real-time scientific data analysis aboard the ESA's Solar Orbiter space mission. A novel method for parallelizing the scientific algorithm in multicore systems is developed. A software tool that automatizes the architecture design process and configuration is presented.

关键词： MIMD multi-core FPGA high-performance software pipelining

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MRAPI implementation for Heterogeneous Reconfigurable systems-on-chip 22

MRAPI implementation for Heterogeneous Reconfigurable System...

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22nd ieee Annual international symposium on Field-Programmable Custom Computing Machines ((FCCM)

作者： Gantel, L. Benkhelifa, M. E. A. Verdier, F. Lemonnier, F. Thales Res & Technol Embedded Syst Lab 1 Ave Augustin Fresnel F-91767 Palaiseau France Univ Cergy Pontoise ENSEA ETIS Lab CNRS F-95014 Cergy Pontoise France Univ Nice Sophia Antipolis CNRS LEAT Lab F-06903 Sophia Antipolis France

ISBN: (纸本)9781479951116

In a Reconfigurable system-on-chip (SoC) platform, the application is divided into threads managed by an operating system, and whereas some threads are implemented as hardware threads and allocated into a partition of the chip, others run as software threads on embedded processing elements. Relying on the multicore Resource management API (MRAPI) specification and client-server mechanisms, we propose solutions to provide a flexible access to the operating system services for every threads whatever is the core they are running on. In order to improve the application deployment process when targeting HRSoC, we realized both a hardware and a software implementation of this API. Depending on affinities of the operating system services with each core, such a solution allows a fine-grain implementation of these services over the platform.

关键词： Hardware Instruction sets multicore processing Operating systems Servers system-on-chip FPGA MRAPI multiprocessor architectures real-time operating systems reconfigurable computing Operating systems system-on-chip real time operating system MULTIPROCESSOR ARCHITECTURE instruction sets Computer hardware THREADS Servers Field programmable gate arrays software implementation

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Task Scheduling Strategies for Batched Basic Linear Algebra Subprograms on many-core CPUs 14

Task Scheduling Strategies for Batched Basic Linear Algebra ...

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14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Mukunoki, Daichi Hirota, Yusuke Imamura, Toshiyuki RIKEN Ctr Computat Sci Kobe Hyogo 6500047 Japan Univ Fukui Fukui Fukui 9108507 Japan

ISBN: (纸本)9781665438605

Batched Basic Linear Algebra Subprograms (BLAS) provides an interface that allows multiple problems for a given BLAS routine (operation) - with different parameters and sizes independent of each other - to be computed in a single routine. The efficient use of cores on many-core processors has been introduced for computing multiple minor problems for which sufficient parallelism cannot be extracted from a single problem. The major goal of this study is to automatically generate high-performance batched routines for all BLAS routines using nonbatched BLAS implementation and OpenMP on CPUs. Furthermore, the primary challenge is the task scheduling method for allocating batches to cores. In this study, we propose a scheduling method based on a greedy algorithm, which allocates batches based on their costs in advance to eliminate load imbalance when the costs of batches vary. Then, we investigate the performance of five scheduling methods, including ones implemented in OpenMP and our proposed method, on matrix multiplication (GEMM) and matrix-vector multiplication (GEMV) under several conditions and environments. As a result, we found that the optimal scheduling strategy differs depending on the problem setting and environment. Based on this result, we propose an automatic generation scheme of batched BLAS from nonbatched BLAS that can introduce arbitrary task scheduling. This scheme facilitates the development of batched routines for a full set of BLAS routines and special BLAS implementations such as high-precision versions.

关键词： batched BLAS task scheduling OpenMP many-core

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