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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Improving long text classification based on Selective State Space model (Mamba)

Improving long text classification based on Selective State ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Mudar Sarem Tarek Jurdi Laya Albshlawy Ebrahim Massrie Faculty of Engineering Manara University Latakia Syria Computer Engineering Dept. Tishreen University Latakia Syria Costal Branch Gen. Org of Remote Sensing Latakia Syria Faculty of Information Tech. Damascus Univarsity Damascus Syria

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Recently, with the use of transformer-based models, a big progress has been achieved across many areas of Natural Language Processing (NLP) including text classification. However, such progress is often limited to the short sequences as the standard approach with self-attention becomes slow and inefficient for long sequences due to its quadratic complexity. As a new architecture, Mamba addresses this challenge using Selective State Space Models (SSMs). Unlike previous SSMs, Mamba empowers its parameters to be input-dependent, enabling content-aware information propagation along the sequence. Also, Mamba integrates these selective SSMs into a streamlined architecture, achieving significant speedup and linear scaling with sequence length. In this paper, by taking the advantage of the smallest pre-trained Mamba model, Mamba-130, our Mamba 130m classifier has achieved a balance between the efficiency and the performance making it ideal for initial investigation. Although Mamba's efficiency and effectiveness empower it to handle sequences up to 1 million elements long, eliminating the need for truncation or chunking within documents, but we are limited to only use 15 GB of VRAM on Google Colab Pro and employ a constrained sequence length to address memory limitations. However, the experimental results presented in this paper show that our Mamba 130m classifier still outperforms the state-of-the-art approaches on long text classification tasks across multiple benchmark datasets.

关键词： multicore processing Text categorization Memory management Benchmark testing Transformers Natural language processing Internet Complexity theory Standards

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Cognitive Bus Coding Scheme for Inter-chip Communications of Deep Learning Accelerator chiplet on Low-cost Si and Glass Interposer

Cognitive Bus Coding Scheme for Inter-Chip Communications of...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yu-Hong Chang Tourangbam Harishore Singh Po-Tsang Huang International College of Semiconductor Technology National Yang Ming Chiao Tung University Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781665465007

In the present Artificial Intelligence (AI) hardware research, interposer based multi-chip Deep Learning Accelerator (DLA) system is one of the main technology. Silicon (Si) interposer is the main key in the emerging 2.5D integration process. However, signal integrity is limited by the capacitive crosstalk and signal reflection can lead to notch attack in some frequency bands. In this paper, two new bus coding schemes are proposed to improve signal integrity, reducing the crosstalk to increase bandwidth for on-silicon-interposer and on-glass-interposer inter-chip data communications. For silicon interposer, a joint code division multiple access and crosstalk avoidance coding (Joint CDMA/CAC) scheme is proposed to reduce the capacitive crosstalk effect for fine-pitch interconnects. The eye diagram and bit error rate are both improved, and the average crosstalk effect is reduced by half. Also, a cognitive bus coding scheme is proposed by spread spectrum and channel learning for glass interposer. The proposed cognitive bus coding increases the total data bandwidth under frequency notches based on the channel condition for modulation.

关键词： Frequency modulation Codes Crosstalk Glass Bandwidth Resists Encoding

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Distance Aware Compression for Low Latency High Bandwidth Interconnection Network

Distance Aware Compression for Low Latency High Bandwidth In...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Zhou Yuqing Naoya Niwa Hideharu Amano Dept. of Information and Computer Science Keio University Yokohama Japan

ISBN: (纸本)9781665465007

NoC(Network-on-chip)s is an essential component of recent multi-core systems. When the number of wires available on a chip is limited, it is sometimes congested and increased la-tency can degrade the parallel application performance. The selective data compression has been proposed to mitigate such network congestion by compressing and decompressing packets based on the packet length and traffic situation. However, since the algorithm does not care the location of nodes, the compression and decompression are performed even when the packet is transferred between neighboring nodes. This paper proposes a distance aware (DA) compression mechanism to select whether the packet should be compressed by the distance to the destination. The packets to the nodes whose distance is larger than threshold level are compressed with a run-length loss-less compression at the sender's network interface and de-compressed at the receiver's network interface. Cycle level network simulation results show that the selective compression method achieves up to 45% bandwidth improve-ment with 1.26 times increase of the latency.

关键词： Multiprocessor interconnection multicore processing Simulation Wires Data compression Bandwidth Fats

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Clustering-Based Image Registration of Tubule Candidates in Breast Histopathology Images

Clustering-Based Image Registration of Tubule Candidates in ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Joseph Jiun Wen Siet Xiao Jian Tan Wai Loon Cheor Khairul Shakir Ab Rahman Yee Von Thien Department of Electrical and Electronics Engineering Faculty of Engineering and Technology (FOET) Tunku Abdul Rahman University of Management and Technology (TAR UMT) Kuala Lumpur Malaysia Biomedical and Bioinformatics Engineering (BBE) Research Group Centre for Multimodal Signal Processing (CMSP) Tunku Abdul Rahman University of Management and Technology (TAR UMT) Kuala Lumpur Malaysia Department of Pathology Hospital Tuanku Fauziah Perlis Malaysia

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Tubule formation is a rudimental and vital parameter to be considered for cancer aggressiveness detections based on histopathology image data, in accordance with the Nottingham Histopathology Grading (NHG) system. In order to identify and measure tubule formation, here, the present study investigates the potential of clustering-based image registrations for tubule candidates’ identification. The elementary structures that constituted the signatures of the tubules: nuclei and central lumens are identified using K-means clustering. The breast histopathology image patches are harvested from the hematoxylin and eosin (H&E) stained breast Whole-Slide Images (WSIs). The stain unmixing method is utilized to normalize the image colors, and to compute the hematoxylin-stained channel (H-channel) and eosin-stained channel (E-channel). K-means clustering is applied on the H-channel to segregate the nuclei regions from the stain artifact regions or background. The same method is applied on the E-channel to identify the hemorrhage regions for segregation from the initial image. Also, the same algorithm is applied to the stainnormalized histopathology patch for the identification of lumen candidates’ regions. A simple heuristic axiom is designed and mechanized, prior to the pronouncement of precise lumen candidates’ cluster affirmations apart from the rest of the clusters. Through overlaying (summing) the nuclei and lumen candidates’ clusters on the same image frame, the candidates of tubules are registered from the reference input histopathology image patch.

关键词： Image registration Image segmentation Histopathology multicore processing Image color analysis Clustering algorithms Lumen Breast Hemorrhaging Cancer

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Evaluation of Different Microarchitectures for Energy-Efficient RISC-V cores

Evaluation of Different Microarchitectures for Energy-Effici...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Junichiro Kadomoto Hidetsugu Irie Shuichi Sakai Department of Information and Communication Engineering The University of Tokyo Tokyo Japan

ISBN: (纸本)9781665465007

The increase in Internet of Things $(\text{IoT})$ applications has triggered the development of energy-efficient embedded SoCs that can utilize limited energy sources. Relatively simple general-purpose processor cores are a vital component of SoCs, and op-timizing the power consumption, performance, and area is a key issue in the design of $\text{SoCs}$ . Therefore, this study quantitatively compared the power, performance, and area of several 32-bit RISC-V cores with different microarchitectures. The simulation evaluations were performed for each processor with different pipeline configurations, with and without a multiplier and divider. The benchmark execution performance of the processors in a register transfer level (RTL) design, as well as the estimated power consumption and area based on logic synthesis and place-and-route using various CMOS process technologies are presented. Based on the results, we provided a brief guideline for the selection of microarchitectures for energy-efficient embedded SoCs.

关键词： Semiconductor device modeling Microarchitecture Power demand multicore processing Pipelines Organizations Energy efficiency

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Design and FPGA Implementation of Lite Convolutional Neural Network Based Hardware Accelerator for Ocular Biometrics Recognition Technology

Design and FPGA Implementation of Lite Convolutional Neural ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Wei-Che Sun Chih-Peng Fan Chung-Bin Wu Department of Electrical Engineering National Chung Hsing University Taichung city Taiwan (R.O.C.)

ISBN: (纸本)9781665465007

In this study, the effective low-complexity Convolutional Neural Network (CNN) inference network is implemented by the FPGA-based hardware accelerator for the biometric authentications. After the labeling processes, the eye images with partial iris and sclera zones are used to train and test the LeNet-based Lite-CNN model. Then the lightweight CNN classifier is rapidly prototyped via FPGA for hardware acceleration. Through testing, the proposed Lite-CNN model achieves up to 98% recognition accuracy with the eye images. Compared with the software-based implementation, the proposed Lite-CNN hardware accelerator provides similar detection accuracy, and the inference time of 0.0246 seconds is accelerated about 377 times on the Xilinx ZCU102 FPGA platform. Besides, compared with the previous FPGA implementation by the high level synthesis design, the proposed hardware acceleration design performs the computing speed more than about 92 times.

关键词： Image recognition multicore processing Biological system modeling Authentication High level synthesis Convolutional neural networks Labeling

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Distributed Decision Fusion for Large Scale IoT- Ecosystem

Distributed Decision Fusion for Large Scale IoT- Ecosystem

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Ashwin Raut Divesh Kumar Vijay Kumar Chaurasiya Manish Kumar Department of IT IIIT-Allahabad Allahabad India

ISBN: (纸本)9781665465007

IoT data analytics have numerous applications that generate huge data to gain new insights and information. How-ever, this work remains challenging due to the heterogeneity of IoT data sources, unnecessary data processing, uncertainty in decision-making, data biasness, and ever-increasing data size. To overcome these challenges, we propose distributed decision fusion framework for the large-scale IoT ecosystem. The proposed framework has divided into three-level. The first and second level provides the local decision of the small individual ecosystem using the filter method-based feature selection and dynamic classifier selection criteria for decision making; whereas the third level fuses the collected decision from the small ecosystems using Majority voting, Weighted majority voting and distributed Naive Bayes classifier. Lastly, we illustrate performance of the proposed solution on the US-Accidents dataset.

关键词： Uncertainty Data analysis multicore processing Fuses Soft sensors Ecosystems Decision making

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Reinforcement Learning for Testtime Optimization in the Network-on-chip based systems

Reinforcement Learning for Testtime Optimization in the Netw...

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ieee international symposium on Quality Electronic Design

作者： Anantha Kamath Aditya Handur-Kulkarni Himanshu Singh Kanchan Manna Department of Computer Science and Information Systems BITS Pilani K. K. Birla Goa Campus India

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Network on chip (NoC) serves as a scalable and cost-effective choice for communication between the cores in multicore or manycore systems. As the number of cores on an Integrated Circuit (IC) increases, so does the risk of defects during manufacturing of these multicore systems. This makes the manufacturing test procedures increasingly important. Finding an optimal test schedule from the large-scale system is extremely time-consuming and a complex optimization task. In this paper, we propose a Machine Learning (ML) framework (MAPIC) to enhance the mapping of cores to the Input-Output (IO) pairs in the network, aiming to generate an optimal test schedule for the NoC-based system. Pointer network architecture has been used for generating the mapping solution and ChatGPT 4o has been used to generate $NoC$ benchmarks from an IP core repository. The repository contains the cores and their test information from ITC'02 benchmarks. The experimental results indicate the effectiveness of the proposed framework as it outperforms a metaheuristic-based optimization technique.

关键词： Integrated circuits Schedules multicore processing Reinforcement learning Network-on-chip Benchmark testing Network architecture Manufacturing Large-scale systems Optimization

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Turn-aware Application Mapping using Reinforcement Learning in Power Gating-enabled Network on chip

Turn-aware Application Mapping using Reinforcement Learning ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Mohammadmehdi Shammasi Mohammad Baharloo Meisam Abdollahi Amirali Baniasadi Department of Electrical and Computer Engineering University of Victoria Victoria Canada

ISBN: (纸本)9781665465007

As the backbone for many-core chips, Network-on-chips (NoCs) consume a significant share of total chip power. As a result, decreasing the power consumption in these components can reduce the total chip's power significantly. NoC's routers can be powered down using power-gating, a promising technique for reducing static power consumption. In some advanced methods, routers are put in sleep mode and only wake up when they are needed to turn/inject packets. Since waking up the router takes several cycles to complete, packets will experience high latency. In this regard, application mapping significantly impacts the number of turns. This article proposes a reinforcement learning (RL) framework based on Actor-Critic architecture to optimize the application mapping problem to minimize the number of turn packets as well as communication cost. Our RL framework learns the heuristic of the mapping problem and outputs a near-optimal mapping. A 2-opt local search algorithm fine-tunes this strategy and provides an improved mapping. Our simulations show that the proposed RL framework can achieve better cost and algorithm run-time performance compared to other heuristic algorithms such as Simulated Annealing (SA) and Genetic Algorithm (GA).

关键词： Costs Power demand multicore processing Heuristic algorithms Reinforcement learning Simulated annealing Logic gates

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Theoretical Analysis of the Memory-Efficient Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs

Theoretical Analysis of the Memory-Efficient Matrix Storage ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Le Tran Xuan Hieu Pham Hoai Luan Vu Tuan Hai Le Vu Trung Duong Yasuhiko Nakashima University of Information Technology Ho Chi Minh City Vietnam Vietnam National University Ho Chi Minh City Vietnam Nara Institute of Science and Technology Ikoma Nara Japan

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the MEMS (Memory-Efficient Matrix Storage) method for storing quantum operators and states, along with a MEMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the MEMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from 2 2 to 2 5 on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it substantially faster than previous works.

关键词： Performance evaluation Quantum system Tensors Quantum algorithm Qubit Emulation Logic gates Quantum circuit Field programmable gate arrays Testing

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