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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Accurate and Efficient Identification of Worst-Case Execution Time for multicore Processors: A Survey

Accurate and Efficient Identification of Worst-Case Executio...

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8th ieee international Design and Test symposium (IDT)

作者： Mushtaq, Hamid Al-Ars, Zaid Bertels, Koen Delft Univ Technol Comp Engn Lab Delft Netherlands

ISBN: (纸本)9781479935253

Parallel systems were for a long time confined to high-performance computing. However, with the increasing popularity of multicore processors, parallelization has also become important for other computing domains, such as desktops and embedded systems. Mission-critical embedded software, like that used in avionics and automotive industry, also needs to guarantee real time behavior. For that purpose, tools are needed to calculate the worst-case execution time (WCET) of tasks running on a processor, so that the real time system can make sure that real time guarantees are met. However, due to the shared resources present in a multicore system, this task is made much more difficult as compared to finding WCET for a single core processor. In this paper, we will discuss how recent research has tried to solve this problem and what the open research problems are.

关键词： Multi-core processors execution time PROCESSOR Research Problems real-time systems parallel system avionics time characteristic automobile industry parallelization

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Automatic Runtime Customization for Variability Awareness on multicore Platforms 9

Automatic Runtime Customization for Variability Awareness on...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Ayad, Gasser Nittala, Ramakrishna Lemaire, Romain Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy Univ Grenoble Alpes F-38000 Grenoble France CEA LETI F-38054 Grenoble France

ISBN: (纸本)9781479986705

Driven by increasingly aggressive CMOS technology scaling, sub-wavelength lithography is incurring more evident variability in the technology parameters of the semiconductors fabrication process. That variability results in otherwise identical designs displaying very different performances, power consumption levels and lifespans once fabricated. Hence, process variability may lead to execution uncertainties, impacting the expected quality of service and energy efficiency of the running software. As such uncertainties are intolerable in certain application domains such as automotive and avionic infotainment systems, it has become a persistent necessity to customize runtime engines to introduce measures for variability awareness in task allocation decisions. The purpose of compensating process variability is to avoid performance degradation and energy inefficiency. And customization is meant to take place automatically through exporting the variability-impacted platform characteristics - such as per-core manufactured clock frequency - for the runtime library to perform variability-aware workload sharing on the target cores of the hardware platform. Hence, we can eventually achieve noticeable optimization results, not only on the system performance and energy consumption levels, but also in increasing productivity in systems development, testing, integration, and marketing. This paper presents a holistic approach starting from a system model of the target multicore platform, to building and integrating the runtime library, and finally highlighting the optimization results achieved through the proposed runtime customization paradigm.

关键词： CMOS integrated circuits energy consumption lithography microprocessor chips multiprocessing systems power aware computing software libraries aggressive CMOS technology scaling automatic runtime customization automotive systems avionic infotainment systems energy consumption levels energy efficiency energy inefficiency multicore platform multicore platforms per-core manufactured clock frequency performance degradation power consumption levels runtime customization paradigm runtime engines runtime library semiconductors fabrication process subwavelength lithography task allocation decisions variability awareness variability-aware workload sharing Hardware multicore processing Resource management Runtime Runtime library Software Unified modeling language Runtime library Runtime power aware computing energy consumption Software libraries Multiprocessing systems UML degradation of performance Microprocessor chips CMOS integrated circuits Lithography Energy efficiency management of resources Computer hardware computer software

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Shared memory protection for spatial separation in multicore architectures

Shared memory protection for spatial separation in multicore...

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7th ieee international symposium on Industrial embedded systems, SIES 2012

作者： Hattendorf, Anton Raabe, Andreas Knoll, Alois Fortiss GmbH München Germany Institut für Informatik VI Technische Universität München Germany

ISBN: (纸本)9781467326841

The introduction of multicore architectures in embedded systems allows system integrators to locate multiple applications on the same chip. In the context of certification separation of these applications is mandatory. Most current multicore systems have a low core count and programmers have a need for easily utilizable platforms. Therefore, most of the current multicore systems use shared memory architectures based on bus communication. In this paper we discuss several possible architectures for shared memory protection using local and shared MPUs and MMUs for architectures of this type. This analysis includes typical use cases for multicore systems and their compatibility to these architectures. It has a strong focus on the platform's suitability for mixed-critical workloads with some cores executing safety-critical, hard-real-time applications. This paper proposes a novel shared memory protection unit to efficiently enforce spatial separation of the shared memory among the cores. Preliminary synthesis results are provided along with latency considerations relevant for hard-real-time application. © 2012 ieee.

关键词： embedded systems

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BRU: Bandwidth Regulation Unit for Real-Time multicore Processors 26

BRU: Bandwidth Regulation Unit for Real-Time Multicore Proce...

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26th ieee Real-Time and embedded Technology and Applications symposium (RTAS)

作者： Farshchi, Farzad Huang, Qijing Yun, Heechul Univ Kansas Lawrence KS 66045 USA Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781728154992

Poor time-predictability of the multicore processors is a well-known issue that hinders their adoption in the real-time systems due to contention in the shared memory resources. In this paper, we present the Bandwidth Regulation Unit (BRU), a drop-in hardware module that enables per-core memory bandwidth regulation at fine-grained time intervals. Additionally, BRU has the ability to regulate the memory access bandwidth of multiple cores collectively to improve bandwidth utilization. Besides eliminating the overhead of software regulation methods, our evaluation results using SD-VBS and synthetic benchmarks show that BRU improves time-predictability of real-time tasks, while it lets the best-effort tasks to better utilize the memory system bandwidth. In addition, we have synthesized our design for a 7nm technology node and show that the chip area overhead of BRU is negligible.

关键词： Bandwidth Regulation Real-time multicore Processor RISC-V TileLink

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2017 ieee 23rd international symposium on On-Line Testing and Robust system Design, IOLTS 2017

2017 IEEE 23rd International Symposium on On-Line Testing an...

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23rd ieee international symposium on On-Line Testing and Robust system Design, IOLTS 2017

ISBN: (纸本)9781538603512

The proceedings contain 60 papers. The topics discussed include: a new 3-bit burst-error correcting code;automating wafer-level test of uncooled infrared detectors using wafer-prober;deterministic network on chip for deploying real time applications on many-core processors;diagnosis with transition faults on embedded segments;design-time reliability evaluation for digital circuits;voltage margins identification on commercial x86-64 multicore microprocessors;a generic embedded sequence generator for constrained-random validation with weighted distributions;an effective functional safety infrastructure for system-on-chips;and in-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.

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Managing the Latency of Data-Dependent Tasks in embedded Streaming Applications 9

Managing the Latency of Data-Dependent Tasks in Embedded Str...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Do, Xuan Khanh Louise, Stephane Cohen, Albert CEA LIST F-91191 Gif Sur Yvette France INRIA F-75005 Paris France ENS F-75005 Paris France

ISBN: (纸本)9781479986705

Streaming languages are well suited to the development of embedded many-core applications that process large volumes of data with high throughput. Because they enable periodic scheduling, cyclo-static models of computation and their variants are well fitted to modern real-time applications. Nevertheless, while schedules may be functionally correct-by-construction, they can still violate timing constraints and safety requirements of critical real-time embedded systems (e.g. avionics). Such violations are usually caused by delays that are not accounted for, due to resource sharing (e.g. the communication medium). In this paper, we investigate the applicability of the theory of hard-real-time scheduling for periodic tasks in the context of streaming applications. More specifically, we consider Cyclo-Static Dataflow (CSDF) graphs with variable interprocessor communication (IPC) times, and real-time constraints imposed by hardware devices or control engineers. As a result, we establish a latency constraint on the initiation times of predecessor actors on which a given actor is dependent. Based on this constraint, we show how to guarantee real-time services and reduce inconsistencies in a CSDF application by introducing a fault-tolerant procedure. We evaluate the performance of our scheduling policy for a set of 12 real-life streaming applications. We find that in most of the cases, our approach yields the maximum achievable throughput as obtained under Self-Timed scheduling (STS).

关键词： cyclo-static dataflow real-time scheduling latency fault-tolerant

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Autotuning Power Consumption and Computation Accuracy using ppOpen-AT 15

Autotuning Power Consumption and Computation Accuracy using ...

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15th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2022

作者： Yamanashi, Shouhei Yashiro, Hisashi Katagiri, Takahiro Nagai, Toru Ohshima, Satoshi Graduate School of Informatics Nagoya University Aichi Japan National Institute for Enviromental Studies Earth System Division Ibaraki Japan Information Technology Center Nagoya University Aichi Japan

ISBN: (纸本)9781665464994

Mixed-precision computation mainly focuses on shortening the execution time, at the expense of accuracy. To achieve speedups for numerical calculation using mixed-precision computation, it is necessary to tune software performance with respect to not only execution speed but also computation accuracy and power consumption. This increases the overall cost of tuning. Autotuning (AT) is one of the candidates among several technologies available for reducing the cost associated with tuning the software performance. In this study, we propose a method for AT to obtain speedups with respect to computation accuracy and power consumption. The proposed AT method uses an AT language that changes computation accuracy of the original code to mixed-precision by combining double and single precisions. Performance evaluation was carried out by using the Fujitsu PRIMEHPC FX1000, which is a 'Fugaku' type supercomputer installed at the Information Technology Center, Nagoya University. The proposed method achieved a 1.5x reduction in execution time and energy consumption while retaining reasonable accuracy degradation from the original code of a global cloud resolving model. © 2022 ieee.

关键词： Electric power utilization

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A Novel Approach to Precision Diagnosis of Multiple Sclerosis Brain Lesions Utilizing a Convolutional-based Ensemble Classification Approach for embedded systems 17

A Novel Approach to Precision Diagnosis of Multiple Sclerosi...

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17th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2024

作者： Chilaka, Saiakhil Kapavarapu, Raghavendra Satwik Rong, Zhikang Enloe High School RaleighNC United States Simon G. Atkins High School Winston-SalemNC United States

ISBN: (纸本)9798331530471

Multiple Sclerosis Is a chronic autoimmune condition characterized by an attack elicited through an immune response in the central nervous system. Affecting over 1.8 million people worldwide. The condition leads to a range of neurological symptoms, including limited mobility, impaired vision, and cognitive deficits. Although the exact causes of multiple sclerosis remain unclear, a combination of genetic, environmental, and immunological factors is believed to play an important role over multiple years. In such cases, an early and accurate diagnosis through MRI scans remains crucial for timely intervention and proper treatment. Leveraging a meticulously curated ensemble model, this approach integrates optimized convolutional layers with customized transfer-learning models, combining the strengths of both frameworks for enhanced performance. The obtained dataset contains sagittal and axial magnetic resonance scans (n=3427) in greyscale, obtained through a prior study that studied 131 subjects in 2021. In the pre-processing stage, all images were resized to 128 by 128 pixels for computational efficiency and converted to RGB, followed by two 80-20 splits, resulting in training, validation, and final testing sets. A final ensemble model consisting of an optimized VGG19 achieved an average 97.5% accuracy, and a receiving operating characteristic (ROC) of 97.8%. Subsequent analyses were directed towards intricate multiclass stratifications, elucidating avenues for nuanced diagnostics and treatment planning for multiple sclerosis. © 2024 ieee.

关键词： Neurodegenerative diseases

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In-Network Memory Access Ordering for Heterogeneous multicore systems 14

In-Network Memory Access Ordering for Heterogeneous Multicor...

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14th ieee/ACM international symposium on Networks-on-chip (NOCS)

作者： Yin, Jieming Zhai, Antonia Lehigh Univ Bethlehem PA 18015 USA Univ Minnesota Twin Cities Minneapolis MN USA

ISBN: (纸本)9781728188478

In heterogeneous multicore systems, implementing a programmer-friendly memory consistency model while maximizing memory-level parallelism is challenging. Ideally, memory accesses can be performed out of order as long as program order is not violated. But enforcing memory access order at the end-point (e.g., a core) prohibits a number of architecture optimizations and limits memory-level parallelism. In this work, we explore the opportunity of preserving memory access order inside the on-chip interconnection network. We propose a hybrid switching networks-on-chip (NoC) attached with a light-weight token ring network to guarantee global memory access order. The hybrid switching NoC that supports both packet and circuit switching serves as the underlying communication infrastructure, while the token ring network is used to preserve memory order among multiple ordering points. Our proposed design enables strong memory consistency models and deterministic program execution, with negligible performance overhead compared to an un-ordered packet switching network.

关键词： Packet switching

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Saving Energy by Means of Dynamic Load Management in embedded multicore systems

Saving Energy by Means of Dynamic Load Management in Embedde...

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9th ieee international symposium on Industrial embedded systems (SIES)

作者： Becker, Matthias Schmidt, Adriaan Orehek, Martin Nolte, Thomas Malardalen Univ MRTC Vasteras Sweden Fraunhofer Inst Embedded Syst & Commun Technol E Munich Germany Univ Appl Sci Munich Munich Germany

ISBN: (纸本)9781479940226

Load balancing is widely used to optimize response times and throughput of software systems. When considering embedded systems, however, additional optimization goals like energy consumption become relevant. In this paper, we explore the use of load balancing in embedded multicore applications. We present extensions to three prominent load balancing schemes, enabling them to dynamically scale the number of active cores. We integrated the algorithms in a proprietary operating system targeting multicore embedded systems. Our evaluation, which is based on a telecommunication (VoIP) scenario, shows that a significant reduction in energy consumption is possible.

关键词： Switches Time factors Load balancing Time Factors Switches energy consumption Multi-core processors energy saving dynamic loading load management Software systems embedded systems Reaction Time embedding

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