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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是11-20 订阅

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Message from the Chairs: Welcome to the 2022 ieee 15th international symposium on embedded multicore/many-core systems-on-chip (ieee MCSoC-2022)

Message from the Chairs: Welcome to the 2022 IEEE 15th Inter...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

The 2022 ieee 15 th international symposium on embedded multicore/many-core systemson-chip (MCSoC-2022) is an annual international symposium favored by the Universiti Sains Malaysia (USM) and the Technical Committee on Microprocessors and Micro-computers of the ieee Computer Society in cooperation with the ieee Singapore Section. MCSoC 2022 is hosted in Penang - a charming island in Malaysia - at Universiti Sains Malaysia (USM). There is growing confidence that future massively-parallel computer systems will be based on connectionist models and the innovative design of interconnection networks, processor architecture, applications, and software tools for embedded multi-core systems-on-chip will play a crucial role in our understanding the future systems. Along with Industry 4.0, the Internet of Things, cloud computing, data-centric computing through the Internet along with artificial intelligence become more and more popular. Therefore, the required computing power is incredibly increasing every moment. The rise of artificial intelligence innovation in recent years is encountering efficiency of power, online adaptation, and architectural and design issues. This edition of MCSoC offers new tracks on artificial intelligence on-chip learning and neuromorphic computing together with nine tracks on SoC design and application to bring new and potent methods for design from devices to applications.

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A real-time fault-tolerant and power-efficient multicore system on chip 13

A real-time fault-tolerant and power-efficient multicore sys...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Gruzlikov, A. M. Kolesov, N. V. Kostygov, D. V. Tolmacheva, M. V. Concern CSRI Elektropribor JSC St Petersburg 197101 Russia

ISBN: (纸本)9781728148823

An approach to designing fault-tolerant and power-efficient multicore systems on chip for real-time information processing and control is proposed. It is assumed that a multicore system has a reserve on the chip, allowing for additional information processing. The approach is based on the rules of introducing redundancy aimed at reducing power consumption and the principles of system-level fault diagnosis, making it possible to decentralize the system recovery in case of failure.

关键词： PMC-model decentralized fault-tolerant system energy-efficient system

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PortBlocker: Detection and Mitigation of Hardware Trojan through Re-routing and Bypassing 16

PortBlocker: Detection and Mitigation of Hardware Trojan thr...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Bagga, Sachin Gupta, Ruchika Jose, John Chandigarh Univ Ajitgarh Punjab India Indian Inst Technol Guwahati Gauhati Assam India

ISBN: (纸本)9798350393613

The ever-evolving semiconductor industry demands swift adaptation to meet dynamic market requirements. Companies that do not have expertise in the entire supply chain process of realizing semiconductor integrated circuits often rely on third-party intellectual property (IP) to cater to the market demands. The dependence on external vendors exposes chips to vulnerabilities like Hardware Trojans (HT) that compromise the system's performance. Network On chip (NoC), the backbone of modern multicore processors is prone to such HT attacks due to the extensive use of third-party IPs. In this paper, we model a packet misrouting HT for a NoC framework and study its impact at the core, cache, and interconnect levels. We also detect the presence of such HTs using traffic profiling. Our mitigation technique called PortBlocker ensures packets reach their destination through an alternate path bypassing the HT router. Experimental analysis using SPEC CPU 2006 benchmark workloads shows the effectiveness of our approach for various packet categories.

关键词： Network on chip Security Hardware Trojan Tile chip multicore Processor Flits

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Design-Time Memory Subsystem Optimization for Low-Power Multi-core embedded systems 13

Design-Time Memory Subsystem Optimization for Low-Power Mult...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Strobel, Manuel Radetzki, Martin Univ Stuttgart Chair Embedded Syst Stuttgart Germany

ISBN: (纸本)9781728148823

embedded multi-core systems are increasingly in use. As established single-core design methodologies are often not applicable out of the box, novel design-time optimization methods are required in order to manage real-time characteristics, predictability, or tight constraints with respect to energy consumption or system performance. With focus on the memory subsystem in a multi-core embedded system, this paper proposes an optimization workflow for the application-specific optimal binding of code and data to memory instances, efficient handling and scheduling of available memory low-power modes, and the automated and transparent integration of these optimization results on the software level. Presented optimization algorithms are realized as integer linear programs;code modification and generation are implemented on the basis of LLVM. Experimental results for an ARM-based quad-core platform with SRAM memory subsystem, consisting of core-local scratchpad memories and global shared memory, prove the efficiency of our method in terms of energy consumption when compared to a system using direct-mapped caches, but also in comparison with a state-of-the-art scratchpad mapping heuristic.

关键词： Design-Time Memory Optimization Low-Power embedded system Design Multi-core Integer-Linear Programming system Design Automation

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Real-Time Audio Processing on the T-CREST multicore Platform 11

Real-Time Audio Processing on the T-CREST Multicore Platform

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ausin, Daniel Sanz Pezzarossa, Luca Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9781538634417

multicore platforms are nowadays widely used for audio processing applications, due to the improvement of computational power that they provide. However, some of these systems are not optimized for temporally constrained environments, which often leads to an undesired increase in the latency of the audio signal. This paper presents a real-time multicore audio processing system based on the T-CREST platform. T-CREST is a time-predictable multicore processor for real-time embedded systems. Multiple audio effect tasks have been implemented, which can be connected together in different configurations forming sequential and parallel effect chains, and using a network-onchip for intercommunication between processors. The evaluation of the system shows that real-time processing of multiple effect configurations is possible, and that the estimation and control of latency ensures real-time behavior.

关键词： Real-time systems multicore processing Signal processing algorithms Signal processing Task analysis Software Mathematical model Signal processing algorithms task analysis Multi-core processors real-time systems signal processing Mathematical Model computer software Audio audio signals real-time process Platform Latency

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A Scalable JPEG Encoder on a many-core Array 16

A Scalable JPEG Encoder on a Many-Core Array

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Abbott, Thomas Baas, Bevan Univ Calif Davis ECE Dept Davis CA 95616 USA

ISBN: (纸本)9798350393613

JPEG is a widely-used image compression algorithm. A 31-core JPEG encoder and a scalable family of JPEG encoders were developed for a fine-grain many-core processor array and are measured on the 32 nm Kilocore chip. These implementations are compared against JPEG implementations on three high-level-language-programmable chip platforms: an Nvidia A100 GPU with an Intel Platinum 8168 (nvJPEG), a TI C66x embedded processor, and an Intel i9-9900 processor (libjpeg-turbo). In addition, an HDL-configurable Xilinx Zynq-7000 FPGA (VISENGI) was compared. All results are scaled to 32nm CMOS, and throughput per area, energy per megapixel encoded, and the comprehensive energy x delay metrics are compared. The Kilocore designs achieve the lowest chip area and the highest normalized throughput per chip area. Among the chips that are programmable by a high-level programming language, the Kilocore achieves up to 4.33x, 31.4x, and 46.4x lower energy dissipation and up to 4.81x, 7,845x, and 14,510x lower energy x delay than the TI, Intel, and Nvidia respectively.

关键词： many-core JPEG encoder processor array

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Distributed Neural Networks using TensorFlow over multicore and many-core systems 13

Distributed Neural Networks using TensorFlow over Multicore ...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ranbirsingh, Jagadish Kumar Kimm, Hanke Kimm, Haklin East Stroudsburg Univ Dept Comp Sci East Stroudsburg PA 18301 USA

ISBN: (纸本)9781728148823

This paper focuses on distributed deep learning models that simulate the HAR (Human Activity Recognition) data set from the UCI machine learning Repository. The proposed deep learning LSTM (Long Short-Term Memory) model works with the TensorFlow framework using the Python 3 programming language which supports the distributed architecture. In order to simulate the distributed deep learning models over different multicore and many-core systems, two hardware platforms are built;the first one is equipped with a Raspberry Pi cluster with 16 Pi 3 model B+ boards which each having 1 GB of RAM and 32 GB flash storage. The second platform is houses an Octa-core Intel Xeon CPU system with a 16MB Cache, 32 GB RAM and 2 TB SSD primary storage with 10 TB HDD secondary storage. In this paper, the performance of the distributed LSTM model over multicore and many-core systems is presented in terms of execution speed and efficiency of prediction accuracy upon varying number of deep layers with corresponding hidden nodes. In this experiment, a 3 x 3 distributed LSTM model has been used, which furnishes higher prediction accuracy with faster computation time than the models that different number of layers provide.

关键词： Distributed LSTM Model TensorFlow multicore systems Human Activity Recognition

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Real-Time Attitude Estimation of Sigma-Point Kalman Filter via Matrix Operation Accelerator 13

Real-Time Attitude Estimation of Sigma-Point Kalman Filter v...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Dai, Zeyang Jing, Lei Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9781728148823

Attitude estimation is an important part for navigation of mobile robotics and unmanned aerial vehicle (UAV) control. Although the Extended Kalman Filter (EKF) can be done typically, the trend is to use Sigma-Point Kalman Filter (SPKF) instead due to its higher accuracy and robustness in harsh environment. The only drawback of such system is the higher computation cost. In order to accelerate the system, most approaches based on Field Programmable Gate Arrays (FPGA) are proposed in the past but too specific, which is not reusable and the high price for design complexity. With looking for re-usability, we present an IP core called matrix operation accelerator in this paper. Moreover, we do the verification on Zynq-7020, the experimental result shows that the proposed scheme can reduce about 50% computing time and save silicon as well.

关键词： real-time orientation estimation sigma-point kalman filter matrix operation accelerator system-on-chip

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Communication-Avoiding Tile QR Decomposition on CPU/GPU Heterogeneous Cluster system 12

Communication-Avoiding Tile QR Decomposition on CPU/GPU Hete...

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Takayanagi, Masatoshi Suzuki, Tomohiro Univ Yamanashi 4-3-11 Takeda Kofu Yamanashi 4008511 Japan

ISBN: (纸本)9781538666890

The tile algorithm for matrix decompositions is attracting attention as a method for the latest multicore/many-core architecture because it can generate many fine-grained tasks which can be executed in parallel. Exploiting many parallel computing resources effectively with a fork-join paradigm is difficult. CPU/GPU heterogeneous cluster system is mainstream for a supercomputer system in recent years. Using the CPU/GPU cluster system efficiently is more difficult than efficiently utilizing the multicore cluster system. We implemented the tile CAQR decomposition algorithm on the CPU/GPU cluster system with OpenMP 4.0, MPI and cuBLAS, and proposed new approaches to utilize GPUs efficiently. In this paper, we show the performance result of our implementation on the Reedbush-H heterogeneous supercomputer.

关键词： Matrix decomposition Task analysis Kernel multicore processing Dynamic scheduling Heuristic algorithms Clustering algorithms

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Statistical analysis for shared resources effects with multi-core real-time systems 13

Statistical analysis for shared resources effects with multi...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Durand, Julien Bouchebaba, Youcef Santinelli, Luca CPT P E&DS SE FR AET Toulouse France Off Natl Etud & Rech Aerosp DTIS Toulouse France

ISBN: (纸本)9781728148823

Today's multi-core and many-core COTS platforms make available a large amount of computational resource for real-time applications. As they aim at increasing performance for real-time, their challenges are the guarantees for timing constraints. Real-time modeling and analysis are thus facing shared resources, optimization mechanisms, and sophisticated functionalities which all combine into complex system dynamics that are extremely costly to characterize. This paper proposes a measurement-based approach and a statistical analysis applied to define average and worst-case models to task executions under different possible execution conditions. The framework is formalized and then used to investigate different families of shared resources interference effects occurring on multi-core platforms;such effects are quantified with statistical metrics applied to measurements of tasks execution times. The focus of the work is on effects due to shared memories within the NXP T4240 multi-core platform and the PikeOS hypervisor. A set of experiments is conducted to validate the framework proposed.

关键词： Task analysis Real-time systems Interference Timing Analytical models

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