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Neuronal population biomarkers of temporal difference learning in human impulsive choices

Neuronal population biomarkers of temporal difference learni...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Rhiannon L. Cowan Tyler S. Davis Bornali Kundu John D. Rolston Elliot H Smith Neurosurgery Department University of Utah Salt Lake City UT USA Department of Neurological Surgery University of California San Francisco CA USA Neurosurgery Department Harvard Medical School Boston MA USA

ISBN: (纸本)9781665465007

Impulsive choice is a facet of impulsivity that may lead to one to choose smaller, more immediate rewards over larger, delayed rewards. Impulsive choice is a kind of maladaptive decision making that is a fundamental element of relapse in substance use disorder. Despite its essential role in relapse, there is currently little understanding of the neural basis of impulsive choices. Better understanding of the neural correlates of impulsivity could lead to improved diagnosis and treatment of psychiatric disorders in which impulsive choice plays a role. In this work, we examined impulsive choice behavior in humans undergoing intracranial seizure monitoring by fitting temporal difference learning models to behavior and broadband high frequency (70–150 Hz) local field potentials. We found neural and behavioral differences between more and less impulsive choosers, informing the neural underpinnings of impulsive choices and describing a biomarker for reward expectation and surprise in the human brain.

关键词： multicore processing Sociology Fitting Decision making Brain modeling Behavioral sciences Broadband communication

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Exploring the Potential of Error-permissive Communication in Multi-FPGA-based Edge Computing

Exploring the Potential of Error-permissive Communication in...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Akram Ben Ahmed Ryousei Takano Takahiro Hirofuchi Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology Koto-ku Tokyo JAPAN

ISBN: (纸本)9781665465007

In recent years, Edge Computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud Computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on Multi-FPGA systems which have gained significant attention in Edge Computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%.

关键词： Performance evaluation Electric potential Cloud computing Power demand multicore processing Voltage Transceivers

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A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA systems

A Message Passing Interface Library for High-Level Synthesis...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Kazuei Hironaka Kensuke Iizuka Hideharu Amano Dept. of Information and Computer Science Keio University Yokohama Japan

ISBN: (纸本)9781665465007

One obstacle to application development on multi-FPGA systems with high-level synthesis (HLS) is a lack of support for a programming interface. Implementing and debugging an application on multiple FPGA boards is difficult without a standard interface. Message Passing Interface (MPI) is a standard parallel programming interface commonly used in distributed memory systems. This paper presents a tool-independent MPI library called FiC-MPI that can be used in HLS for multi-FPGA systems in which each FPGA node is connected directly. By using FiC-MPI, various parallel software, including a general-purpose benchmark, can be easily implemented. FiC-MPI was implemented and evaluated on the M-KUBOS cluster consisting of Zynq MPSoC boards connected with a static time-division multiplexing network. By using the FiC-MPI simulator, parallel programs can be debugged before implementing on real machines. As a case study, the Himeno-BMT benchmark was implemented with FiC-MPI. It achieved 178.7 MFLOPS with a single node and scaled to 643.7 MFLOPS with four nodes, and 896.9 MFLOPS with six nodes of the M-KUBOS cluster. Through the implementation, the easiness of developing parallel programs with FiC-MPI on multi-FPGA systems was demonstrated.

关键词： Multiplexing Parallel programming multicore processing Message passing Benchmark testing Libraries Software

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A systematic review of machine learning techniques in online learning platforms

A systematic review of machine learning techniques in online...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Cyril Elorm Kodjo Agbewali-Koku Md. Atiqur Rahman Mohamed Hamada Mohammad Ameer Ali Lutfun Nahar Oysharja Md Tazmim Hossain Department of Computer Science and Engineering Daffodil International University Bangladesh School of Computer Science and Engineering The University of Aizu Fukushima Japan Monash University Australia Department of English Daffodil International University Bangladesh

ISBN: (纸本)9781665465007

The mode of education has changed over the past few years from the conventional method of in-person classes to the usage of online platforms to facilitate teaching and learning. These platforms popularly, known as online learning systems, have gradually become an integral part of education. These online platforms have been designed using various Artificial intelligence frameworks and techniques to enhance their functionality and personalize them for their users. Machine learning is one of the major fields of AI that has been used in most of these online platforms. Popular machine learning techniques such as deep learning, natural language processing, reinforcement learning, and others are being actively used and studied to further improve them for use. In this study, the focus will be on content analysis of different studies aimed at disclosing machine learning techniques that have been applied in the online learning sector and exploring the potential research trends and challenges of integrating machine learning techniques in online learning. The study will focus on published papers from the year 2015 to 2021, classifying them based on the research question.

关键词： Learning systems Deep learning systematics multicore processing Education Machine learning Reinforcement learning

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Cluster Based Smart Random Walk for Data Aggregation in Wireless Sensor Network

Cluster Based Smart Random Walk for Data Aggregation in Wire...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Manish Kumar Maurya Anubhav Shivhare Aadil Ali Satakshi Ashutosh Mishra Manish Kumar Dept. of Information Technology Indian Institute of Information Technology Allahabad Prayagraj India Department of Maths Sam Higginbottom University of Agriculture Technology and Sciences Prayagraj India Department of Applied Sciences Indian Institute of Information Technology Allahabad Prayagraj India

ISBN: (纸本)9781665465007

Wireless Sensor Network (WSN) is a collection of sensor devices having limited communication range and battery power. It has unreliable wireless medium for data transmission hence reliable message delivery is a challenging task for routing protocols designed for WSN. In multiple scenarios a Random Walk (RW) in WSNs is proved to be energy efficient for routing and load balancing. Further clustering methodologies provide a novel idea of multi-hop data gathering and aggregation which significantly reduces redundant data transmission. The present work explores the integration of RW and clustering schemes with an objective to improve upon existing routing protocols in terms reliable data transmission and network lifetime. Hence, a hybrid Cluster-Based Smart Random Walk (CBSRW) routing technique for data collection and aggregation is proposed in this paper. It has two phases: Clustering & data aggregation and CBSRW. Experimental results and comparative analysis show that the proposed work achieves an enhanced lifetime and efficient packet delivery ratio compared to the conventional state of the art schemes designed for the domain.

关键词： Wireless communication Wireless sensor networks multicore processing Data aggregation Routing Reliability engineering Load management

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Intelligent congestion control for NoC architecture in Gem5 simulator

Intelligent congestion control for NoC architecture in Gem5 ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Smriti Srivastava Mushtaq Ahmed Shaikh Shivaneetha G Minal Moharir Department of CSE R V College of Engineering Bangalore India Department of ECE R V College of Engineering Bangalore India

ISBN: (纸本)9781665465007

Congestion in a network significantly impacts the performance of an NoC as there is a substantial increase in latency and power consumption. Machine Learning techniques aid in designing routing methods to keep the network cognizant of the traffic status. This paper presents a congestion-aware Q-routing algorithm based on the Q-learning model of reinforcement learning. The proposed algorithm enhances the network's performance in an NoC under heavy traffic conditions by routing the packets along a less congested path. Thus, it reduces the congestion in the network. This is possible as Q-learning allows the network to keep track of the local and non-local congestion by estimating Q-values. The Q-values guide a node in sending a data packet along an optimal path, thereby evading busy routes. The simulation done on the gem5 simulator with uniform link latency in the network exhibits that Q-routing performs better in a high-load environment than traditional XY and Odd-Even Routing methods, with a performance gain of 5.73% and 12.73%, respectively. The results for varied link latencies that were randomly assigned to create a practical congestion-probable scenario showed that the proposed method outperformed both the XY and Odd-Even routing algorithm with a respective performance gain of 7.38% and 15.19%.

关键词： Q-learning Machine learning algorithms Power demand multicore processing Performance gain Routing

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Allocating Auto Offset system in Periodic Task for Load Balancing in Multi-core ECU

Allocating Auto Offset System in Periodic Task for Load Bala...

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ieee international symposium on Industrial Electronics (ISIE)

作者： Sung Keun Cha Se Jeong Lim Young Soo Do Jae Wook Jeon Department of Electrical and Computer Engineering Sungkyunkwan University Suwon Korea

ISBN: (数字)9798350394085

ISBN: (纸本)9798350394092

In the automotive industry, there is a lot of research on how to handle tasks by considering the load on the core. As automotive features are widely added, electronic control units are moving from using single-core to multi-core electronic control units. many methods have been developed for handling tasks in multi-core electronic control units, and we have been able to reduce the load on the cores. We want to reduce the peak core load and wait time, which are key core performance metrics in the automotive sector. In this paper, we propose a system that automatically assigns a suitable offset to each periodic task. By giving offset to periodic tasks with our auto-calculation system, we reduce the peak core load and reduce unnecessary wait time.

关键词： Measurement Industries Industrial electronics Job shop scheduling multicore processing Load management Resource management

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A Genetic Algorithm for Scheduling in Heterogeneous multicore system Integrated with FPGA 19

A Genetic Algorithm for Scheduling in Heterogeneous Multicor...

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19th ieee international symposium on Parallel and Distributed Processing with Applications (ieee ISPA)

作者： Jiang, Qingyuan Xu, Jinyi Chen, Yixiang East China Normal Univ Software Engn Inst Dept Embedded Software & Syst Shanghai Peoples R China MOE Engn Res Ctr Software Hardware Codesign Techn Shanghai Peoples R China

ISBN: (纸本)9781665435741

The heterogeneous multicore system integrated with FPGA is a kind of Multi-Processor systems-on-chip(MPSoC) that can achieve both efficiency and flexibility. FPGA uses hardware resource instead of instruction sets to process tasks. The resource on FPGA is limited which should be considered when scheduling tasks. We propose a static task scheduling algorithm targeting this kind of system. The aim is to minimize the executing time of an application as well as considering FPGA resource limit. In our genetic algorithmbased method, a chromosome consists of computing units where tasks are assigned. When generating the initial population, some tasks are assigned to FPGA, considering FPGA resource limit. We have modified the crossover operator and mutation operator to ensure that the FPGA resource used implied in chromosomes will not exceed the FPGA resource limit. Task scheduling is completed in the chromosome evaluation stage. Through the genetic algorithm, the improved task assignment and schedule sequence are obtained. The experiments on random graph applications and two real-world applications show that our method has achieved better performance than existing works.

关键词： task scheduling heterogeneous multicore system FPGA genetic algorithm

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DNA: Dynamic Resource Allocation for Soft Real-Time multicore systems 27

DNA: Dynamic Resource Allocation for Soft Real-Time Multicor...

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30th ieee international symposium on Software Reliability Engineering (ISSRE)

作者： Gifford, Robert Gandhi, Neeraj Phan, Linh Thi Xuan Haeberlen, Andreas Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781665403863

Modern latency-sensitive and real-time systems often use multi-core platforms;thus, tasks on different cores share certain hardware resources, such as the memory bus and certain cache levels. This has two undesirable consequences: (1) tasks can interfere with each other, causing high latency for the system as a whole, and (2) it becomes difficult to meet deadlines, since the worst-case timing of a given task depends on all the tasks it might have to compete with. Static partitioning isolates tasks from each other by allocating a certain fraction of the resources to each;however, many tasks execute in different phases (e.g., memory-intensive and CPU-intensive) that have different requirements. Thus, system designers are left with a choice between overprovisioning, based on the most demanding phase, or suboptimal performance. In this paper, we propose a pair of techniques, called DNA and DADNA, to address the above challenge. DNA increases throughput and decreases latency, by building an execution profile of each task to identify the phases, and then dynamically allocating resources based on which task can benefit the most;DADNA further adds support for soft real-time workloads by taking deadlines into account We have built a prototype of both techniques in the Xen hypervisor;our experimental results show that, compared to a state-of-the-art solution, DNA and DADNA can substantially improve schedulability, reduce job deadline miss ratios, and cut latencies by more than a factor of two even in extremely overloaded situations.

关键词： Virtual machine monitors multicore processing DNA Prototypes Static analysis Throughput Real-time systems

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Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices

Composite Lightweight Authenticated Encryption Based on LED ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Mohammed Al-Shatari Fawnizu Azmadi Hussin Azrina Abd Aziz Mohd Saufy Rohmad Xuan-Tu Tran Department of Electrical and Electronic Engineering Universiti Teknologi Petronas Seri Iskandar Perak Malaysia Faculty of Electrical Engineering Universiti Teknologi MARA Shah Alam Selangor Malaysia VNU Information Technology Institute Vietnam National University Hanoi Vietnam

ISBN: (纸本)9781665465007

IoT devices are being used in different environments recently. They are mostly resource-constrained, and therefore, their data security is crucial. Several lightweight cryptographic primitives were proposed to overcome the limitations of the devices while maintaining moderate security levels. Such primitives provide either encryption or authentication. The encryption must be authenticated by a Message Authentication Code (MA C) or hash function for better overall security. Therefore, an architecture of integrated lightweight authenticated encryption (AE) based on LED block cipher and PHOTON hash function is presented. LED and PHOTON architectures were combined while exploiting area-performance trade-offs and utilizing the shared internal functions. The architecture is designed in Verilog HDL, synthesized in Altera Quartus II and simulated on Field Programmable Gate Array (FPGA) devices. The individual design of LED utilizes 357 logic elements (LE) and PHOTON utilizes 852 LE resulting in a total of 1209 LE. The logic utilization of the proposed shared architecture is 1046 LE. The results reveal that 13.5 % reduction in logic area is achieved compared to the independent implementations of LED and PHOTON.

关键词： Hash functions Ciphers multicore processing Programmable logic arrays Light emitting diodes Encryption Internet of Things

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