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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Modelling Bus Contention during system Early Design Stages 12

Modelling Bus Contention during System Early Design Stages

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12th ieee international symposium on Industrial embedded systems (SIES)

作者： Trilla, David Hernandez, Carles Abella, Jaume Cazorla, Francisco J. BSC Barcelona Spain UPC Barcelona Spain Spanish Natl Res Council IIIA CSIC Barcelona Spain

ISBN: (纸本)9781538631669

Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early stages applications are not yet consolidated and IP constraints may prevent sharing them across providers, challenging the estimation of contention bounds. In this paper, we propose a model to estimate the increase in applications' execution time due to on-chip bus sharing when they simultaneously execute in a multicore. The model works with information derived from the execution of each application in isolation, hence, without the need to actually run applications simultaneously. The model improves inaccuracy with respect to the existing model, and tends to over-estimate. The latter, is very important to prevent that, during late design stages, applications miss their deadline when consolidated into the same multicore, causing costly system redesign.

关键词： multicore processing Timing Program processors Load modeling Mathematical model Schedules Analytical models

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Investigating core-level N-modular redundancy in multiprocessors 8

Investigating core-level N-modular redundancy in multiproces...

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8th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Simevski, Aleksandar Kraemer, Rolf Krstic, Milos Brandenburg Tech Univ Cottbus D-03046 Cottbus Germany IHP D-15236 Frankfurt Oder Germany

ISBN: (纸本)9781479943050

When the limits of exploiting parallelism are reached, multiprocessors are not efficient since many of the processing elements (cores) are idle. Several proposed solutions use this idleness in order to improve the fault tolerance of the multiprocessor, with relatively small performance and/or cost overheads. In this paper, we propose a dynamical fault tolerant scheme in which one or more groups of multiprocessor cores are arranged to form tightly-synchronized N-Modular Redundant (NMR) sub-systems. These NMR groups could be formed dynamically, with an arbitrary number of cores, according to the application requirements of fault tolerance and performance. Moreover, the cores which are not engaged in an NMR group could continue to work independently. Tight synchronization and voting in each clock cycle is provided by special, programmable NMR voters. We make a vast number of experiments in order to investigate the reliability of the proposed scheme. The results led to closed-form expressions which show whether a given NMR group of N cores will be able to withstand the assumed fault rate during the projected mission time.

关键词： Arrays Fault tolerance Nuclear magnetic resonance Reliability theory Synchronization Tunneling magnetoresistance N-modular redundant (NMR) systems dynamic NMR formation multiprocessor reliability programmable NMR voters Fault tolerance Multiprocessor reliability theory Nuclear Magnetic Resonance tunneling magnetoresistance core clock cycle core samples modular redundancy mission time failure rates arrays

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A High-Throughput Network Intrusion Detection system Using On-Device Learning on FPGA 17

A High-Throughput Network Intrusion Detection System Using O...

引用

17th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2024

作者： Wu, Man Kondo, Masaaki Keio University Department of Information and Computer Science Yokohama Japan

ISBN: (纸本)9798331530471

Deploying machine learning (ML)/deep learning (DL)-based network intrusion detection system (NIDS) enables intelligent traffic analysis against the increasing sophistication of modern network traffic. However, most existing DL/ML-based NIDSs rely heavily on large-scale models and statistical-based features, which lead to the development of such NIDS for IoT devices being computationally expensive and low throughput, thereby falling against the ever-growing network bandwidth. In this work, we propose a new intrusion detection system on FPGA by using on-device learning to classify network traffic online at high throughput. In particular, the proposed NIDS first introduces the two-level hierarchical raw transmitted bytes for input features. Further, our NIDS employs a lightweight classifier by incorporating a genetic algorithm-based feature selector and on-device sequential learning semi-supervised anomaly detector (ONLAD). These three engines are implemented on the Xilinx ZCU104 FPGA platform for high throughput while supporting model updates online by the on-device learning mechanism. For proof of concept, our results on the CIC-IDS2018 dataset show that the proposed method reaches a maximum throughput of 3,302,010 pps and a supported bandwidth of 39.62 Gbps while maintaining 0.986 AUC score. Moreover, our NIDS allows model updates on-device with a power consumption of 0.703 W and latency of 4.17 us. © 2024 ieee.

关键词： Genetic algorithms

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Experiences with the Sparse Matrix-Vector Multiplication on a many-core Processor

Experiences with the Sparse Matrix-Vector Multiplication on ...

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26th ieee international Parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Pichel, Juan C. Rivera, Francisco F. Univ Santiago de Compostela Ctr Invest Tecnol Informac CITIUS Santiago De Compostela Spain

ISBN: (纸本)9780769546766

Industry is moving towards many-core processors, which are expected to consist of tens or even hundreds of cores. One of these future processors is the 48-core experimental processor Single-chip Cloud Computer (SCC). The SCC was created by Intel Labs as a platform for many-core research. The characteristics of this system turns it into a big challenge for researchers in order to extract performance from such complex architecture. In this work we study and explore the behavior of an irregular application such as the Sparse Matrix-Vector multiplication (SpMV) on the SCC processor. An evaluation in terms of performance and power efficiency is provided. Our experiments give some key insights that can serve as guidelines for the understanding and optimization of the SpMV kernel on this architecture. Furthermore, a comparison of the SCC processor with several leading multicore processors and GPUs is performed.

关键词： many-core sparse matrix performance power efficiency

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Design and implementation of vehicle oil online information monitoring system 15

Design and implementation of vehicle oil online information ...

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15th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2022

作者： Lv, Zhenbin Wang, Xin Zhi, Haifeng Lin, Bo Shen, Yitao Wang, Yanyan Wang, Chenxu Harbin Institute of Technology Weihai Weihai China National Ocean Technology Center Tianjin China

ISBN: (纸本)9781665464994

With the popularization and application of vehicles, the safety of automobiles has gradually attracted widespread attention, among which the quality of oil is an important factor affecting vehicle safety. Nowadays, the monitoring and evaluation of oil is divided into offline and online ways. This paper is aimed at the application of obtaining and analyzing oil quality in real time for vehicles. And based on the online monitoring method, this paper designed and implemented a vehicle oil information monitoring system. In the system, hardware acquisition part consists of oil sensors and self-made STM32 board, and host computer monitoring software as an analysis display part. After experimental testing, the system can conduct online monitoring, early warning and evaluation of the dielectric constant, viscosity, water content, water activity, density and temperature indicators of oil, and can predict the soot content and diesel content with the given model, and can calculate the 100°C kinematic viscosity using the least squares fitting algorithm. The accuracy and measurement range of the system depend on the indicators of the oil sensors. This vehicle oil information monitoring system is conducive to collecting the actual parameters of vehicle oil operation and providing a reliable basis for vehicle safety maintenance. © 2022 ieee.

关键词： Vehicle safety

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Scalable and Memory-efficient Spin Locks for embedded Tile-based many-core Architectures 21

Scalable and Memory-efficient Spin Locks for Embedded Tile-b...

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21st ieee international symposium on Real-Time Computing (ISORC)

作者： Awamoto, Shinichi Chishiro, Hiroyuki Kato, Shinpei Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan

ISBN: (纸本)9781538658475

embedded many-core system-on-chip (SoC) architectures require scalability and memory constraints. However, communication between many cores, especially locking mechanisms of operating systems, is often the main obstacle to scalable and memory-efficient processing. Existing scalable spin locks consume non-negligible amounts of memory in many-core architectures, thus they are not suitable for memory constrained systems. This paper focuses on a combination of a global Mellor-Crummey and Scott (MCS) queue lock, and local ticket (TKT) locks. We refer to this lock as the C-MCS-TKT lock, which has much better memory efficiency than other scalable spin locks without degrading scalability. In addition, this paper also presents a memory-optimized version of the C-MCS-TKT lock, which slightly degrades scalability but reduces memory fragmentation, compared to the original C-MCS-TKT lock. Experimental results show that these locks have comparable performance to those of other highly scalable spin locks.

关键词： Spin Locks Synchronization many-core Architectures embedded systems Scalability Memory Efficiency

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Towards Automatic Code Generation of Run-Time Power Management for embedded systems using Formal Methods 9

Towards Automatic Code Generation of Run-Time Power Manageme...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Fathabadi, Asieh Salehi Maeda-Nunez, Luis Alfonso Butler, Michael J. Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Elect & Comp Sci Southampton SO9 5NH Hants England

ISBN: (纸本)9781479986705

Run-Time Management (RTM) systems are used to control energy hooks at run-time to minimise the energy consumption of embedded systems with single and many-core processors. Typically, such RTM systems are aware of application requirements and utilise workload prediction and machine learning algorithms to estimate the optimal configuration. An RTM mechanism should not compromise the reliability or performance of the platform it is managing. Because of the potential complexity and interaction with the platform and its applications, we are using rigorous design methods that allow us to master the complexity and verify the correctness of our designs in a formal way. The formal RTM design can be verified earlier in the development process before implementation, which early verification can reduce the cost of fixing potential failures which can be very demanding in testing the system after implementation. In addition, the formal model of a RTM system can be automatically translated into executable code to be executed on the hardware. Automatic code generation reduces the efforts of hand-coded implementation and is portable across different architectures and Operating systems (OSs). In this paper we propose a formal approach toward automatic generation of RTM system code, for a video decoder application, from a verified formal model of a RTM. The formal model of the RTM system is developed using the Event-B formal modelling language and is verified using theorem proving and model checking. The automatically generated RTM system has been integrated in an embedded platform as a Linux governor, and provides up to 4% improvement over Linux's default Ondemand governor.

关键词： Linux embedded systems formal verification power aware computing program compilers theorem proving Event-B formal modelling language Linux governor RTM system code automatic code generation formal methods model checking run-time power management video decoder Algorithm design and analysis Decoding Hardware Learning (artificial intelligence) Mathematical model Monitoring Prediction algorithms embedded systems theorem proving power aware computing Transfer molding Video Decoder Algorithm design and analysis compilers Prediction algorithms Linux Model checking Formal verification Computer hardware DECODING Code generation Runtime

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Comparative Analysis of Middleware for Multi-Processor system-on-chip (MPSoC)

Comparative Analysis of Middleware for Multi-Processor Syste...

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9th Annual international Conference on Innovations in Information Technology (IIT)

作者： Jallad, Abdul-Halim Mufid Mohammad, Lubna Badri Al Zaytoonah Univ Jordan Dept Comp & Commun Engn Amman Jordan

ISBN: (纸本)9781467362030

Efficient software is required in order to make optimum utilization of the full-scale features of the rapidly developing MPSoC hardware. embedded MPSoCs are characterized by their heterogeneity and resource limitation. In addition, embedded MPSoCs systems would be required to deal with a complex set of tasks whose resource requirements cannot be easily determined statically at design time. Middleware is a particularly important software component of embedded MPSoC that enables the system to overcome heterogeneity and manage resources dynamically at run-time. An important part of the middleware is the run-time system manager responsible for the distributed resource manager of the MPSoC-based system. system management at run-time is important for many modern embedded systems because the tasks performed by the system vary over time. In this paper we explore design trade-offs for middleware systems targeting multi-core embedded systems. The experimental platform implemented for the project is presented and future work is highlighted.

关键词： multicore Multi-Processor-system-on-chip middleware embedded systems run-time management

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On-chip Cache Hierarchy-Aware Tile Scheduling for multicore Machines

On-Chip Cache Hierarchy-Aware Tile Scheduling for Multicore ...

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9th Annual ieee/ACM international symposium on Code Generation and Optimization (CGO)

作者： Liu, Jun Zhang, Yuanrui Ding, Wei Kandemir, Mahmut Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)9781612843551

Iteration space tiling and scheduling is an important technique for optimizing loops that constitute a large fraction of execution times in computation kernels of both scientific codes and embedded applications. While tiling has been studied extensively in the context of both uniprocessor and multiprocessor platforms, prior research has paid less attention to tile scheduling, especially when targeting multicore machines with deep on-chip cache hierarchies. In this paper, we propose a cache hierarchy-aware tile scheduling algorithm for multicore machines, with the purpose of maximizing both horizontal and vertical data reuses in on-chip caches, and balancing the workloads across different cores. This scheduling algorithm is one of the key components in a source-to-source translation tool that we developed for automatic loop parallelization and multithreaded code generation from sequential codes. To the best of our knowledge, this is the first effort that develops a fully-automated tile scheduling strategy customized for on-chip cache topologies of multicore machines. The experimental results collected by executing twelve application programs on three commercial Intel machines (Nehalem, Dunnington, and Harpertown) reveal that our cache-aware tile scheduling brings about 27.9% reduction in cache misses, and on average, 13.5% improvement in execution times over an alternate method tested.

关键词： on-chip cache Tile Multi-core processors machinery machine sequential codes execution time Uniprocessor embedded application Code generation

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Classifying Performance Bottlenecks in Multi-Threaded Applications 8

Classifying Performance Bottlenecks in Multi-Threaded Applic...

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8th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Dutta, Sourav Manakkadu, Sheheeda Kagaris, Dimitri So Illinois Univ ECE Dept Carbondale IL 62901 USA

ISBN: (纸本)9781479943050

The performance of multi-threaded applications on modern multi-core processors does not necessarily depend on the number of cores. Instead it depends on multiple factors such as thread synchronization, which leads to thread spinning, and limited memory bandwidth for memory bound applications, which causes cores to wait for requested data and negative references in a shared cache or last-level cache. From a designer's perspective it is important to understand performance bottlenecks of a given application in order to design efficient hardware to achieve optimal performance. In this paper, we propose a model to identify scaling bottlenecks of multi-threaded applications which is based on linear regression. We demonstrate the practical usefulness of the model by applying it to benchmark multi-threaded applications.

关键词： Connectors Copper Damping Iron Reactive power Springs Switches Connector Device Component springs Device Spring Reactive power Switches absorption of shock Traffic Bottlenecks multi-threaded application memory bandwidth Copper Iron core

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