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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Accelerating Non-Negative Matrix Factorization on embedded FPGA with Hybrid Logarithmic Dot-Product Approximation

Accelerating Non-Negative Matrix Factorization on Embedded F...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yizhi Chen Yarib Nevarez Zhonghai Lu Alberto Garcia-Ortiz School of Electrical Engineering and Computer Science KTH Royal Institute of Technology Stockholm Sweden Institute of Electrodynamics and Microelectronics (ITEM.ids) University of Bremen Bremen Germany

ISBN: (纸本)9781665465007

Non-negative matrix factorization (NMF) is an ef-fective method for dimensionality reduction and sparse decom-position. This method has been of great interest to the scien-tific community in applications including signal processing, data mining, compression, and pattern recognition. However, NMF implies elevated computational costs in terms of performance and energy consumption, which is inadequate for embedded applications. To overcome this limitation, we implement the vector dot-product with hybrid logarithmic approximation as a hardware optimization approach. This technique accelerates floating-point computation, reduces energy consumption, and preserves accuracy. To demonstrate our approach, we employ a design exploration flow using high-level synthesis on an embedded FPGA. Compared with software solutions on ARM CPU, this hardware implementation accelerates the overall computation to decompose matrix by $5.597\times$ and reduces energy consumption by $69.323\times$ . Log approximation NMF combined with KNN(k-nearest neighbors) has only 2.38% decreasing accuracy compared with the result of KNN processing the matrix after floating-point NMF on MNIST. Further on, compared with a dedicated floating-point accelerator, the logarithmic approximation approach achieves $3.718\times$ acceleration and $8.345\times$ energy reduction. Compared with the fixed-point approach, our approach has an accuracy degradation of 1.93% on MNIST and an accuracy amelioration of 28.2% on the FASHION MNIST data set without pre-knowledge of the data range. Thus, our approach has better compatibility with the input data range.

关键词： Degradation Energy consumption Visualization Program processors Memory management Hardware Matrix decomposition

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Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks

Digital Computation-in-Memory Design with Adaptive Floating ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yun-Ru Yang Wei Lu Po-Tsang Huang Hung-Ming Chen International College of Semiconductor Technology National Yang Ming Chiao Tung University Hsinchu Taiwan Institute of Electronics National Yang Ming Chiao Tung University Hsinchu Taiwan Institute of Electronics National Yang Ming Chiao Tung University Taiwan

ISBN: (纸本)9781665465007

All-digital deep neural network (DNN) accelerators or processors suffer from the Von-Neumann bottleneck, because of the massive data movement required in DNNs. Computation-in-memory (CIM) can reduce the data movement by performing the computations in the memory to save the above problem. However, the analog CIM is susceptible to PVT variations and limited by the analog-digital/digital-analog conversions (ADC/DAC). Most of the current digital CIM techniques adopt integer operation and the bit-serial method, which limits the throughput to the total number of bits. Moreover, they use the adder tree for accumulation, which causes severe area overhead. In this paper, a folded architecture based on time-division multiplexing is proposed to reduce the area and improve the energy efficiency without reducing the throughput. We quantize and ternarize the adaptive floating point (ADP) format with low bits, which can achieve the same or better accuracy than integer quantization, to improve the energy cost of calculation and data movement. This proposed technique can improve the overall throughput and energy efficiency up to 3.83x and 2.19x, respectively, compared to other state-of-the-art digital CIMs with integer.

关键词： Deep learning Quantization (signal) Program processors Neural networks Computer architecture Throughput Time division multiplexing

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High-Performance Asynchronous CNN Accelerator with Early Termination

High-Performance Asynchronous CNN Accelerator with Early Ter...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Tan Rong Loo T. Hui Teo Mulat Ayinet Tiruye I-Chyn Wey Engineering Product Development Singapore University of Technology and Design Singapore Engineering Product Development Science Mathematics and Technology Singapore University of Technology and Design Singapore Artificial Intelligence Research Center School of Electrical and Computer Engineering College of Engineering Graduate Institute of Electrical Engineering Chang Gung University Chang Gung University Taiwan

ISBN: (纸本)9781665465007

Convolutional Neural Network (CNN), especially very deep networks, are highly computation intensive, resulting in long delays and high-power consumption. The dynamically varying environmental conditions in real world inference can result in highly complex problems, and hence the need for these inefficient deep networks to guarantee satisfactory accuracy all the time. Several studies employ approximation techniques to execute partial computation of the network, in attempt to reduce the amount of computation were unnecessary. However, such approaches are still highly sequential in nature, since they still need to run the whole network. This paper proposes an early termination architecture on an already-trained CNN to allow for testing the partial results midway through the network, reducing computations by terminating the main network when it is sufficient as the inference results. The first proposal is implemented in synchronous circuit, however, due to its nature all memory elements are required to capture even when no new data is generated. The second proposal employs the use of asynchronous circuit to significantly reducing power consumption and further sped up the architecture since an operation need not wait the slowest critical path in the circuit. The proposed circuits were designed on FPGA platform. The results of the asynchronous circuit show a nearly 20% increment in speed with about 12% reduction in power consumption in comparison with a synchronous circuit.

关键词： Power demand multicore processing Memory management Logic gates Delays Convolutional neural networks Proposals

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Developing Computer Applications without any OS or Kernel in a Multi-core Architecture

Developing Computer Applications without any OS or Kernel in...

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2021 international symposium on Networks, Computers and Communications, ISNCC 2021

作者： Ordouie, Navid Soundararajan, Nirmala Karne, Ramesh Wijesinha, Alexander L. Towson University Department Of Computer And Information Sciences Towson United States

ISBN: (纸本)9780738113166

Over the years, operating systems (OSs) have grown significantly in complexity and size providing attackers with more avenues to compromise their security. By eliminating the OS, it becomes possible to develop general-purpose non-embedded applications that are free of typical OS-related vulnerabilities. Such applications are simpler and smaller in size, making it easier secure the application code. Bare machine computing (BMC) applications run on ordinary desktops and laptops without the support of any operating system or centralized kernel. many BMC applications have been developed previously for single-core systems. We show how to build BMC applications for multicore systems by presenting the design and implementation of a novel UDP-based bare machine prototype Web server for a multicore architecture. We also include preliminary experimental results from running the server on the Internet. This work provides a foundation for building secure computer applications that run on multicore systems without the need for intermediary software. © 2021 ieee.

关键词： Web services

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Proceedings of the 2022 33rd ieee international Workshop on Rapid system Prototyping: Shortening the Path from Specification to Prototype, RSP 2022

Proceedings of the 2022 33rd IEEE International Workshop on ...

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33rd ieee international Workshop on Rapid system Prototyping, RSP 2022

ISBN: (纸本)9798350398519

The proceedings contain 9 papers. The topics discussed include: marine objects detection using deep learning on embedded edge devices;TernaryNERF: quantizing voxel grid-based NERF models;enhancing embedded AI-based object detection using multi-view approach;ANN-based performance estimation of embedded software for RISC-V processors;a case for second-level software cache coherency on many-core accelerators;early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system;automatically restructuring HDL modules for improved reusability in rapid synthesis;a framework that enables systematic analysis of mixed-signal applications on FPGA;and machine learning-based hard/soft logic trade-offs in VTR.

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Simultaneous Multithreading in Mixed-Criticality Real-Time systems 27

Simultaneous Multithreading in Mixed-Criticality Real-Time S...

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30th ieee international symposium on Software Reliability Engineering (ISSRE)

作者： Bakita, Joshua Ahmed, Shareef Osborne, Sims Hill Tang, Stephen Chen, Jingyuan Smith, F. Donelson Anderson, James H. Univ N Carolina Dept Comp Sci Chapel Hill NC 27515 USA

ISBN: (纸本)9781665403863

Simultaneous multithreading (SMT) enables enhanced computing capacity by allowing multiple tasks to execute concurrently on the same computing core. Despite its benefits, its use has been largely eschewed in work on real-time systems due to concerns that tasks running on the same core may adversely interfere with each other. In this paper, the safety of using SMT in a mixed-criticality multicore context is considered in detail. To this end, a prior open-source framework called MC2 (mixed-criticality on multicore), which provides features for mitigating cache and memory interference, was re-implemented to support SMT on an SMT-capable multicore platform. The creation of this new, configurable MC2 variant entailed producing the first operating-system implementations of several recently proposed real-time SMT schedulers and tying them together within a mixed-criticality context. These schedulers introduce new spatial-isolation challenges, which required introducing isolation at both the L2 and L3 cache levels. The efficacy of the resulting MC2 variant is demonstrated via three experimental efforts. The first involved obtaining execution data using a wide range of benchmark suites, including TACLeBench, DIS, SD-VBS, and synthetic microbenchmarks. The second involved conducting a large-scale overhead-aware schedulability study, parameterized by the collected benchmark data, to elucidate schedulability tradeoffs. The third involved experiments involving case-study task systems. In the schedulability study, the use of SMT proved capable of increasing platform capacity by an average factor of 1.32. In the case-study experiments, deadline misses of highly critical tasks were never observed.

关键词： multicore processing Multithreading Random access memory Interference Benchmark testing Real-time systems Safety

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Florian: Developing a Low-Power RISC-V multicore Processor with a Shared Lightweight FPU

Florian: Developing a Low-Power RISC-V Multicore Processor w...

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international symposium on Low Power Electronics and Design (ISLPED)

作者： Jina Park Kyuseung Han Eunjin Choi Sukho Lee Jae-Jin Lee Woojoo Lee Massoud Pedram School of Electrical and Electronics Engineering Chung-Ang University Korea AI SoC Research Division Electronics and Telecommunications Research Institute (ETRI) Korea Department of Electrical and Computer Engineering University of Southern California USA

As applications running on lightweight RISC-V processors become increasingly diverse and complex, the need for multicore processors supporting floating-point units (FPUs) is riseing, making processor designs using existing open-source RISC-V cores challenging. With the exception of a very few, most open lightweight RISC-V cores are integer cores without FPUs, which greatly reduces the design exploration space, making it impossible to design a processor optimized for each application. For example, most of these applications mainly perform integer operations, but occasionally perform floating-point operations. For them, a multicore processor with FPU per core is overkill and wastes power, which is a critical problem for processors where low-power design is paramount. To address the problem, we propose an external lightweight FPU that can be attached to any RISC-V integer core and a low-power multicore architecture using the designed FPU. For verification, we designed a RISC-V processor that implements all the proposed technologies, prototyped it on an FPGA device, and finally fabricated it as a system-on-chip. Through experiments, it was confirmed that the proposed technology can cut energy consumption energy by up to 23%.

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HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Computing from embedded to High-Performance systems

HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Compu...

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ieee international Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Cyril Koenig Björn Forsberg Luca Benini ETH Zurich Zurich Switzerland RISE Research Institutes of Sweden Kista Sweden Università di Bologna Bologna Italy

ISBN: (数字)9798350380408

ISBN: (纸本)9798350380415

Heterogeneous computing systems couple a general-purpose host processor with a single or multiple domain-specific accelerators. Generally, embedded systems exploit heterogeneity to increase energy efficiency through on-chip accelerators, while high-performance architectures leverage it for higher performance through powerful off-chip resources. In both cases, heterogeneity comes with programmability and portability challenges. In this work, we present HeroSDK, a software development kit (SDK) that facilitates both application developers and platform designers of RV-based heterogeneous accelerated computing systems. For developers, HeroSDK facilitates programming by offering OpenMP-based offloading and a device management library. For designers, it boosts portability by segmenting its codebase into platform-agnostic and platform-specific regions. We demonstrate HeroSDK on two open-source systems-on-chip coupling RISC-V 64-bit host processors with RISC-V 32-bit multi-core accelerators. By emulating these platforms on FPGA, we measure an overhead as small as 98k clock cycles to offload the simplest OpenMP regions within Linux user space applications. Additionally, we benchmark matrix-vector operations for both platforms and measure up to 5.9× speedup with a 19 % offload-to-work ratio using eight accelerator cores. Finally, we propose a kernel module to extend the HeroSDK capabilities to off-chip PCIe accelerator cards while reusing 100 % of its codebase.

关键词： Runtime library multicore processing Linux Programming Vectors Libraries system-on-chip Kernel Hardware acceleration Software development management

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Infrastructure for Exploring SIMT Architecture in General-Purpose Processors

Infrastructure for Exploring SIMT Architecture in General-Pu...

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ieee international symposium on Performance Analysis of systems and Software

作者： Nikitha Karman Kevin Wei Dylan Scott Natheesan Ratnasegar Oğuzhan Canpolat Hieu Mai Michael Ferdman BITS Pilani Stony Brook University TOBB ETU

ISBN: (数字)9798350376388

ISBN: (纸本)9798350376395

Single-Instruction Multiple-Thread (SIMT) computing has enabled a revolution in graphics, high-performance computing, and artificial intelligence. However, despite its benefits in these domains, SIMT processing has been relegated to accelerators rather than becoming a feature of general-purpose computing. Although a number of recent works have explored the potential benefits of “G PSIMT,“ current research infrastructures to study high performance general-purpose CPUs provide no support for the SIMT architecture and its programming model. This work presents our initial efforts toward developing a full-system GPSIMT research infrastructure. We first describe how we extend the QEMU emulator with SIMT features, enabling ISA pathfinding for GPSIMT hardware and providing a platform for the rapid development of system software for GPSIMT. We then present our approach to leveraging the chip yard hardware gen-eration framework to develop a full-system GPSIMT exploration platform on an FPGA by extending the RISC- V Rocket core.

关键词： Graphics Rockets Program processors multicore processing High performance computing Prototypes Computer architecture

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Boosting CPU Performance using Pipelined Branch and Jump Folding Hardware with Turbo Module

Boosting CPU Performance using Pipelined Branch and Jump Fol...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Mong Tee Sim University of Colorado Colorado Springs Colorado USA

ISBN: (纸本)9781728187525

The new generation of embedded applications demands both high performance and energy efficiency. This paper presents a new hardware design to support architecture-level thread isolation, together with logics to fold the branch and jump instructions and a Turbo module, thereby reducing the overall number of instructions flowing through the CPU without causing any pipeline stalls. By pipelining the branch and jump folding logics from multiple threads of execution, the hardware can continuously operate at the peak CPU speed, with reduced power consumption by reducing the number of microcontrollers required in the system. We show that this novel technique can accelerate the system performance, increase the instruction per cycle up to 1.36, and with the Turbo module, up to 1.823, without requiring any extra programming effort by developers. We used the Dhrystone, coremark, and ten selected benchmark metrics to validate the performance and functionality of our system.

关键词： Measurement Power demand multicore processing Microcontrollers system performance Programming Multitasking

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