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Trends and Challenges in Ensuring Security for Low-Power and High-Performance embedded SoCs*

Trends and Challenges in Ensuring Security for Low-Power and...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Parisa Rahimi Amit Kumar Singh Xiaohang Wang Alok Prakash University of Essex South China University of Technology Nanyang Technological University

ISBN: (纸本)9781728187525

In recent years, security, power consumption, and performance have become the important issues in embedded SoCs’ design. With the growing number of embedded devices for automotive electronic and electric vehicles, real-time systems, robotics, artificial intelligence, smart technologies, or telecommunication, it is highly likely that these systems will be exposed to attacks or threats. Therefore, it is not easy to implement the security measure of such devices, and it becomes challenging while considering the performance and power issues due to limited available computing resources and often operating on batteries. In this paper, we survey the weaknesses of the embedded SoCs and examine the attacks, power consumption, and performance more closely with the main focus on Physical and Side-Channel attacks, which have not been surveyed previously. Along with the current trends and challenges, upcoming trends and challenges are also elaborated. This paper is intended to help the researchers and system designers in gaining deep insight into designing secure, power-efficient, and high-performance embedded SoCs in the future.

关键词： Performance evaluation Power demand Power measurement multicore processing Side-channel attacks Market research Real-time systems

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Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters

Detection of Cache Side Channel Attacks Using Thread Level M...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Pavitra Prakash Bhade Sharad Sinha Indian Institute of Technology Goa

ISBN: (纸本)9781728187525

Modern multiprocessor systems adopt optimization techniques to boost the speed of execution. These optimizations create vulnerabilities that can be exploited by attackers, thus causing security breaches. The hierarchical structure of cache memory where the Last Level Cache is a super set of previous levels and is shared between multiple cores of the processors creates an attack vector for cache side-channel attacks (SCA). In such attacks, the attacker is able to trace the pattern of victim process execution and correspondingly retrieve secret information by monitoring the shared cache. Mitigation techniques against such attacks trade off security against overall system performance. Hence, mitigation only when an attack is detected is needed. We propose an architecture-agnostic approach that uses hardware performance counters at run time and at thread level instead of current state of the art which use counters at system level to detect cache SCA. The proposed approach reduces the false positives by 48% when compared with system level approaches. Thus, the trade off with performance is also reduced and hence, the proposed approach is especially significant for embedded systems where processor cycle time is a limited resource.

关键词： Program processors embedded systems multicore processing system performance Side-channel attacks Hardware Security

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Linearly extensible system based interconnection network for multi-core multi-processor systems 8

Linearly extensible system based interconnection network for...

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8th international Conference on Computing for Sustainable Global Development, INDIACom 2021

作者： Gautam, Savita Umar, M. Sarosh Samad, Abdus University Women's Polytechnic F/O Engg. Tech. Aligarh Muslim University Aligarh India Z. H. College of Engg. Tech. Aligarh Muslim University Department of Computer Engineeering Aligarh India

ISBN: (纸本)9789380544434

multicore processor implementation for server, workstations and embedded multicore chips is a challenging task. The design decisions with underlying trends affect the performance of such systems. Conventionally, interconnection networks are designed to connect several nodes, each of them having different cores. However, the on-chip interconnection network between cores becomes a bottleneck as it is being shared by all the cores to cooperate while being solving a given problem. This paper presents a scalable Network-on-chip architecture which exploits the interconnection network to connect different many core processors. The proposed architecture is designed in analogy to linearly extensible multiprocessor networks which have simple architecture and lesser cost. The introduced architecture is symmetrical in nature and exhibits the desirable properties of similar networks with lesser complexity and cost. A basic (4 x 4), 16-core architecture named as CA network is introduced which is symmetrically extendable at higher level with increasing number of cores. The topological variables such as number of cores, number of links, diameter and bisection width are evaluated for CA network and a comparative study is carried out with Mesh and Torus networks in order to validate the ascendancy of the proposed architecture. The proposed CA network has low diameter, low cost and performs better with lesser number of nodes. It is scalable and expandable easily at higher levels with lesser complexity. © 2021 Bharati Vidyapeeth, New Delhi. Copy Right in Bulk will be transferred to ieee by Bharati Vidyapeeth.

关键词： Topology

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Portability of Vectorization-aware Performance Tuning Expertise across system Generations

Portability of Vectorization-aware Performance Tuning Expert...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Shunpei Sugawara Yoichi Shimomura Ryusuke Egawa Hiroyuki Takizawa Graduate School of Information Sciences Tohoku University Cyberscience Center Tohoku University Tokyo Denki University

ISBN: (纸本)9781728187525

Even HPC expert programmers need to invest considerable time and effort in empirically establishing effective performance tuning strategies for their target systems. When the target system is changed and/or updated, it is thus preferable for expert programmers if their performance tuning expertise can be ported to the new system as much as possible. In this paper, we focus on multiple generations of NEC SX series vector systems. We have documented the performance tuning expertise for the previous generations and built a machine-usable database of performance tuning cases. Therefore, this paper investigates how much the recorded expertise in the database can contribute to performance tuning for the latest generation, NEC SX-Aurora TSUBASA (SX-AT). Since the system architecture as well as the software stack such as compilers are totally renewed for SX-AT, this paper discusses the differences in performance tuning across system generations. In addition, this paper also discusses how to express performance tuning techniques in a machine-usable way. The case study in this paper indicates that the Xevolver's approach of using user-defined code transformations can express most of the vectorization-aware performance tuning techniques, and is thus promising for recording the performance tuning expertise in a future-proof fashion.

关键词： Codes Databases multicore processing systems architecture Software Tuning

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An Architecture to Enable Machine-Learning-Based Task Migration for Multi-core Real-Time systems

An Architecture to Enable Machine-Learning-Based Task Migrat...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Octavio Delgadillo Bernhard Blieninger Juri Kuhn Uwe Baumgarten fortiss GmbH Research Institute of the Free State of Bavaria Munich Germany Technical University of Munich Munich Germany

ISBN: (纸本)9781728187525

ECU consolidation is an automotive trend that tends to reduce the number of electronic devices in a vehicle to optimize resources and costs. However, its implementation introduces new challenges, especially in terms of safety. Research at our group is exploring the idea of task migration between different electronic-control-units (ECUs) to add redundancy and fail-safety capabilities to an automotive setup. In particular, we are exploring machine-learning-aided schedulability analysis strategies as means to decide which ECU a task should be mapped to. In this paper. we present the implementation of an architecture that allows for testing different machine-learning techniques for schedulability analysis, enabling the deployment of tasks to the respective ECUs and a simple migration of tasks between them. The architecture is based on a real-time operating system. The test system developed implements a mix of dummy tasks with constant execution times and an autonomous task that interacts with a virtual environment and with a variable execution time. Also, the architecture allows for collecting data on each task for proving if the executed task sets are actually schedulable, as predicted by the machine learning component.

关键词： multicore processing Operating systems Redundancy Virtual environments Machine learning Real-time systems Safety

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Scheduling DAGs of Multi-Version Multi-Phase Tasks on Heterogeneous Real-Time systems

Scheduling DAGs of Multi-Version Multi-Phase Tasks on Hetero...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Julius Roeder Benjamin Rouxel Clemens Grelck University of Amsterdam Amsterdam The Netherlands

ISBN: (纸本)9781728187525

Heterogeneous high performance embedded systems are increasingly used in industry. Nowadays, these platforms embed accelerator-style components, such as GPUs, alongside different CPU cores. We use multiple alternatives/versions/implementations of tasks to fully benefit from the heterogeneous capacities of such platforms and due to binary incompatibility. Implementations targeting accelerators not only require access to the accelerator but also to a CPU core for, e.g., pre-processing and branching the control flow. Hence, accelerator workloads can naturally be divided into multiple phases (e.g. CPU, GPU, CPU). We propose an asynchronous scheduling approach that utilises multiple phases and thereby enables a finegrained scheduling of tasks that require two types of hardware. We show that our approach can increase the schedulability rate by up 24% over two multi-version phase-unaware schedulers. Additionally, we demonstrate that the schedulability rate of our heuristic is close to the optimal schedulability rate.

关键词： Industries Job shop scheduling embedded systems multicore processing Graphics processing units Optimal scheduling Hardware

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Dynamic Service Recommendation Using Lightweight BERT-based Service Embedding in Edge Computing

Dynamic Service Recommendation Using Lightweight BERT-based ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Kungan Zeng Incheon Paik School of Computer Science and Engineering University of Aizu Aizuwakamatsu Japan

ISBN: (纸本)9781728187525

With the rapid development of the Internet of Things (IoT) as well as edge computing, and fog computing, many microservices are being created. Service recommendation based on these distributed environments is an important issue for boosting the utilization of services since service composition in edge and cloud computing has increasingly attracted attention. However, the direct application of traditional service recommendation methods in edge computing encounters several problems such as insufficient computing resources, and the dynamic update of recommendation systems. This paper presents a deep learning-based approach for dynamic service recommendations using lightweight BERT-based service embedding to address the problems. First, a lightweight BERT-based service embedding was proposed to learn the practical-value vector of service based on the invocation association. Second, based on service embedding, a content-based filtering method is utilized to perform service recommendations. Next, a dynamic update process is implemented on the system by fine-tuning the model. Finally, the experimental results show that our approach can perform service recommendations effectively.

关键词： Cloud computing multicore processing Filtering Computational modeling Microservice architectures Dynamic scheduling Boosting

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Text Compression Based on an Alternative Approach of Run-Length Coding Using Burrows-Wheeler Transform and Arithmetic Coding

Text Compression Based on an Alternative Approach of Run-Len...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Md. Atiqur Rahman Mohamed Hamada Md Asfaqur Rahman School of Computer Science and Engineering The University of Aizu Fukushima Japan Islamic University Kushtia Bangladesh

ISBN: (纸本)9781728187525

In modern life, communication via text is becoming one of the most popular means of communication. As a result, storing text in a small format or transferring it quickly over the internet has become a challenging issue, and text compression has become an important research field. many algorithms for text compression have already been developed, and new algorithms are being devised to fulfil the demands of current technology. This research article proposes a text compression technique based on: (i) the Burrows-Wheeler transform; (ii) an alternative method of run-length coding; (iii) finding repeated patterns more frequently; and (iv) arithmetic coding. The proposed approach is compared with other state-of-the-art methods, and gives better performance in terms of compression ratios.

关键词： Technological innovation multicore processing Transforms Encoding Arithmetic

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FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning Tasks

FPGA based Adaptive Hardware Acceleration for Multiple Deep ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yufan Lu Xiaojun Zhai Sangeet Saha Shoaib Ehsan Klaus D. McDonald-Maier School of Computer Science and Electronic Engineering University of Essex Colchester UK

ISBN: (纸本)9781728187525

Machine learning, and in particular deep learning (DL), has seen strong success in a wide variety of applications, e.g. object detection, image classification and self-driving. However, due to the limitations on hardware resources and power consumption, there are many challenges to deploy deep learning algorithms on resource-constrained mobile and embedded systems, especially for systems running multiple DL algorithms for a variety of tasks. In this paper, an adaptive hardware resource management system, implemented on field-programmable gate arrays (FPGAs), is proposed to dynamically manage the on-chip hardware resources (e.g. LUTs, BRAMs and DSPs) to adapt to a variety of tasks. Using dynamic function exchange (DFX) technology, the system can dynamically allocate hardware resources to deploy deep learning units (DPUs) so as to balance the requirements, performance and power consumption of the deep learning applications. The prototype is implemented on the Xilinx Zynq UltraScale+ series chips. The experiment results indicate that the proposed scheme significantly improves the computing efficiency of the resource-constrained systems under various experimental scenarios. Compared to the baseline, the proposed strategy consumes 38% and 82% of power in low working load cases and high working load cases, respectively. Typically, the proposed system can save approximately 75.8% of energy.

关键词： Deep learning Power demand Heuristic algorithms Classification algorithms Table lookup system-on-chip Resource management

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RELAX: a REconfigurabLe Approximate Network-on-chip

RELAX: a REconfigurabLe Approximate Network-on-Chip

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Richard Fenster Sébastien Le Beux Concordia University Montréal Canada

ISBN: (纸本)9781728187525

The high error-resilience of numerous applications such as neural networks and signal processing led to new optimization opportunities in manycore systems. Indeed, approximate computing enable the reduction of data bit size, which allows to relax design constraints of computing resources and memory. However, on-chip interconnects can hardly take advantage of the reduced data size since they also need to transmit plain sized data. Consequently, existing approximate networks-on-chip (NoCs) either involve additional physical layers dedicated to approximate data or significantly increase the energy to transfer non-approximate data. To solve this challenge, we propose RELAX, a reconfigurable network-on-chip that can operate in an accurate data only mode or a mixed mode. The mixed mode allows for concurrent accurate and approximate data transactions using the same physical layer, hence allowing the efficient transmission of approximate data while reducing the resources overhead. Synthesis and simulation results show that RELAX improves communication latency of approximate data up to 44.2% when compared to an accurate data only, baseline 2D-Mesh NoC.

关键词： multicore processing Simulation Image processing Neural networks Network-on-chip Signal processing Physical layer

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