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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Evaluation of Performance in AUTOSAR Micro-ECUs using dedicated system cores on a Multi-core Processor 13

Evaluation of Performance in AUTOSAR Micro-ECUs using dedica...

引用

13th ieee/ACM international Workshop on Network on chip Architectures (NoCArc)

作者： Urbina, Moises Obermaisser, Roman Univ Siegen Inst Embedded Syst Siegen Germany

ISBN: (纸本)9781728191515;9781728184593

Multi-Processor system-on-a-chips (MPSoCs) are becoming a preferred option for the development of automotive embedded systems. The multicore version of AUTOSAR proposes a master/slave approach for the distribution of the AUTOSAR Basic Software running on a shared-memory multicore processor. However, a multicore processor which uses network-on-chips for the inter-core communication provides several advantages to the AUTOSAR system (e.g., fault isolation, temporal predictability). The presented work offers an evaluation of performance of the TIme-triggered MEssage-based AUTOSAR (TIMEA) multicore platform when using dedicated system cores for hardware acceleration. These system cores replace expensive functionalities of the Basic Software for off-chip communication support and memory abstraction services. Several automotive use case scenarios are implemented within a co-simulation framework which allow us to compare the automotive application performance, the operating system overhead and the reliability of the system with and without the employment of the system cores.

关键词： Network-on-chip

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2QoSM: A Q-Learner QoS Manager for Application-Guided Power-Aware systems

2QoSM: A Q-Learner QoS Manager for Application-Guided Power-...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Michael J. Giardino Daniel Schwyn Bonnie Ferri Aldo Ferri Systems Group Zürich Switzerland School of Mechanical Engineering Georgia Institute of Technology Atlanta United States School of Electrical Engineering Georgia Institute of Technology Atlanta United States

ISBN: (纸本)9781728187525

This paper describes the design and performance of Q-learning-based quality-of-service manager (2QoSM) for compute-aware applications (CAAs) as part of platform-agnostic resource management framework. CAAs and hardware are able to share metrics of performance with the 2QoSM and the 2QoSM can attempt to reconfigure CAAs and hardware to meet performance targets. This enables many co-design benefits while allowing for policy and platform portability. The use of Q-Learning allows online generation of the power management policy without requiring details about system state or actions, and can meet different goals including error, power minimization, or a combination of both. 2QoSM, evaluated using an embedded MCSoC controlling a mobile robot, reduces power compared to the Linux on-demand governor by 38.7-42.6% and a situation-aware governor by 4.0-10.2%. An error-minimization policy obtained a reduction in path-following error of 4.6-8.9%.

关键词： Measurement Training Q-learning Machine learning algorithms Power system management Linux Quality of service

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Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes

Multi-objective Reinforcement Learning for Energy Harvesting...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Shaswot Shresthamali Masaaki Kondo Hiroshi Nakamura Keio University The University of Tokyo

ISBN: (纸本)9781728187525

Modern Energy Harvesting Wireless Sensor Nodes (EHWSNs) need to intelligently allocate their limited and unreliable energy budget among multiple tasks to ensure long-term uninterrupted operation. Traditional solutions are ill-equipped to deal with multiple objectives and execute a posteriori tradeoffs. We propose a general Multi-objective Reinforcement Learning (MORL) framework for Energy Neutral Operation (ENO) of EHWSNs. Our proposed framework consists of a novel Multi-objective Markov Decision Process (MOMDP) formulation and two novel MORL algorithms. Using our framework, EHWSNs can learn policies to maximize multiple task-objectives and perform dynamic runtime tradeoffs. The high computation and learning costs, usually associated with powerful MORL algorithms, can be avoided by using our comparatively less resource-intensive MORL algorithms. We evaluate our framework on a general single-task and dual-task EHWSN system model through simulations and show that our MORL algorithms can successfully tradeoff between multiple objectives at runtime.

关键词： Wireless communication Wireless sensor networks Runtime Costs multicore processing Heuristic algorithms Computational modeling

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Analyzable Publish-Subcribe Communication Through a Wait-Free FIFO Channel for MPSoC Real-Time Applications

Analyzable Publish-Subcribe Communication Through a Wait-Fre...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Saeid Dehnavi Dip Goswami Kees Goossens Eindhoven University of Technology The Netherlands

ISBN: (纸本)9781728187525

As a transparent communication protocol for concurrent distributed applications, the Publish-Subscribe (Pub-Sub) paradigm is a trending programming model in many recent industrial use-cases in robotics and avionics. To apply the Pub-Sub programming model for safety-critical concurrent realtime applications in Multi-Processor systems on chip (MPSoC) environments, a non-blocking wait-free First-In-First-Out (FIFO) channel is a fundamental requirement. However, the proposed approaches in the literature have no proven real-time guarantees. In this paper, we propose a novel wait-free FIFO approach for single-producer-single-consumer core-to-core communication through shared memory. By analyzing the execution paths of each involved process, we prove that the execution time of each read/write operation is bounded by a Worst Case Execution Time (WCET). Moreover, we define a Timed Automata model of our approach. Using the UPPAAL model checker, we prove freedom of deadlock and starvation. For the performance evaluation of the proposed approach, we apply a stochastic analysis technique on the defined UPPAAL model. Finally, we implement the proposed approach on the CompSOC platform as the underlying realtime MPSoC to show that the implementation conforms to the proposed formal model and to experimentally validate the formal properties. The experimental evaluation on an instance of CompSOC that works at 40 MHz has a throughput of 109K tokens per second.

关键词： Performance evaluation Protocols Service robots Stochastic processes Publish-subscribe Programming system recovery

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Checkpointing-Aware End-to-End Data Age Analysis of Task Chains under Transient Faults

Checkpointing-Aware End-to-End Data Age Analysis of Task Cha...

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international symposium on Object-Oriented Real-Time Distributed Computing

作者： Sridhar Mallareddy Pavan Kumar Kondooru Deepak Gangadharan IIIT Hyderabad India

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

Safety-critical real-time systems are conventionally designed to meet specific hard real-time deadline requirements. many applications in such systems consist of task chains, which exhibit complex temporal dependencies based on the activation rates of the tasks. As a result, there has been an increasing interest in analyzing the age of data (i.e., the time elapsed since the data was first updated) that propagates through the task chains as an important system performance parameter. Transient faults in safety-critical systems can lead to undesirable consequences. One of the most common methods used for fault tolerance in such systems is checkpointing. However, the interference due to checkpointing can significantly impact the data age, reducing the predictability of the system’s *** paper proposes an analytical framework for calculating the data age in real-time task chains with checkpointing for transient faults in both single-core and multi-core platforms. The proposed analysis has been validated by comparing it with extensive simulations of the execution of real-time task chain-based systems under faults. It shows comparable data age values with low time complexity.

关键词： Checkpointing Fault tolerance multicore processing Fault tolerant systems Distributed databases Interference Real-time systems

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RVcoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions

RVCoreP-32IC: An optimized RISC- V soft processor supporting...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Takuto Kanamori Kenji Kise School of Computing Tokyo Institute of Technology Tokyo Japan

ISBN: (纸本)9781728187525

The compressed instructions extension in RISC-V reduces the program size. However, it needs a complicated logic for the instruction fetch unit and has an impact on performance. In this paper, we propose an instruction fetch unit that supports the compressed instructions achieving high performance. Furthermore, we propose a RISC-V soft processor using this unit. We implement this proposed processor in Verilog HDL and verify the behavior using Verilog simulation and a Xilinx Artix-7 FPGA board. We compare the results of some benchmarks and the amount of hardware with related works. From the evaluation results, we show that the proposed processor achieves 42.5% performance improvement compared with VexRiscv, which is a high-performance and open source RV32IC processor.

关键词： multicore processing Memory management Benchmark testing Hardware Hardware design languages Field programmable gate arrays

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Efficient Resource Shared RISC-V multicore Processor

Efficient Resource Shared RISC-V Multicore Processor

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Md Ashraful Islam Kenji Kise School of Computing Tokyo Institute of Technology Tokyo Japan

ISBN: (纸本)9781728187525

Edge computing pushes the computational loads from the cloud to embedded devices, where data would be processed near the data source. Heterogeneous multicore architecture is believed to be a promising solution to fulfill the edge computational requirement. In FPGAs, the heterogeneous multicore is realized as multiple soft processor cores with custom processing elements. Since FPGA is a resource-constrained device, sharing the hardware resources among the soft processor cores can be advantageous. Some research has focused on the sharing resources among soft processors, but they do not study how much FPGA logic is minimized for a five-stage pipeline processor. This paper proposes the microarchitecture of a five-stage pipeline scalar processor that enables the sharing of functional units for execution among the multiple cores. We then investigate the performance and hardware resource utilization for a four-core processor. We find that sharing different functional units can save the LUT usage to 23.5% and DSP usage to 75%. We analyze the performance impact of sharing from the Embench benchmark program by simulating the same program in all four cores. Our simulation results indicate that based on the sharing configuration, the average performance drops from 2.9% to 22.3%.

关键词： Microarchitecture multicore processing Simulation Soft sensors Pipelines Computer architecture Hardware

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A Distance Estimation Method to Railway Crossing Using Warning Signs

A Distance Estimation Method to Railway Crossing Using Warni...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Kaisei Shimura Yoichi Tomioka Qiangfu Zhao School of Computer Science and Engineering University of Aizu Fukushima Japan

ISBN: (纸本)9781728187525

A mobility scooter has come to be used to expand the range of mobility for the elderly. On the other hand, accidents involving mobility scooters have become serious problems. For example, if a mobility scooter stops inside a railway crossing due to battery exhaustion, it is very dangerous because accidental contact with a train may happen. Measuring the distance to a railway crossing during driving is helpful to avoid entrance to a railway crossing without enough battery. In this paper, we propose a method for predicting the distance to a railroad crossing based on the railway crossing warning signs in the video from a camera installed in front of the mobility scooter. In experiments, we evaluate the proposed method using images taken at various positions in relation to the railway crossing and show that the proposed method achieves higher accuracy than the distance estimation using a depth sensor.

关键词： multicore processing Estimation Motorcycles Wheels Cameras Rail transportation Battery charge measurement

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Configuring an embedded Neuromorphic Coprocessor Using a RISC-V chip for Enabling Edge Computing Applications

Configuring an Embedded Neuromorphic Coprocessor Using a RIS...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Evelina Forno Andrea Spitale Enrico Macii Gianvito Urgese Politecnico di Torino Torino (TO) ITALY

ISBN: (纸本)9781728187525

Neuromorphic hardware shows promising potential for employment in edge computing applications, as it can provide real-time and low-power elaboration of complex data directly on edge using computational paradigm based on Spiking Neural Networks (SNNs). However, such systems cannot be deployed as edge devices by themselves, as they require an external host for configuration and data input management. In this paper, we present a chip-level integrated system performing on-edge configuration of a neuromorphic platform. The proposed solution makes use of two existing open-source platforms: the low-power RISC-V processor Rocket chip and the digital SNN processor ODIN. We built the two systems into a single SoC using the chipyard framework, and connected them by designing a communication interface using ODIN's SPI and AER input/output ports. We validated the system by RTL simulation of a synfire chain running on ODIN, where Rocket chip sets up configuration of the network, triggers the first spike, then collects the simulation results. The synthesized design utilizes a modest amount of resources on a PYNQ-Z2 board: 16% of LUT slices, 11% of Block RAMs and 8 pins, leaving plenty of room to integrate other peripherals or systems. The present work represents a first step towards seamless integration of neuromorphic technologies with state-of-the-art processors, improving on the ease of use of neuromorphic devices and leading the way into widespread use of SNN coprocessors in edge computing applications.

关键词： Rockets Neuromorphics Simulation Process control Hardware Central Processing Unit Table lookup

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EEG-based Positive-Negative Emotion Classification Using Machine Learning Techniques

EEG-based Positive-Negative Emotion Classification Using Mac...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yuta Kasuga Jungpil Shin Md. Al Mehedi Hasan Yuichi Okuyama Yoichi Tomioka University of Aizu Aizuwakamatsu Japan

ISBN: (纸本)9781728187525

The aim of this study is to find useful electrodes for positive-negative emotion classification based on EEG. We collected EEG signals from 30 people aged 19-38 using 14 electrodes. We used two movies for positive and negative emotions. First, we extracted the power spectrum from the EEG data, normalized the data, and extracted frequency-domain statistical parameters therefrom. When the features were applied to Random Forests (RF), 85.4%, 83.8%, and 83.4% accuracy was obtained for P8, P7, and FC6 electrodes, respectively. This indicates that the P8, P7 and FC6 electrodes are the useful electrode in positive-negative emotion classification.

关键词： Electrodes Radio frequency multicore processing Frequency-domain analysis Training data Feature extraction Motion pictures

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