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Multiport Register File Design for High-Performance embedded cores

Multiport Register File Design for High-Performance Embedded...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Junichiro Kadomoto Hidetsugu Irie Shuichi Sakai University of Tokyo Tokyo Japan

ISBN: (纸本)9781728187525

As the application areas of embedded SoCs continue to expand, there is a need to adopt general-purpose cores with higher performance. One method of achieving higher performance in general-purpose processors is to use superscalar execution, which exploits instruction-level parallelism to achieve higher performance by simultaneously executing multiple instructions. As the number of parallel execution lanes of the processor increases, more ports are required in the internal memory structures, including a register file, to enable reading or writing multiple data in parallel. As the number of ports increases, the power consumption and area of the register file become larger, and the design becomes exceedingly complex. Therefore, an elaborate design space exploration of such register files is crucial for developing higher-performance cores. In this paper, we discuss the design of multiport register files, especially for 32-bit out-of-order superscalar processors, and investigate the design space through SPICE simulations.

关键词： Semiconductor device modeling Program processors Power demand multicore processing Simulation Random access memory Writing

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Distributed Neural Network with TensorFlow on Human Activity Recognition Over multicore TPU

Distributed Neural Network with TensorFlow on Human Activity...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Haklin Kimm Incheon Paik East Stroudsburg University East Stroudsburg PA USA School of Computer Science and Engineering University of Aizu Aizu-Wakamatsu City Fukushima Japan

ISBN: (纸本)9781728187525

There have been increasing interests and success of applying deep learning neural networks to their big data platforms and workflows, say Distributed Deep Learning. In this paper, we present distributed long short-term memory (dLSTM) neural network model using TensorFlow over multicore Tensor Processing Unit (TPU) on Google Cloud. LSTM is a variant of the recurrent neural network (RNN), which is more suitable for processing temporal sequences. This model could extract human activity features automatically and classify them with a few model parameters. In the proposed model, the raw data collected by mobile sensors was fed into distributed multi-layer LSTM layers. Human activity recognition data from UCI machine-learning library have been applied to the proposed distributed LSTM (dLSTM) model to compare the efficiency of TensorFlow over CPU and TPU based on execution time, and evaluation metrics: accuracy, precision, recall and F1 score along with the use of Google Colab Notebook.

关键词： Deep learning Measurement Tensors Recurrent neural networks multicore processing Distributed databases Activity recognition

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Inter-core Communication Mechanisms for Microkernel Operating system based on Signal Transmission and Shared Memory 7

Inter-Core Communication Mechanisms for Microkernel Operatin...

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7th international symposium on system and Software Reliability, ISSSR 2021

作者： Liu, Cheng Luo, Lei Li, Meng Lei, Pinyuan Chen, Lirong Xiao, Kun University of Electronic Science and Technology of China School of Computer Science and Engineering Chengdu China University of Electronic Science and Technology of China School of Information and Software Engineering Chengdu China

ISBN: (纸本)9781665434317

With the coming of the Internet of things(IoT) era and the development of semiconductor equipment, multicore processors have begun to be widely used in IoT devices to meet their requirements for powerful processing capabilities. Unlike desktop or server operating systems such as Linux, current embedded operating systems often do not support multi-core processors well. Tasks on different cores often require information exchange, known as inter-core communication, which significantly impacts the processing performance of multi-core operation systems. In this paper, we proposed an inter-core communication method based on signal transmission and shared memory, which is flexible and various types of data can be transferred efficiently. We have implemented and experimented with it on our own microkernel operating system named Mginkgo. The experimental results show that the average time to trigger an inter-core interrupt is about 0.093 microseconds. The average inter-core interrupt processing time is about 3.986 microseconds. And the communication time of the system for multi-core Inter-Process Communication(IPC) is about 18us, which is the same as that of single-core IPC. The inter-core communication method proposed in this paper achieves very low latency with almost no performance consumption and maintains the high performance of the whole system. © 2021 ieee.

关键词： Internet of things

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Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Performance Estimation of High-Level Dataflow Program on Het...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Aurelien Bloch Simone Casale Brunet Marco Mattavelli SCI-STI-MM École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781728187525

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programming paradigm is particularly well suited for heterogeneous parallel systems because it is inherently free of memory contention and exposes parallel opportunities. Both of these statements show the necessity for a way to easily and automatically evaluate and find good design configurations. The paper describes the methodology required for clock-accurate profiling of high-level dataflow programs written in RVL-CAL when synthesized on heterogeneous CPU/GPU co-processing platforms. It also extends to the heterogeneous paradigm an existing methodology for qualitatively estimating the performance of such programs as a function of the provided configuration. This, without the need to synthesize and profile every single configuration on the actual hardware platform. This approach is validated using two application programs and several configurations.

关键词： Program processors Processor scheduling multicore processing Computational modeling Estimation Programming Hardware

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Sparse Matrix Ordering Method with a Quantum Annealing Approach and its Parameter Tuning

Sparse Matrix Ordering Method with a Quantum Annealing Appro...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Tomoko Komiyama Tomohiro Suzuki Graduate School of Engineering University of Yamanashi Ko-fu Japan

ISBN: (纸本)9781728187525

Quantum annealing realizes quantum computers specialized for combinatorial optimization problems (COPs). A COP is formulated as a Hamiltonian, and quantum annealing obtains a solution by finding the ground state of the Hamiltonian. The ease of finding a solution depends on the weights assigned to the cost and constraint functions when formulating the problem. In other words, parameter tuning is essential in solving problems with quantum annealing. In the present paper, the problem of searching an ordering that reduces the fill-in for a sparse direct solver is formulated as a Hamiltonian, and quantum annealing finds the solution to this problem. We discuss the necessity and effectiveness of parameter tuning for solving COPs with quantum annealing. The results after weight tuning show that we can improve the rate of an optimal solution obtained by a maximum of 94% for ${5\,\times \,5}$ matrices, 68% for ${6\,\times \,6}$ matrices, and 27% for ${7\,\times \,7}$ matrices. Moreover, it is shown that giving high weights to the constraints we want to satisfy will not provide an optimal solution.

关键词： Annealing Costs multicore processing Stationary state Quantum annealing Search problems Cost function

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Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge Creation

Design of a Knowledge Experience Based Environment for Museu...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Hoshino Takayuki Yoshioka Rentaro Kohira Yukihide The Graduate School of Computer Science and Engineering University of Aizu Nihon Unisys Ltd. Technology Research & Innovation Tokyo Japan The Graduate School of Computer Science and Engineering University of Aizu Aizu-Wakamatsu Japan

ISBN: (纸本)9781728187525

Asystem to support and improve knowledge creation activity based on a sensor network is presented. This system aims to understand the experience of visitors to the museum and to gain learning that will lead to improved activities. The lessons learned from the visitor's experience at the museum can be interpreted in two different contexts: the visitor and the curator, but this paper deals with the curator's context. For curators, learning involves understanding the behavior/reactions of visitors to improve the museum experience through the curator's learning. The proposed system is designed to perform passive measurements to capture data about the movement of visitors on the exhibition floor along with various environmental data. The role of the system is to support curators in investigating, reasoning, and correlating data, and ultimately to the generation of useful knowledge that can be shared with colleagues. Currently, the observation components of the system are being developed, data is being collected daily at affiliated museums, and data exploration and knowledge creation environment are being developed for curators. In this paper, an example of designing an environments based on the concept of knowledge experience is presented. Evaluations of these designs are made by demonstrating possible analysis and interpretation of visitor behavior and the creation of corresponding knowledge based on the data collected. These findings provide insights on how to design systems that facilitate active knowledge creation.

关键词： Knowledge engineering Computers multicore processing Current measurement Knowledge based systems Semantics Machine learning

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Mini-Batch Training along Convolution Windows for Representation Learning Based on Spike-Time-Dependent-Plasticity Rule

Mini-Batch Training along Convolution Windows for Representa...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yohei Shimmyo Yuichi Okuyama Graduate School of Computer Science and Engineering The University of Aizu Fukushima Japan School of Computer Science and Engineering The University of Aizu Fukushima Japan

ISBN: (纸本)9781728187525

This paper presents a mini-batch training methodology along convolutional windows for layer-wised STDP unsupervised training on convolutional layers in order to shorten the training time of spiking neural networks (SNNs). SNN is a third-generation neural network that uses an accurate neuron model compared to rate-coded models used in conventional artificial neural networks (ANNs). The mini-batches of input convolution windows are convoluted at once. Then, the input, output, and current filter generate a batch of weight updates at once. This system reduces overheads of library calls or GPU execution. The batch processing methodology leads more significant and extensive models to be trained in ANNs, while many evaluations of direct SNN training methodologies are limited to smaller models. Currently, training large-scale models is virtually impossible. We evaluated the mini-batch processing effect on training speed and feature extraction power against various mini-batch sizes. The result showed that a larger mini-batch size enables us to utilize GPUs effectively, maintaining comparable feature extraction power. This research concludes that mini-batch training along convolution windows reduces training time by STDP training rule.

关键词： Training Representation learning Convolution multicore processing Neurons Graphics processing units Feature extraction

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A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-core CPU

A Computation-Aware TPL Utilization Procedure for Paralleliz...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Lan-Da Van Tao-Jung Wang Sing-Jia Tzeng Tzyy-Ping Jung National Yang Ming Chiao Tung University Taiwan Swartz Center for Computational Neuroscience University of California (UCSD) San Diego USA

ISBN: (纸本)9781728187525

Independent Component Analysis is a widely used machine learning technique to separate mixed signals into statistically independent components. This study proposes a computation-aware (CA) Task Parallel Library (TPL) utilization procedure to parallelize the Fast Independent Component Analysis (FastICA) algorithm on a multi-core CPU. The proposed CA method separates the complex from simple computations by exploring their execution times on a multi-core CPU. TPL is used for complex calculations, but not for simple ones. In comparison to the program without the TPL, the proposed CA procedure reduces the execution time of decomposing 8- and 32-channel artificially mixed signals by 34.88% and 43.01%, respectively. The proposed CA procedure reduces the execution time of decomposing 8- and 32-channel artificially mixed signals by 10.04% and 0.93%, respectively, compared to the fully parallelized program with TPL. Using CA TPL, the decomposition of 12-channel electroencephalograms (EEG) signals take 48.27% less time than without it. The proposed CA procedure reduces execution time by 15.12% compared to the fully parallelized program with TPL.

关键词： Machine learning algorithms multicore processing Independent component analysis Machine learning Electroencephalography Libraries Heterogeneous networks

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Data Fusion Driven Lane-level Precision Data Transmission for V2X Road Applications

Data Fusion Driven Lane-level Precision Data Transmission fo...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Albert Budi Christian Chih-Yu Lin Lan-Da Van Yu-Chee Tseng National Yang Ming Chiao Tung University Taiwan National Taiwan Ocean University Taiwan

ISBN: (纸本)9781728187525

Inter-vehicle communication is being developed continuously in order to accomplish a better driving experience. Through the exchange of information between vehicles and Road Side Unit (RSU), number of accidents can be reduced by notifying the driver through the facts obtained. In general, broadcast information for vehicles is sent in an ad hoc manner. However, unfiltered information may be useless and wasted for most vehicles. Thus, a raised question is whether precise information can be delivered only to the target vehicles without interfering with other non-target vehicles. A computer vision (CV) and sensor fusion-based transmission system are exchanged by RSU and Vehicle On-board Unit (OBU) is developed to attain this objective. In order to correctly transmit the specific information to the target vehicles, we propose a data fusion driven lane-level precision data transmission system that utilizes three kinds of sensory inputs: Road Side Camera (RSC), GPS, and magnetometer. By combining common features from these sensory inputs, our system is able to select the receiver of specific information on the road. Our system focuses on the scenario where a message can be transmitted to the target vehicles located in a certain lane. The experimental evaluation shows a recognition rate of 87.34% and the generated messages have a total delay less than 72 ms.

关键词： multicore processing Magnetometers Roads Road side unit Data integration Receivers Data communication

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UI Method to Support Knowledge Creation in Hybrid Museum Experience

UI Method to Support Knowledge Creation in Hybrid Museum Exp...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Toru Tamahashi Yoshioka Rentaro Hoshino Takayuki The Graduate School of Computer Science and Engineering University of Aizu Aizu-Wakamatsu Japan The Graduate School of Computer Science and Engineering University of Aizu Nihon Unisys Ltd. Technology Research & Innovation Tokyo Japan

ISBN: (纸本)9781728187525

A user interaction method to support knowledge creation in a hybrid museum experience is proposed and evaluated. The method incorporates a knowledge creation process of visitor experiences to the interaction scheme on the user interface based on two intentions. The first intention is to invoke user actions required for an effective knowledge experience, including individual learning. The second intention is to document the knowledge with sufficient information for sharing and reuse. The method is designed as part of an application for a hybrid museum experience such that the digital device does not distract the visitor from the museum exhibit. This paper presents the proposed UI interaction method, its implementation in the application, and an evaluation study of its effects. The evaluation was conducted with a group of curators to obtain professional feedback on the method's effect on observation behavior and knowledge creation. As a result, we found that the user interface of expressing one's own impressions and seeing the impressions of others helped to deepen the understanding of the exhibits.

关键词： Visualization multicore processing User interfaces

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