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Distributed Neural Networks using TensorFlow over multicore and many-core systems 13

Distributed Neural Networks using TensorFlow over Multicore ...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ranbirsingh, Jagadish Kumar Kimm, Hanke Kimm, Haklin East Stroudsburg Univ Dept Comp Sci East Stroudsburg PA 18301 USA

ISBN: (纸本)9781728148823

This paper focuses on distributed deep learning models that simulate the HAR (Human Activity Recognition) data set from the UCI machine learning Repository. The proposed deep learning LSTM (Long Short-Term Memory) model works with the TensorFlow framework using the Python 3 programming language which supports the distributed architecture. In order to simulate the distributed deep learning models over different multicore and many-core systems, two hardware platforms are built;the first one is equipped with a Raspberry Pi cluster with 16 Pi 3 model B+ boards which each having 1 GB of RAM and 32 GB flash storage. The second platform is houses an Octa-core Intel Xeon CPU system with a 16MB Cache, 32 GB RAM and 2 TB SSD primary storage with 10 TB HDD secondary storage. In this paper, the performance of the distributed LSTM model over multicore and many-core systems is presented in terms of execution speed and efficiency of prediction accuracy upon varying number of deep layers with corresponding hidden nodes. In this experiment, a 3 x 3 distributed LSTM model has been used, which furnishes higher prediction accuracy with faster computation time than the models that different number of layers provide.

关键词： Distributed LSTM Model TensorFlow multicore systems Human Activity Recognition

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Real-Time Attitude Estimation of Sigma-Point Kalman Filter via Matrix Operation Accelerator 13

Real-Time Attitude Estimation of Sigma-Point Kalman Filter v...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Dai, Zeyang Jing, Lei Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9781728148823

Attitude estimation is an important part for navigation of mobile robotics and unmanned aerial vehicle (UAV) control. Although the Extended Kalman Filter (EKF) can be done typically, the trend is to use Sigma-Point Kalman Filter (SPKF) instead due to its higher accuracy and robustness in harsh environment. The only drawback of such system is the higher computation cost. In order to accelerate the system, most approaches based on Field Programmable Gate Arrays (FPGA) are proposed in the past but too specific, which is not reusable and the high price for design complexity. With looking for re-usability, we present an IP core called matrix operation accelerator in this paper. Moreover, we do the verification on Zynq-7020, the experimental result shows that the proposed scheme can reduce about 50% computing time and save silicon as well.

关键词： real-time orientation estimation sigma-point kalman filter matrix operation accelerator system-on-chip

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Prototype of FPGA Dynamic Reconfiguration based-on Context-Oriented Programming 13

Prototype of FPGA Dynamic Reconfiguration based-on Context-O...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ohkawa, Takeshi Tanigawa, Ikuta Sato, Mikiko Hisazumi, Kenji Ogura, Nobuhiko Watanabe, Harumi Tokai Univ Dept Embedded Technol Tokyo Japan Kyushu Univ Dept Adv Informat Tech Fukuoka Japan Tokyo City Univ Dept Informat Syst Tokyo Japan

ISBN: (纸本)9781728148823

Acceleration by FPGA is expected for real-time edge processing as well as server applications in the cloud. A robot is one of the examples which need the acceleration of processing such as image recognition processing and actuation based on its visual feedback. As the system is more complex, it is required to introduce a management mechanism of FPGA dynamic reconfiguration. In this paper, we propose a method of system development which includes FPGA acceleration. The key idea of the proposed method is the FPGA reconfiguration based on a context, which is defined in Context-Oriented Programming (COP). This idea contributes to solve the cross-cutting concern problem at runtime. The problem causes to decrease the efficiency of development. Thus, this idea makes easily manage to FPGA reconfiguration with software in case of changing a whole system. In evaluation, we compare the reconfiguration time of FPGA to switch a context with the context switching time of the COP software written in C++ language. It indicates that the proposed method is feasible to handle FPGA context.

关键词： Dynamic Reconfiguration FPGA Context-Oriented Programming

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Statistical analysis for shared resources effects with multi-core real-time systems 13

Statistical analysis for shared resources effects with multi...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Durand, Julien Bouchebaba, Youcef Santinelli, Luca CPT P E&DS SE FR AET Toulouse France Off Natl Etud & Rech Aerosp DTIS Toulouse France

ISBN: (纸本)9781728148823

Today's multi-core and many-core COTS platforms make available a large amount of computational resource for real-time applications. As they aim at increasing performance for real-time, their challenges are the guarantees for timing constraints. Real-time modeling and analysis are thus facing shared resources, optimization mechanisms, and sophisticated functionalities which all combine into complex system dynamics that are extremely costly to characterize. This paper proposes a measurement-based approach and a statistical analysis applied to define average and worst-case models to task executions under different possible execution conditions. The framework is formalized and then used to investigate different families of shared resources interference effects occurring on multi-core platforms;such effects are quantified with statistical metrics applied to measurements of tasks execution times. The focus of the work is on effects due to shared memories within the NXP T4240 multi-core platform and the PikeOS hypervisor. A set of experiments is conducted to validate the framework proposed.

关键词： Task analysis Real-time systems Interference Timing Analytical models

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Performance tuning of tile matrix decomposition 13

Performance tuning of tile matrix decomposition

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Suzuki, Tomohiro Univ Yamanashi Dept Interdisciplinary Res Div Engn 4-3-11 Takeda Kofu Yamanashi 4008511 Japan

ISBN: (纸本)9781728148823

Task parallel algorithms have attracted attention as algorithms for highly parallel architectures in recent years. The aim of such algorithms is to keep all computing resources running without stalling by executing a large number of finegrained tasks asynchronously while observing data dependencies. The tile algorithm of matrix decomposition of dense matrices is implemented using a task parallel programming model following such an approach. In this article, we will consider how to select tile size, which is an important performance parameter.

关键词： matrix decomposition tile algorithm multi-core/many-core architecture

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A system Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration 13

A System Delay Monitor Exploiting Automatic Cell-Based Desig...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Okuhara, Hayate Kazami, Ryosuke Amano, Hideharu Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan

ISBN: (纸本)9781728148823

In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs;thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

关键词： Performance monitor Adaptive voltage control VLSI systems Low power design

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Efficient Search-Space Encoding for system-Level Design Space Exploration of embedded systems 13

Efficient Search-Space Encoding for System-Level Design Spac...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Richthammer, Valentina Glass, Michael Ulm Univ Ulm Germany

ISBN: (纸本)9781728148823

For Design Space Exploration (DSE) of embedded systems as a combinatorial Multi-Objective Optimization Problem (MOP), metaheuristic optimization approaches are typically employed to determine high-quality solutions within limited optimization time. This requires the encoding of implementations from the design space in a search space which represents the available degrees of freedom for the optimization approach. Determining an encoding that ensures all design constraints are met by construction is, however, impossible for multi-/many-core DSE problems, so that the search space contains infeasible solutions. While state-of-the-art DSE techniques repair infeasible solutions, little to no attention has been paid to the efficiency of the resulting encoding w.r.t. its suitability for the employed optimization approach. Therefore, we formally define requirements for an efficient search space and analyze the drawbacks of automatically generated inefficient encodings. We furthermore present efficient search-space encodings for a state-of-the-art hybrid optimization approach suitable for a wide range of MOPs. The proposed encodings significantly reduce the required degree of repair, allowing us to introduce a feedback loop from repaired solutions in the design space to the respective encoded solutions in the efficient search space to further improve the optimization. The positive effects of the proposed efficient encoding and design-space feedback are demonstrated for system-level DSE using benchmarks from the domains of embedded many-core as well as networked automotive systems. Compared to inefficient search spaces from literature, significant enhancements in both optimization quality and time are observed. Furthermore, we propose metrics to quantify search-space efficiency which provide novel insights into the interdependence of search space and design space for multi-/many-core DSE.

关键词： Design automation system-level design

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Tumour Detection using Convolutional Neural Network on a Lightweight Multi-core Device 13

Tumour Detection using Convolutional Neural Network on a Lig...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Teo, T. Hui Tan, Wei Ming Tan, Yi Shu Singapore Univ Technol & Design Sci & Math Cluster Singapore Singapore Singapore Univ Technol & Design Engn Prod Dev Singapore Singapore

ISBN: (纸本)9781728148823

Convolutional neural networks (CNN) have been the main driving force behind image classification and it is widely used. Large amounts of processing power and computation complexity is required to mimic our human brain as in the image classification. Such complexity may result in large bulky systems. A lack of such, while possible, may result in a rather limited use case and as such constrained functional implementation. One solution is to explore the use of multicore system on chips (MCSoC). CNN, however, were commonly built on Graphics Processing Units (GPUs) based machine. In this paper, we reduce the overall size of a CNN while retaining a satisfactory level of accuracy so that it is better suited to be deployed in an MCSoC environment. We trained a CNN model that was validated on detecting malignant tumor cells. The results show significant boost in functionality in the form of faster inference times and smaller model parameter sizes, deploying neural networks in an environment that would have otherwise seemed less practical. Efficient inference networks on lightweight systems can serve as an inexpensive and physically small alternative to existing Artificial Intelligence (AI) systems that are generally costly, bulky and power hungry.

关键词： Artificial Intelligence Convolutional Neural Network Deep Learning Machine Learning multicore system on chip

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Exploiting Model-Level Parallelism in Recurrent Neural Network Accelerators 13

Exploiting Model-Level Parallelism in Recurrent Neural Netwo...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Peng, Lu Shi, Wentao Zhang, Jian Irving, Samuel Louisiana State Univ Baton Rouge LA 70803 USA

ISBN: (纸本)9781728148823

Recurrent Neural Networks (RNNs) have continued to facilitate rapid progress in a variety of academic and industrial fields, though their complexity continues to make efficient deployment difficult;when the RNN model size is not properly matched to hardware resources, performance can suffer from hardware under-utilization. In this work, we propose to explore model-level parallelism for LSTM-RNN accelerators in different levels of the model using a multicore design. The multi-core design proposed in this work operates in three computing modes: multi-programming mode in which independent models are executed;multi-threading mode in which parallelism among layers of an LSTM model is explored and properly scheduled;and helper-core mode in which cores collaborate on a single LSTM layer in a lower model level comparing with multi-thread mode. Our design can achieve up to 1.98x speedup in "multi-programming" mode, a 1.91x speedup in "multi-threading" mode and a 1.88x speedup in "helper-core" mode over the single-core design.

关键词： Parallel processing Computational modeling Instruction sets Recurrent neural networks Hardware multicore processing

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Fault-tolerant Traffic-aware Routing Algorithm for 3-D Photonic Networks-on-chip 13

Fault-tolerant Traffic-aware Routing Algorithm for 3-D Photo...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Meyer, Michael Conrad Wang, Yu Watanabe, Takahiro Waseda Univ GS Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan Univ Aizu GS Comp Sci & Engn Aizu Wakamatsu Fukushima 9658580 Japan

ISBN: (纸本)9781728148823

As the number of cores on a single chip increased, the inter-core communication system quickly became the performance bottleneck. In order to solve the performance and scalability issues of bus-based systems, Network-on-chip (NoC) was proposed. This eventually met its own bottleneck and several technologies sprouted out from NoC research. The most commonly researched upgrade to NoCs was 3D NoCs, which utilized stacked routers to reduce the maximum hop count. Other researchers have looked at alternative transmission mediums, such as photonics. These technologies can be combined to give great performance and power benefits but can be slowed down by congestion in their path-setup phase. In order to solve this issue, we propose a traffic-aware routing algorithm that can evenly distribute the traffic throughout the chip, all while simultaneously avoiding faulty nodes. The results show that the proposed algorithm was successful in balancing the load across the chip and that the performance costs of the algorithm were mostly offset by the benefits of reducing blocked paths.

关键词： Fault-tolerant Traffic-aware Optical Router NoC High-performance Routing Algorithm many-core systems Microring

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