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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是21-30 订阅

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Privacy-stealing Approach in Distributed IoMT systems 16

Privacy-stealing Approach in Distributed IoMT Systems

引用

16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Wang, Haoda Zhao, Lingjun Qiu, Chen Lian, Zhuotao Su, Chunhua Univ Aizu Dept Comp Sci Aizu Wakamatsu Fukushima Japan Guangdong Polytech Normal Univ Sch Elect & Informat Guangzhou Peoples R China

ISBN: (纸本)9798350393613

Model or parameter sharing has been commonly used in many distributed learning architectures, e.g., federated learning. However, such a sharing mechanism may result in the risk of privacy leakage to the third party. In this paper, we represent an approach to medical image privacy stealing in the distributed Internet of Medical Things (IoMT) systems. Experiment results based on the real-world dataset show that, based on our approach, key characteristics of original medical images could be recovered in a third party, i.e., aggregation server.

关键词： Privacy leakage stealing medical image distributed system

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systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming 16

Systematic Construction of Deadlock-Free Routing for NoC Usi...

引用

16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Liu, Shuang Radetzki, Martin Univ Stuttgart Inst Comp Architecture & Comp Engn Embedded Syst Stuttgart Germany

ISBN: (纸本)9798350393613

Network-on-chip (NoC) presents a promising solution for on-chip communication in highly integrated system-on-chips (SoCs). This work addresses critical challenges in NoC design, including routing construction, application mapping, and particularly the issue of deadlocks in the widely-used wormhole routing method. In this paper, an Integer Linear Programming (ILP) approach for deadlock-free routing is proposed, applicable to arbitrary network topologies. We systematically analyze deadlock-free routing construction for mesh and torus topologies under uniform random traffic and provide alternative solutions to turn models. In the context of application-specific NoCs, application mapping, and deadlock-free routing are integrated within a single ILP. Through evaluation with several benchmark applications, it is demonstrated that the ILP method consistently delivers optimal solutions and could obtain better results than various heuristic methods within an acceptable time. Fault tolerance is also explored and existing techniques are incorporated into the ILP approach. As an illustrative example, application mapping and a 1-link-fault-tolerant deadlock-free routing for the MP3 application on a mesh network is performed.

关键词： Network-on-chip integer linear programming deadlock-free routing construction application mapping fault tolerance

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Performance tuning of tile matrix decomposition 13

Performance tuning of tile matrix decomposition

引用

ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Suzuki, Tomohiro Univ Yamanashi Dept Interdisciplinary Res Div Engn 4-3-11 Takeda Kofu Yamanashi 4008511 Japan

ISBN: (纸本)9781728148823

Task parallel algorithms have attracted attention as algorithms for highly parallel architectures in recent years. The aim of such algorithms is to keep all computing resources running without stalling by executing a large number of finegrained tasks asynchronously while observing data dependencies. The tile algorithm of matrix decomposition of dense matrices is implemented using a task parallel programming model following such an approach. In this article, we will consider how to select tile size, which is an important performance parameter.

关键词： matrix decomposition tile algorithm multi-core/many-core architecture

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Power Management Controller for Online Power Saving in Network-on-chips 10

Power Management Controller for Online Power Saving in Netwo...

引用

10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Friederich, Stephanie Neber, Marco Becker, Juergen Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9781509035311

Growing chip integration density and increasing frequencies lead to tremendous leakage power and henceforth to chip heat problems. Power management is one possibility to reduce the power consumption and get the temperature problem under control. Current technology mainly focuses on powergating techniques on basis of multi-core systems but leaving the network perspective out of scope. We provide a holistic concept, bringing together power-gating and frequency scaling techniques for network-on-chips. Following this, network static power consumption could be minimized without affecting the system performance. We present a light-weight power management controller for network-on-chips with online monitoring to optimize the power consumption of network resources. Our work comprises a hardware simulation model for design space exploration of varying technology specific parameters and an FPGS based prototype for verification. The power saving potential heavily depend on the network communication load. Our power controller adds only 2.1% of resources while 28.11% of the total power could be saved with clock gating.

关键词： embedded multicore/many-core systems-on-chip Network-on-chip Low-power design

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Multikernel Design and Implementation for Improving Responsiveness of Aperiodic Tasks 12

Multikernel Design and Implementation for Improving Responsi...

引用

ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Yabuuchi, Hidehito Awamoto, Shinichi Chishiro, Hiroyuki Kato, Shinpei Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan

ISBN: (纸本)9781538666890

Modern real-time systems need to efficiently handle aperiodic tasks as well as periodic ones. This paper presents a system design applying the hybrid operating system approach to multi-core architectures. A core is allocated exclusively and dynamically to a newly booted kernel and an aperiodic task on it so that the task can avoid overhead caused by the rest of the system, leading to reduced response time. We implemented and evaluated the presented design on a real multi-core architecture. The evaluation results indicate that the design improves responsiveness of aperiodic tasks that access shared resources frequently.

关键词： Task analysis Kernel multicore processing Real-time systems Linux Time factors

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Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-core Processor 12

Evaluation of Performance and Fault Containment in AUTOSAR M...

引用

ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Urbina, Moises Obermaisser, Roman Univ Siegen Inst Embedded Syst Siegen Germany

ISBN: (纸本)9781538666890

The AUTOSAR standard does not provide an approach for the mapping of its ECU software architecture to a message-based multicore system. In this work we present an analysis of performance and fault containment of a novel TIme-triggered MEssage-based multi-core architecture for AUTOSAR (TIMEA). The TIMEA platform is intended to bring the advantages of network-on-a-chip architectures to the AUTOSAR software, which lead to multiple benefits for fail operational real time systems such as temporal predictability and fault isolation. We introduce a fault hypothesis consisting of multiple fault assumptions and the definition of the fault containment regions and we describe the algorithms for the integration of a multicore monitoring service into the AUTOSAR Basic Software. A set of experiments were carried out to evaluate the performance of the system using an anti-lock braking use case in a simulation scenario under failure occurrences. The obtained results demonstrate how the TIMEA platform remains operational in the presence of failures.

关键词： multicore processing Monitoring Timing Computer crashes Operating systems

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Combining Decision Tree and Convolutional Neural Network for Energy Efficient On-Device Activity Recognition 16

Combining Decision Tree and Convolutional Neural Network for...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Brehler, Marius Camphausen, Lucas Fraunhofer IML AI & Autonomous Syst Dortmund Germany

ISBN: (纸本)9798350393613

Activity recognition and the sub-problem of motion classification can be performed by using the data provided by inertial measurements units. For many applications it is of high interest to process the data in an energy efficient manner. This can be realized by processing the data close to the sensor on a low-cost, low power embedded device. In this paper, we explore a hybrid, hierarchical architecture that combines a decision tree (DT) with a convolutional neural network (CNN). Different DTs are executed in the sensor whereas the CNN is executed on a central processing unit close to the sensor. We show to which extent the hybrid models allow to reduce the amount of required energy and how the accuracy is affected.

关键词： Machine Learning Activity Recognition Energy Efficiency embedded systems

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An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-chips 11

An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Dai, Jindun Jiang, Xin Li, Renjie Watanabe, Takahiro Waseda Univ Grad Sch Informat Prod & Syst Tokyo Japan Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai Peoples R China

ISBN: (纸本)9781538634417

Network-on-chips (NoC) has been proven as a flexible solution for chip-Multiprocessor (CMP) systems due to its reusability and scalability. To increase communication efficiency, Three-Dimensional Networks-on-chips (3D NoCs) are developed, which can shorten the wire length and improve the system performance. In this paper, we present a novel deadlock-free adaptive routing algorithm for 3D mesh NoC interconnections. The routing rules of traditional XY routing and YX routing are relaxed and used for intra-layer routing. Via multiple layers, balanced adaptiveness can be achieved. We detail the basic principle of this method and test its efficiency through simulations.

关键词： Routing Three-dimensional displays system recovery Two dimensional displays Adaptation models Load modeling system performance three-dimensional displays system performance system recovery Network routing Load modeling network-on-chip Routing algorithms Adaptation models Wire length

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Prototype of FPGA Dynamic Reconfiguration based-on Context-Oriented Programming 13

Prototype of FPGA Dynamic Reconfiguration based-on Context-O...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ohkawa, Takeshi Tanigawa, Ikuta Sato, Mikiko Hisazumi, Kenji Ogura, Nobuhiko Watanabe, Harumi Tokai Univ Dept Embedded Technol Tokyo Japan Kyushu Univ Dept Adv Informat Tech Fukuoka Japan Tokyo City Univ Dept Informat Syst Tokyo Japan

ISBN: (纸本)9781728148823

Acceleration by FPGA is expected for real-time edge processing as well as server applications in the cloud. A robot is one of the examples which need the acceleration of processing such as image recognition processing and actuation based on its visual feedback. As the system is more complex, it is required to introduce a management mechanism of FPGA dynamic reconfiguration. In this paper, we propose a method of system development which includes FPGA acceleration. The key idea of the proposed method is the FPGA reconfiguration based on a context, which is defined in Context-Oriented Programming (COP). This idea contributes to solve the cross-cutting concern problem at runtime. The problem causes to decrease the efficiency of development. Thus, this idea makes easily manage to FPGA reconfiguration with software in case of changing a whole system. In evaluation, we compare the reconfiguration time of FPGA to switch a context with the context switching time of the COP software written in C++ language. It indicates that the proposed method is feasible to handle FPGA context.

关键词： Dynamic Reconfiguration FPGA Context-Oriented Programming

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An open-source and GUI-capable RISC-V computer system on a low-end FPGA board 16

An open-source and GUI-capable RISC-V computer system on a l...

引用

16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Kise, Kenji Tokyo Inst Technol Sch Comp Tokyo Japan

ISBN: (纸本)9798350393613

RISC-V is an open and elegant instruction set architecture designed on the lessons learned from history. Since RISC-V requires no license fee and can be available freely, it has been used in broad areas of research, development, and industry. many processor cores and systems on a chip based on RISC-V have been released, and some are Linux-capable. On the other hand, few stand-alone RISC-V systems on a low-end FPGA can run Linux with various I/Os, such as a network and a display port. If we can design such a system running on a low-cost FPGA board, it will enhance the development of software and hardware related to RISC-V and thus be valuable for numerous purposes. This paper proposes RV-PC, an open-source and GUI-enabled RISC-V computer running as a stand-alone system using a low-end FPGA board. RV-PC supports a wide range of I/Os, such as Ethernet, SD card, VGA display, mouse, and keyboard. It is the unique system that runs GUI and network applications on a system using a RISC-V soft processor on a low-cost FPGA board, such as Nexys A7. The evaluation results show that RV-PC achieves a 1.31 times faster coremark score than the related work.

关键词： RISC-V FPGA GUI-capable Linux

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