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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Fault Detection and Localization for Network-on-chips in Mixed-Criticality systems 13

Fault Detection and Localization for Network-on-Chips in Mix...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Maleki, Adele Ahmadian, Hamidreza Obermaisser, Roman Univ Siegen Chair Embedded Syst Siegen Germany

ISBN: (纸本)9781728148823

The increasing trend towards mixed-critical systems, in which applications with different levels of criticality coexist and interact on the same platform, calls for fault-tolerant hardware platforms. On the other hand, due to the demanded performance in such systems, network-on-chips are employed to interconnect several computation resources. Consequently, the detection and localization of faults in the communication and computation resources becomes a challenge, if a high number of shared resources (e.g., routers, physical links) are used. This paper proposes a new hardware architecture for run-time fault detection and localization in mixed-criticality networks-on-chips. The proposed architecture detects the transient and permanent faults in the network and distinguishes between faults of different resources. The fault detection and localization mechanisms have been evaluated using Gem5 simulation and example scenarios.

关键词： Fault detection Routing Monitoring Schedules Computer architecture Safety Nickel

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Energy and Performance Analysis of STTRAM Caches for Mobile Applications 13

Energy and Performance Analysis of STTRAM Caches for Mobile ...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Kuan, Kyle Adegbija, Tosiron Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781728148823

Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency. Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications. We analyze the characteristics of mobile applications' cache blocks and how those characteristics dictate the appropriate retention time for mobile device caches. We show that due to their inherently interactive nature, mobile applications' execution characteristics-and hence, STTRAM cache design requirements-differ from other kinds of applications. We also explore various STTRAM cache designs in both single and multicore systems, and at different cache levels, that can efficiently satisfy mobile applications' execution requirements, in order to maximize energy savings without introducing substantial latency overhead.

关键词： Spin-Transfer Torque RAM (STTRAM) cache mobile applications performance analysis retention time non-volatile memory energy efficient multicore processor

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A machine learning enabled long-term performance evaluation framework for NoCs 13

A machine learning enabled long-term performance evaluation ...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hou, Jie Han, Qi Radetzki, Martin Univ Stuttgart Chair Embedded Syst Stuttgart Germany Univ Stuttgart Inst Visualizat & Interact Syst Stuttgart Germany

ISBN: (纸本)9781728148823

The rapidly increasing transistor density enables the evolution of many-core on-chip systems. Networks-on-chips (NoCs) are the preferred communication infrastructure for such systems. Technology scaling increases the susceptibility to failures in the NoC's components. However, such a NoC can still operate at the cost of performance degradation. Therefore, it is not sufficient to analyze the performance and reliability of a NoC separately. In this paper, we propose a machine learning enabled performability evaluation framework to treat both aspects together. It applies Markov reward models. In addition, it leverages machine learning techniques to obtain different performance metrics under consideration of faulty routers and various simulation parameters quickly, which is a challenging task in an analytical manner. Moreover, we use a mesh-based NoC to demonstrate our methodology. Long-term performances of mesh 8x8 under XY and fault-tolerant negative-first routing algorithms are evaluated.

关键词： Long-term performance machine learning supervised learning fault-tolerant routing Markov models Markov reward models NoCs Mesh

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Direct solution of larger coupled sparse/dense linear systems using low-rank compression on single-node multi-core machines in an industrial context

Direct solution of larger coupled sparse/dense linear system...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： Emmanuel Agullo Marek Felš ö ci Guillaume Sylvand HiePACS team Inria Bordeaux Sud-Ouest Bordeaux France HiePACS team Airbus Central R&#x0026 T Issy-les-Moulineaux France

While hierarchically low-rank compression methods are now commonly available in both dense and sparse direct solvers, their usage for the direct solution of coupled sparse/dense linear systems has been little investigated. The solution of such systems is though central for the simulation of many important physics problems such as the simulation of the propagation of acoustic waves around aircrafts. Indeed, the heterogeneity of the jet flow created by reactors often requires a Finite Element Method (FEM) discretization, leading to a sparse linear system, while it may be reasonable to assume as homogeneous the rest of the space and hence model it with a Boundary Element Method (BEM) discretization, leading to a dense system. In an industrial context, these simulations are often operated on modern multicore workstations with fully-featured linear solvers. Exploiting their low-rank compression techniques is thus very appealing for solving larger coupled sparse/dense systems (hence ensuring a finer solution) on a given multicore workstation, and - of course - possibly do it fast. The standard method performing an efficient coupling of sparse and dense direct solvers is to rely on the Schur complement functionality of the sparse direct solver. However, to the best of our knowledge, modern fully-featured sparse direct solvers offering this functionality return the Schur complement as a non compressed matrix. In this paper, we study the opportunity to process larger systems in spite of this constraint. For that we propose two classes of algorithms, namely multi-solve and multi-factorization, consisting in composing existing parallel sparse and dense methods on well chosen submatrices. An experimental study conducted on a 24 cores machine equipped with 128 GiB of RAM shows that these algorithms, implemented on top of state-of-the-art sparse and dense direct solvers, together with proper low-rank assembly schemes, can respectively process systems of 9 million and 2.5 million

关键词： Couplings Linear systems multicore processing Atmospheric modeling Random access memory Workstations Finite element analysis

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Integrating Intra- and Intercellular Simulation of a 2D HL-1 Cardiac Model based on embedded GPUs 13

Integrating Intra- and Intercellular Simulation of a 2D HL-1...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Liu, Baohua Shen, Wenfeng Zhu, Xin Wangchen, Xingyu Shanghai Univ Sch Comp Engn & Sci Shanghai Inst Adv Commun & Data Sci Shanghai Peoples R China Univ Aizu Biomed Informat Technol Lab Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9781728148823

Simulation of electrophysiological cardiac models enables researchers to investigate the activity of heart under various circumstances. Fortunately, recent development in embedded parallel computing architectures has made it possible for one to efficiently simulate sophisticated electrophysiological models that match up to real conditions on embedded computing devices, which typically relies on large scale CPU or GPU clusters in the past. In this paper, a simultaneous implementation of a 2D Takeuchi-HL-1 cardiac model combining unicellular and intercellular solver is proposed and conducted on NVIDIA Jetson Tegra X2 embedded computer. The experiment results demonstrate that our implementation yields considerable efficiency improvement compared with that using non-simultaneous methods, without loss of simulation accuracy. Moreover, it's also proved that embedded devices are much more energy-efficient than conventional systems on the simulation.

关键词： Takeuchi-HL-1 Electrophysiology Parallelization Scheduling

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Lightweight Semantics-Preserving Communication for Real-Time Automotive Software 13

Lightweight Semantics-Preserving Communication for Real-Time...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Yip, Eugene Lalo, Erjola Luettgen, Gerald Sailer, Andreas Univ Bamberg Software Technol Res Grp D-96045 Bamberg Germany Vector Informatik GmbH D-93053 Regensburg Germany

ISBN: (纸本)9781728148823

The automotive industry is confronting the multi-core challenge, where legacy and modern software must run correctly and efficiently in parallel, by designing their software around the Logical Execution Time (LET) model. While such designs offer implementations that are platform independent and time predictable, task communications are assumed to complete instantaneously. Thus, it is critical to implement timely data transfers between LET tasks, which may be on different cores, in order to preserve a design's data-flow. In this paper, we develop a lightweight Static Buffering Protocol (SBP) that satisfies the LET communication semantics and supports signal-based communication with multiple signal writers. Our simulation-based evaluation with realistic industrial automotive benchmarks shows that the execution overhead of SBP is at most half that of the traditional Point-To-Point (PTP) communication method. Moreover, SBP needs on average 60% less buffer memory than PTP.

关键词： buffering protocol logical execution time multi-core

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Development of Soft-core Processor with Efficient Array Data Transfer Mechanism 8

Development of Soft-Core Processor with Efficient Array Data...

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8th international symposium on Computing and Networking Workshops, CANDARW 2020

作者： Kikuchi, Tomoya Kimura, Yoshiki Ootsu, Kanemitsu Yokota, Takashi Jvckenwood Corporation Japan Utsunomiya University Graduate School of Regional Development and Creativity Utsunomiya Japan

ISBN: (纸本)9781728199191

Recently, the use of FPGA in the fields of embedded systems has been increasing. However, there is a problem that it is difficult to develop dedicated circuit on FPGA in a short time in many cases. One method for solving this problem is to reduce the development cost of the dedicated circuit by migrating some part of the target task, whose performance is not critical in the system, onto soft-core processor. If the performance of the soft-core processor is improved, more part of the target task can be migrated onto it, the amount of the dedicated circuit to be developed can be further reduced, and thus the development cost can be ***, when trying to raise the performance of soft-core processor, the improvement of the memory access performance is a critical issue, since the performance of memory system including off-chip memory is generally not high in embedded system. Therefore, in this paper, we aim to improve the performance of off-chip SDRAM memory access, and discuss the method of efficient data transfer that utilizes the SDRAM bandwidth as efficiently as possible. And we implement the mechanism to realize the efficient data transfer. We also develop a soft-core processor equipped with vector loading function as research prototype platform, and preliminarily evaluate the performance. © 2020 ieee.

关键词： Data transfer

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multicore Power Estimation using Independent Component Analysis based Modeling 13

Multicore Power Estimation using Independent Component Analy...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Sagi, Mark Nguyen Anh Vu Doan Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Chair Integrated Syst Munich Germany

ISBN: (纸本)9781728148823

State-of-the-art power estimation research for multi-core processors combine performance counters that collect runtime activity information with an offline-generated power model. To generate these power models, the package power is measured and the activity information is traced while synthetic workloads are executed. These workloads stress distinct core components in order to expose power responses so that the activity information has low collinearity. The measurements are then combined into a power model describing the general power behavior. However, one of the main drawbacks of these synthetic workloads is that they are most of the time custom-designed for a given multi-core architecture and are hardly available. In this paper, we present a methodology to generate power models using freely available benchmarks, e.g. PARSEC/Splash-2. To minimize the collinearity of the activity information due to the uncontrolled/unspecified behavior of these more general benchmarks, we propose to use independent component analysis. This allows to avoid the use of synthetic workloads and a reduction of the relative error by 24% in the average case, when compared to prior state-of-the-art work. Although, we also observe an increase of 22% relative error in the worst case for our approach, this can easily be improved by using either different or more training benchmarks. These promising results give a strong indication that independent component analysis could directly be used with real application workload, leading to the possibility to build/improve power models during runtime.

关键词： multicore power estimation performance counters independent component analysis accuracy

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MITRACA: a next-gen heterogeneous architecture 13

MITRACA: a next-gen heterogeneous architecture

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ben Abdelhamid, Riadh Yamaguchi, Yoshiki Boku, Taisuke Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki Japan Univ Tsukuba Fac Engn Informat & Syst Tsukuba Ibaraki Japan Univ Tsukuba Ctr Comp Sci Tsukuba Ibaraki Japan

ISBN: (纸本)9781728148823

GPU (Graphics Processing Unit) and CPU (Central Processing Unit) possess a sufficient and appropriate performance to compute massively parallel applications like AI, Big data, and material sciences. However, their real performance is far lower than those theoretical ones. The primary reason for the performance degradation is that they suffer from limited memory bandwidth and inefficient interconnection topology not optimized for these types of applications. Thus, from the viewpoint of real computational performance called computational efficiency, FPGA (Field Programmable Gate Array) is now becoming an attractive chip for these types of applications with massively parallel computation. FPGA can efficiently propose optimized communication and bridge different computing accelerators as customized hardware. In other words, FPGA-based hardware accelerators offer a convenient solution for both high performance and high memory bandwidth. However, one serious concern is usability. For example, the FPGA design using hardware description language is a meticulous task and requires specialized skill sets as well as a long time to market. An overlay architecture will become an appropriate candidate that can resolve this issue because it offers a software layer that simplifies FPGA programmability by abstracting the fabric resources. Thus, this article proposes an overlay architecture based on a tightly-connected many-core-based CGRA (Coarse-Grained Reconfigurable Architecture). It will help software engineers on seamlessly implementing their applications. Our final goal is not on the current fine-grained FPGAs but new middle-to-course-grained programmable chips. If an ASIC (Application-Specific Integrated Circuit) implementation was adopted, the performance would achieve at least ten times higher compared with the current FPGA implementation because of the working frequency. In this article, the proposed overlay system provides a programmable interface that virtualizes FPGA res

关键词： FPGA many-core overlay VLIW SIMD CGRA 3D Torus double-precision floating-point

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A STDM (Static Time Division Multiplexing) switch on a multi-FPGA system 13

A STDM (Static Time Division Multiplexing) switch on a multi...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Azegami, Keita Musha, Kazusa Hironaka, Kazuei Ben Ahmed, Akram Koibuch, Michihiro Hu, Yao Amano, Hideharu Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo Japan

ISBN: (纸本)9781728148823

FPGAs can be a promising accelerator used for MEC (Multi-access Edge Computing) which provides timing critical services for a number of terminals at the base stations near from edges. Although a high-end FPGA can support a fixed latency computation with a relatively small power consumption, they are expensive and the available acceleration circuits are limited into a size of single FPGA. FiC (Flow-in-Cloud) has been developed for building a virtual large FPGA from a number of middle-range economical FPGAs connected with high speed serial links. Although the current target of FiC is cloud computing, it is more suitable for the future MEC, because huge hardware resource can be supported with small cost. One of the problem to use such multi-FPGA systems for timing critical computation is network uncertainty. With a common packet switching, the computation speed is influenced with the network traffic. That is, the fixed latency computation which could be supported by a single FPGA is hard to be supported with multi-FPGA systems using common packet switching networks. In order to address this problem, we introduced STDM (Static Time Division Multiplexing) switch in the FiC system. Since the STDM always supports a constant communication latency, transfer time can be estimated beforehand. Through the implementation of the STDM switch on the FPGA board for FiC, it appeared that the utilization ratio of the LUTs for the STDM switch is smaller than 14%. The required number of slots is less than 16 even for a system with 256 nodes. We implemented the Conjugate Gradient method, which includes all-to-all communication, on 4x2 FiC system. It achieved 17.9 times performance improvement of Intel E5-2667 2.90GHz CPU with 6 cores.

关键词： STDM Multi-FPGA system FPGA-in-Cloud

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