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Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-criteria Recommender system 12

Adaptive Genetic Algorithm for Improving Prediction Accuracy...

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hamada, Mohamed Abdulsalam, Latifat Ometere Hassan, Mohammed Univ Aizu Software Engn Lab Aizu Wakamatsu Fukushima Japan African Univ Sci & Technol Dept Comp Sci & Engn Abuja Nigeria Bayero Univ Kano Dept Software Engn Kano Nigeria

ISBN: (纸本)9781538666890

Recommender systems are software tools used to make valuable recommendations to users. Traditionally, recommender systems use information obtained from ratings of an item by users with similar opinions to make recommendations. A user uses a single rating to represent the degree of likeness of an item in traditional recommender systems. Though this approach has reasonably shown a good prediction accuracy, however, the performance of traditional recommender systems is considered inadequate, as users could have different opinions based on some specific features of an item. Multi-criteria recommendation extends the traditional techniques by incorporating ratings for various attributes of the items. It provides better recommendations for users as the system allows the opportunity for users to specify their preferences based on different attributes of user item, which improves prediction accuracy. In this paper, we proposed an aggregation function based method that uses an adaptive genetic algorithm to efficiently incorporate the criteria ratings for improving the accuracy of the multi-criteria recommender system. We carried out an experiment using a dataset for multi-criteria recommendations of movies to users. The experimental result shows that our proposed approach provides better accuracy than the corresponding traditional technique.

关键词： Recommender system Adaptive genetic algorithm Multi-criteria recommender system Asymmetric singular value decomposition Prediction accuracy

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A Fuzzy-based Approach for Modelling Preferences of Users in Multi-criteria Recommender systems 12

A Fuzzy-based Approach for Modelling Preferences of Users in...

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hamada, Mohamed Nkiruka, Odu B. Hassan, Mohammed Univ Aizu Software Engn Lab Aizu Wakamatsu Fukushima Japan African Univ Sci & Technol Abuja Nigeria Bayero Univ Dept Software Engn Kano Nigeria

ISBN: (纸本)9781538666890

Recommender systems (RSs) are web-based tools that use various machine learning and filtering methods to propose useful items for users. Several techniques have been used to develop such a system for generating a list of useful recommendations. Traditionally, RSs use a single rating to represent preferences of a user on an item. A multi-criteria recommendation is a new technique that recommends items to users based on multiple attributes of the items. This technique has been used to solve many recommendation problems. Its predictive performance has been tested and proved to be more efficient than the traditional approach. However, this paper presents a model that is based on the architecture and main features of fuzzy sets and systems. Fuzzy logic (FL) is widely known for its application in different fields of study with its main advantage being that it does not need a lot of training data and its ability to combine human heuristics into the computer-assisted decision making process. FL is highly applicable in the domain of RS. The proposed study is to test and provide the predictive performance of the fuzzy-based multi-criteria technique and compare it with a single rating RS. Experimental results on real-world datasets from Yahoo! Movies proved that the proposed technique has remarkably improved the accuracy of the system.

关键词： Recommender system Multi-criteria Recommendation Asymmetric Singular Value Decomposition Fuzzy Logic Prediction Accuracy

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On the Complexity of Mapping Feasibility in many-core Architectures 12

On the Complexity of Mapping Feasibility in Many-Core Archit...

引用

ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Schwarzer, Tobias Roloff, Sascha Richthammer, Valentina Khaldi, Rami Wildermann, Stefan Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany Ulm Univ Ulm Germany

ISBN: (纸本)9781538666890

many-core architectures enable the concurrent execution of multiple application programs. In this context, the well-known problem of feasibly mapping applications, i.e., their tasks and communication, to such architectures has gained importance due to the large number of cores and limited inter-processor communication capacities. This challenge is tackled by so-called Hybrid Application Mapping (HAM) approaches: These combine a design-time analysis to extract sets of mapping constraints that characterize feasible, respectively optimal mappings with the runtime determination of a concrete mapping in dependence of these mapping constraints and the set of currently available resources. A major strength of HAM approaches has been shown as their ability to give real-time and other guarantees for statically characterized application programs even in highly dynamic workload scenarios while avoiding the pessimism of static resource partitionings. However, finding a feasible mapping is an NP-complete problem. This work discusses arising implications for HAM approaches in general and investigates two exact techniques for solving the mapping constraints at runtime in particular: (I) a problem-specific backtracking approach, and (II) an approach that adopts a general-purpose SAT solver. Experimental results show that the overhead of the general-purpose solver and, in particular, processing and solving the required SAT formulation becomes significant, whereas the problem-specific backtracking technique achieves significantly lower execution times.

关键词： Constraint Solving Hybrid Application Mapping many core Architectures

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Tool-based development of efficient automotive multi-core systems

Tool-based development of efficient automotive multi-core sy...

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19th Stuttgart international symposium on Automotive and Engine Technology, 2019

作者： Friederich, Patrick Zeeb, Alexander Vector Informatik GmbH Germany

ISBN: (纸本)9783658259389

Due to increasing demands for computing power by upcoming applications, such as autonomous driving or Car2x, more and more multi-core processors finding their way into electronic control units of the automotive domain. This leads to a paradigm shift from sequential to parallel processing, which creates many challenges in the development of safety-critical embedded multi-core systems. The appropriate deployment of software components on the available cores of the processor is crucial for a good system behavior, especially regarding response times. This paper proposes a tool-based visualization, analysis and validation of the configured AUTOSAR system, that assists in deployment evaluation and optimization. The fundamental prerequisite that enables deployment of software components on multi-core processors is the efficient provision of basic software services to application software on all processor cores. It is described, that this requirement can be met in particular by the master-satellite architecture. The emerging complexity which results from the vast design space of embedded multicore systems shows, that efficient systems can only be developed by integrating specific tools into a toolchain and using suitable software platforms. © Springer Fachmedien Wiesbaden GmbH, ein Teil von Springer Nature 2019.

关键词： Program processors

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Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor 12

Search Space Reduction for Parameter Tuning of a Tsunami Sim...

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Komatsu, Kazuhiko Kishitani, Takumi Sato, Masayuki Musa, Akihiro Kobayashi, Hiroaki Tohoku Univ Cybersci Ctr Sendai Miyagi Japan Tohoku Univ Grad Sch Informat Sci Sendai Miyagi Japan NEC Corp Ltd Tokyo Japan

ISBN: (纸本)9781538666890

The structures of recent computing systems have become complicated such as heterogeneous memory systems with a deep hierarchy and many core systems. To achieve high performance of HPC applications on such computing systems, performance tuning is mandatory. However, the number of tuning parameters has become large due to the complexities of the systems and applications. In addition, along with the improvement of computing systems, HPC applications are getting larger and complicated, resulting in long execution time of each application execution. Due to a large number of tuning parameters and a long time of each execution, a time to search for an appropriate tuning parameter combination becomes huge. This paper proposes a method to reduce the time to search for an appropriate tuning parameter combination. By considering the characteristics of a many-core processor and a simulation code, a search space of tuning parameters is reduced. Moreover, a time of each application execution for parameter search is reduced by limiting a simulation period of an application unless characteristics of the application are changed. Through the evaluation of performance tuning using the tsunami simulation code on the Intel Xeon Phi Knight Landing processor, it is clarified that a 3.67x performance improvement can be achieved by the parameter tuning. It is also clarified that the time for parameter tuning can drastically be saved by reducing the number of tuning parameters to be searched and limiting the simulation period of each application execution.

关键词： Parameter tuning many-core processor Search space reduction Tsunami simulation

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Neksus: An Interconnect for Heterogeneous system-In-Package Architectures

Neksus: An Interconnect for Heterogeneous System-In-Package ...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： Vidushi Goyal Xiaowei Wang Valeria Bertacco Reetuparna Das Department of Computer Science and Engineering University of Michigan Ann Arbor USA

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

In the embedded systems industry today, skyrocketing design and manufacturing costs of systems-on-chip (SoCs) are key limiting factors for growth. Emerging 2.5D-based system-In-Package (SiP) architectures show potential to lower these costs by enabling the reuse of hard core units and providing higher manufacturing yields due to small chiplet *** this paper, we present Neksus, a novel architecture designed to lower SiP manufacturing costs, support modular "plug-and-play" chiplet integration, and leverage the unique properties of interposers. Key to Neksus is a new dedicated interconnect chiplet that addresses the limitations of SiP packaging technology by leveraging direct communication over a mini-chain IP-connection topology. In addition to satisfying SiP technology constraints, because our mini-chain design provides high-bandwidth IP-to-IP communication, it is particularly well-suited for bandwidth-intensive mobile applications. Our evaluation shows Neksus provides up to 28% performance improvement and 31% energy savings over recent SiP architecture.

关键词： IP networks Silicon Bandwidth Substrates Industries Topology Stacking

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LAHEL: Lightweight Attestation Hardening embedded Devices using Macrocells

LAHEL: Lightweight Attestation Hardening Embedded Devices us...

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ieee international Workshop on Hardware-Oriented Security and Trust (HOST)

作者： Orlando Arias Dean Sullivan Haoqi Shan Yier Jin University of Florida

ISBN: (数字)9781728174051

ISBN: (纸本)9781728174068

In recent years, we have seen an advent in software attestation defenses targeting embedded systems which aim to detect tampering with a device's running program. With a persistent threat of an increasingly powerful attacker with physical access to the device, attestation approaches have become more rooted into the device's hardware with some approaches even changing the underlying microarchitecture. These drastic changes to the hardware make the proposed defenses hard to apply to new systems. In this paper, we present and evaluate LAHEL as the means to study the implementation and pitfalls of a hardware-based attestation mechanism. We limit LAHEL to utilize existing technologies without demanding any hardware changes. We implement LAHEL as a hardware IP core which interfaces with the coreSight Debug Architecture available in modern ARM cores. We show how LAHEL can be integrated to system on chip designs allowing for microcontroller vendors to easily add our defense into their products. We present and test our prototype on a Zynq-7000 SoC, evaluating the security of LAHEL against powerful time-of-check-time-of-use (TOCTOU) attacks, while demonstrating improved performance over existing attestation schemes.

关键词： Performance evaluation Macrocell networks Software Security Runtime Hardware Computer architecture

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Scalable and Memory-efficient Spin Locks for embedded Tile-based many-core Architectures 21

Scalable and Memory-efficient Spin Locks for Embedded Tile-b...

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21st ieee international symposium on Real-Time Computing (ISORC)

作者： Awamoto, Shinichi Chishiro, Hiroyuki Kato, Shinpei Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan

ISBN: (纸本)9781538658475

embedded many-core system-on-chip (SoC) architectures require scalability and memory constraints. However, communication between many cores, especially locking mechanisms of operating systems, is often the main obstacle to scalable and memory-efficient processing. Existing scalable spin locks consume non-negligible amounts of memory in many-core architectures, thus they are not suitable for memory constrained systems. This paper focuses on a combination of a global Mellor-Crummey and Scott (MCS) queue lock, and local ticket (TKT) locks. We refer to this lock as the C-MCS-TKT lock, which has much better memory efficiency than other scalable spin locks without degrading scalability. In addition, this paper also presents a memory-optimized version of the C-MCS-TKT lock, which slightly degrades scalability but reduces memory fragmentation, compared to the original C-MCS-TKT lock. Experimental results show that these locks have comparable performance to those of other highly scalable spin locks.

关键词： Spin Locks Synchronization many-core Architectures embedded systems Scalability Memory Efficiency

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Exploration of Memory and Cluster Modes in Directory-Based many-core CMPs 12

Exploration of Memory and Cluster Modes in Directory-Based M...

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12th ieee/ACM international symposium on Networks-on-chip (NOCS)

作者： Charles, Subodha Patil, Chetan Arvind Ogras, Umit Y. Mishra, Prabhat Univ Florida Gainesville FL 32611 USA Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781538648933

Networks-on-chip have become the standard interconnect solution to address the communication requirements of many-core chip multiprocessors. It is well-known that network performance and power consumption depend critically on the traffic load. The network traffic itself is a function of not only the application, but also the cache coherence protocol, and memory controller/directory locations. Communication between the distributed directory to memory can introduce hotspots, since the number of memory controllers is much smaller than the number of cores. Therefore, it is critical to account for directory-memory communication, and model them accurately in architecture simulators. This paper analyzes the impact of directory-memory traffic and different memory and cluster modes on the NoC traffic and system performance. We demonstrate that unrealistic models in a widely used multiprocessor simulator produce misleading power and performance predictions. Finally, we evaluate different memory and cluster modes supported by Intel Xeon-Phi processors, and validate our models on four different cache coherence protocols.

关键词： Coherence Program processors Protocols Power demand Memory management Load modeling Optimization

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Exploiting Dark cores for Performance Optimization via Patterning for many-core chips in the Dark Silicon Era 12

Exploiting Dark Cores for Performance Optimization via Patte...

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12th ieee/ACM international symposium on Networks-on-chip (NOCS)

作者： Wang, Xiaohang Singh, Amit Kumar Wen, Shengyan South China Univ Technol Guangzhou Peoples R China Univ Essex Colchester Essex England

ISBN: (纸本)9781538648933

All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark silicon era. These free cores (referred to as bubbles) can be placed near active cores for heat dissipation so that the active cores can run at a higher frequency level, boosting the performance of active cores and applications. In the literature, this approach is referred as static patterning. Patterning for performance boost has the following challenges. First, communication distance increases when a bubble is inserted between two communicating tasks, leading to performance degradation. Second, budgeting too many bubbles as cooler to running applications leads to insufficient cores for future applications. In addition, task-migration-based dynamic patterning can further improve the performance of the system. In this paper, a static and a dynamic patterning approaches are proposed to budget free cores to each application so as to optimize the throughput of the whole system. Essentially, the proposed static patterning algorithm determines the number and locations of bubbles to optimize the performance and waiting time of each application, followed by tasks of each application being mapped to a core region. The dynamic patterning algorithm first selects the best pattern, the bubble number and the core region shape for each application that results in maximal performance, followed by choosing the location for each application's core region. Experiments show that our approach achieves 50% higher throughput when compared to state-of-the-art thermal-aware runtime task mapping approaches.

关键词： Task analysis Heuristic algorithms Silicon Time factors Heating systems Resource management Servers

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