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ieee international symposium on Smart Electronic systems (iSES)

作者： Kalyan Baital Amlan Chakrabarti National Institute of Electronics and Information Technology Kolkata Centre Kolkata India A.K. Choudhury School of Information Technology University of Calcutta Kolkata India

ISBN: (数字)9781728146553

ISBN: (纸本)9781728146560

embedded real-time systems are gradually increasing to execute high-performance-oriented applications on multicore architecture. It is very necessary to have efficient task scheduling model in these systems so that majority of the tasks can be scheduled within their deadline to provide the needed throughput. We proposed a dynamic scheduling algorithm where random tasks are accommodated into a system that is already running a set of tasks, meeting the deadline of the tasks. Random tasks are generated at different time intervals with different periodicity and execution time. Energy consumption is one of the critical design issues in real-time systems especially in battery-operated systems. We further implemented an energy efficient real-time scheduling where voltages are adjusted dynamically to achieve optimum energy as well as throughput. We extended the scheduling work to heterogeneous multicore systems (HMS) architecture where real-time tasks are accommodated to the appropriate cores maintaining the task deadline. We demonstrated that the heterogeneous multicore scheduling model can be used as commercially available heterogeneous multicore systems. We verified the model using generated task sets and the results showed that our model performs excellently in all cases and significantly reduces the energy consumption of the system with respect to some popular and new scheduling schemes.

关键词： embedded system Energy Efficiency Heterogeneous multicore Real-Time system Task Scheduling Multi-core processors real-time systems TASK SCHEDULING Energy efficiency embedded systems Heterogeneous Religious Missions energy consumption Throughput

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Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques

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MICROPROCESSORS AND MICROsystemS 2018年 63卷 259-268页

作者： Nouri, Sajjad Rossi, Davide Nurmi, Jari Tampere Univ Technol Lab Elect & Commun Engn Tampere Finland Univ Bologna Dept Elect Elect & Informat Engn Guglielmo Marcon Bologna Italy

This article presents an integrated self-aware computing model in a Heterogeneous multicore Architecture (HMA) to mitigate the power dissipation of an Orthogonal Frequency-Division Multiplexing (OFDM) receiver. The proposed platform consists of template-based Coarse-Grained Reconfigurable Array (CGRA) devices connected through a Network-on-chip (NoC) around a few Reduced Instruction-Set Computing (RISC) cores. The self-aware computing model exploits Feedback Control system (FCS) which constantly monitors the execution-time of each core and dynamically scales the operating frequency of each node of the NoC depending on the worst execution-time. Therefore, the performance of the overall system is equalized towards a desired level besides mitigating the power dissipation. Measurement results obtained from Field-Programmable Gate Array (FPGA) synthesis show up to 20.2% dynamic power dissipation and 16.8% total power dissipation savings. Since FCS technique can be employed for scaling the frequency and the voltage and on the other hand, voltage supply cannot be scaled on the FPGA-based prototyped platform, the implementation is also estimated in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted Silicon-On-Insulator (FD-SOI) Application-Specific Integrated Circuit (ASIC) technology to scale voltage in addition to frequency and get more benefits in terms of dynamic power dissipation reduction. Subsequent to synthesizing the whole platform on ASIC and scaling the voltage and frequency simultaneously as a Dynamic Voltage and Frequency Scaling (DVFS) method, significant dynamic power dissipation savings by 5.97X against Dynamic Frequency Scaling (DFS) method were obtained. (C) 2018 Published by Elsevier B.V.

关键词： Reconfigurable CGRA Network-on-chip Heterogeneous Accelerator multicore FFT Time synchronization Channel estimation Frequency offset estimation Receiver OFDM FCS DVFS Power mitigation FPGA ASIC

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2018 12th ieee/ACM international symposium on Networks-on-chip, NOCS 2018

2018 12th IEEE/ACM International Symposium on Networks-on-Ch...

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12th ieee/ACM international symposium on Networks-on-chip, NOCS 2018

ISBN: (纸本)9781538648933

The proceedings contain 21 papers. The topics discussed include: NoC-based support of heterogeneous cache-coherence models for accelerators;exploration of memory and cluster modes in directory-based many-core CMPs;accurate congestion control for RDMA transfers;testing WiNoC-enabled multicore chips with BIST for wireless interconnects;towards energy-efficient high-throughput photonic NoCs for 2.5D integrated systems: a case for AWGRs;AxNoC: low-power approximate network-on-chips using critical-path isolation;DAPPER: data aware approximate NoC for GPGPU architectures;and Brownian bubble router: enabling deadlock freedom via guaranteed forward progress.

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Communication-Avoiding Tile QR Decomposition on CPU/GPU Heterogeneous Cluster system

Communication-Avoiding Tile QR Decomposition on CPU/GPU Hete...

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ieee international symposium on embedded multicore/many-core system-on-chip

作者： Masatoshi Takayanagi Tomohiro Suzuki University of Yamanashi

ISBN: (纸本)9781538666906

The tile algorithm for matrix decompositions is attracting attention as a method for the latest multicore/many-core architecture because it can generate many fine-grained tasks which can be executed in parallel. Exploiting many parallel computing resources effectively with a fork-join paradigm is difficult. CPU/GPU heterogeneous cluster system is mainstream for a supercomputer system in recent years. Using the CPU/GPU cluster system efficiently is more difficult than efficiently utilizing the multicore cluster system. We implemented the tile CAQR decomposition algorithm on the CPU/GPU cluster system with OpenMP 4.0, MPI and cuBLAS, and proposed new approaches to utilize GPUs efficiently. In this paper, we show the performance result of our implementation on the Reedbush-H heterogeneous supercomputer.

关键词： Tile supercomputer matrix decomposition quick release core construction decomposition Mainstreaming (Education)

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Micro-Viruses for Fast system-Level Voltage Margins Characterization in multicore CPUs

Micro-Viruses for Fast System-Level Voltage Margins Characte...

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ieee international symposium on Performance Analysis of systems and Software (ISPASS)

作者： Papadimitriou, George Chatzidimitriou, Athanasios Kaliorakis, Manolis Vastakis, Yannos Gizopoulos, Dimitris Univ Athens Athens Greece

ISBN: (纸本)9781538650103

In this paper, we propose the employment of fast targeted programs (diagnostic micro-viruses) that aim to stress individually the main hardware components of a multicore CPU architecture which most likely determine the limits of voltage scaling, i.e. safe V-min values. We describe in detail the complex development process for the diagnostic micro-viruses and their comprehensive validation in modern multicore CPU hardware. The combined execution of the micro-viruses takes very short time compared to regular programs execution, and can quickly reveal the voltage limits of the cores and chips at voltage levels below nominaL The micro-virus based characterization flow requires orders of magnitude shorter time while it delivers virtually identical: (a) V-min values for the different CPU chips, and (b) V-min values for the different cores within a CPU chip. We evaluate our micro-viruses based characterization flow (and compare it to the SPEC-based flow) on three different chips (a nominal graded and two corner parts) of Applied Micro's X-Gene 2 micro-server family (with 8-core ARMv8-based CPUs manufactured in 28nm). We report detailed validation and evaluation results that prove the effectiveness of the micro-viruses for the fast and accurate identification of the voltage margins variability among the chips and the cores of a multicore CPU.

关键词： multicore processing Benchmark testing Microprocessors Stress Hardware Viruses (medical) Pipelines

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Hybrid-Comp: A Criticality-Aware Compressed Last-Level Cache 19

Hybrid-Comp: A Criticality-Aware Compressed Last-Level Cache

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19th international symposium on Quality Electronic Design (ISQED)

作者： Jadidi, Amin Arjomand, Mohammad Kandemir, Mahmut T. Das, Chita R. Penn State Univ Sch Elect Engn & Comp Sci University Pk PA 16802 USA Georgia Inst Technol Sch Comp & Elect Engn Atlanta GA 30332 USA

ISBN: (纸本)9781538612149

Cache compression is a promising technique to increase on-chip cache capacity and to decrease off-chip bandwidth usage. While prior compression techniques always consider a trade-off between compression ratio and decompression latency, they are oblivious to the variation in criticality of different cache blocks. In multi-core processors, last-level cache (LLC) is logically shared but physically distributed among cores. In this work, we demonstrate that, cache blocks within such non-uniform architecture exhibit different sensitivity to the access latency. Owing to this behavior, we propose a criticality-aware compressed LLC that favors lower latency over higher capacity based on the criticality of the data blocks. Based on our studies on a 16-core processor with 4MB LLC, our proposed criticality-aware mechanism improves the system performance comparable to that of with an 8MB uncompressed LLC.

关键词： Sensitivity multicore processing system-on-chip system performance Data compression Delays Electrical engineering

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Multikernel Design and Implementation for Improving Responsiveness of Aperiodic Tasks

Multikernel Design and Implementation for Improving Responsi...

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ieee international symposium on embedded multicore/many-core system-on-chip

作者： Hidehito Yabuuchi Shinichi Awamoto Hiroyuki Chishiro Shinpei Kato Graduate School of Information Science and Technology The University of Tokyo

ISBN: (纸本)9781538666906

Modern real-time systems need to efficiently handle aperiodic tasks as well as periodic ones. This paper presents a system design applying the hybrid operating system approach to multi-core architectures. A core is allocated exclusively and dynamically to a newly booted kernel and an aperiodic task on it so that the task can avoid overhead caused by the rest of the system, leading to reduced response time. We implemented and evaluated the presented design on a real multi-core architecture. The evaluation results indicate that the design improves responsiveness of aperiodic tasks that access shared resources frequently.

关键词： Responsiveness Reaction Time Religious Missions BOOTS ARCHITECTURE core construction real-time systems Operating systems

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Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker

Performance Comparison of Time-Step-Driven versus Event-Driv...

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ieee international symposium on Circuits and systems (ISCAS)

作者： Yousefzadeh, Amirreza Soto, Mikel Serrano-Gotarredona, Teresa Galluppi, Francesco Plana, Luis Furber, Steve Linares-Barranco, Bernabe CSIC Inst Microelect Sevilla Seville Spain Univ Seville Seville Spain Univ Manchester Dept Comp Sci Manchester Lancs England

ISBN: (纸本)9781538648810

The SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large number of neurons in real-time. SpiNNaker is using a general purpose ARM processor that gives a high amount of flexibility to implement different methods for processing spikes. Various libraries and packages are provided to translate a high-level description of Spiking Neural Networks (SNN) to low-level machine language that can be used in the ARM processors. In this paper, we introduce and compare three different methods to implement this intermediate layer of abstraction. We have examined the advantages of each method by various criteria, which can be useful for professional users to choose between them. All the codes that are used in this paper are available for academic propose.

关键词： Neurons Biological neural networks Real-time systems Libraries Neuromorphics multicore processing

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Performance Analysis of a multicore based LEON3 integrating a RTOS 15

Performance Analysis of a Multicore based LEON3 integrating ...

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15th international Multi-Conference on systems, Signals and Devices (SSD)

作者： Kchaou, Afef El Hadj Youssef, Wajih Tourki, Rached Univ Tunis El Manar Lab Elect & Microelect Monastir Fac Sci Tunis Monastir Tunisia Univ Monastir Lab Elect & Microelect Monastir Monastir Tunisia

ISBN: (纸本)9781538653050

embedded system is characterized by three principal categories: real-time performance, low coast (low hardware occupation) and a low power/energy consumption. Measuring the performance of an embedded system versus the cost for designs has become a very important interest for any embedded system design process. In goal to improve the speed of a system, the integration of many processors in the same chip can be a solution but it requires saving power in electronic systems. In this paper a new method is used to evaluate a hardware performance of FPGA based on different embedded systems and running freely available benchmarks. A hardware implementation and real-time performance measurements of an embedded system (mono-processor, bi-processor and quad-processor based LEON3 soft-core) is done with the integration of a Real Time Operating system open-source, like eCos.

关键词： LEON3 RTOS eCos SMP Performance Dhrystone FFT

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Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for many-core systems

Globally Wireless Locally Wired (GloWiLoW): A Clock Distribu...

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ieee international symposium on Circuits and systems (ISCAS)

作者： Ding, Qian Fletcher, Benjamin J. Mak, Terrence Univ Southampton Elect & Comp Sci Southampton Hants England

ISBN: (纸本)9781538648810

Modern high-performance systems are now facing critical issues on delivering power-efficient and globally interconnected clock networks. Conventional metal-based interconnect has gradually reached its bottleneck with the technology scaling which limits system performance as the interconnect delay has already overweighed circuit gate delay. A typical clock distribution network (CDN) might consume up to 50% of the total chip power and could generate large phase delay and clock uncertainties due to its RC characteristic and unbalanced load. This paper proposes a novel hybrid wire-wireless CDN, which improves the performance of on-chip clock distribution significantly using embedded wireless clock transmitter and receiver fabrics. In particular, On-Off-Keying (OOK) transceivers are implemented for overall system simplicity and has achieved significant power-efficiency. Results indicate that the total propagation delay can be reduced to 39.4ps, which is 57 times lower than the conventional H-tree. Besides, the system clock skew can be predictable and limited only by the displacement of clock receivers. Less than 26.9ps of clock skew (6.7% of a clock period at 2.5GHz) could be found within the proposed CDN and hence, shows the promising potential of future high-performance on-chip clock distribution.

关键词： Clocks Delays Integrated circuit interconnections Wireless communication Receivers Propagation delay Dipole antennas

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