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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Proceedings - ieee 10th international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2016

Proceedings - IEEE 10th International Symposium on Embedded ...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2016

ISBN: (纸本)9781509035304

The proceedings contain 49 papers. The topics discussed include: acceleration of full-PIC simulation on a CPU-FPGA tightly coupled environment;data and commands communication protocol for neuromorphic platform configuration;heuristic based routing algorithm for network on chip;2-step power scheduling with adaptive control interval for network intrusion detection systems on multicores;a data locality and memory contention analysis method in embedded NUMA multi-core systems;time-triggered and rate-constrained on-chip communication in mixed-criticality systems;a Benes based NoC switching architecture for mixed criticality embedded systems;cReComp: automated design tool for ROS-compliant FPGA component;dynamic ring-based multicast with wavelength reuse for optical network on chips;a task allocation method for the DTTR scheme based on the parallelism of tasks;accelerating multicore architecture simulation using application profile;full-system simulation of *** multicore architecture for performance and energy exploration;communication-based power modelling for heterogeneous multiprocessor architectures;optimizing latencies and customizing NoC of time-predictable heterogeneous multi-core processor;dual-engine cross-ISA DBTO technique utilising multithreaded support for multicore processor system;and pushing the limits of online auto-tuning: machine code optimization in short-running kernels.

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Real-Time Audio Processing on the T-CREST multicore Platform 11

Real-Time Audio Processing on the T-CREST Multicore Platform

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ausin, Daniel Sanz Pezzarossa, Luca Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9781538634417

multicore platforms are nowadays widely used for audio processing applications, due to the improvement of computational power that they provide. However, some of these systems are not optimized for temporally constrained environments, which often leads to an undesired increase in the latency of the audio signal. This paper presents a real-time multicore audio processing system based on the T-CREST platform. T-CREST is a time-predictable multicore processor for real-time embedded systems. Multiple audio effect tasks have been implemented, which can be connected together in different configurations forming sequential and parallel effect chains, and using a network-onchip for intercommunication between processors. The evaluation of the system shows that real-time processing of multiple effect configurations is possible, and that the estimation and control of latency ensures real-time behavior.

关键词： Real-time systems multicore processing Signal processing algorithms Signal processing Task analysis Software Mathematical model Signal processing algorithms task analysis Multi-core processors real-time systems signal processing Mathematical Model computer software Audio audio signals real-time process Platform Latency

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A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-Time Scheduling

A Novel Task-to-Processor Assignment Approach for Optimal Mu...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Duy Doan Kiyofumi Tanaka School of Information Science Japan Advanced Institute of Science and Technology Nomi Ishikawa Japan

ISBN: (纸本)9781538666906

Recent decades have recognized the popularization of multiprocessor architectures in real-time embedded systems. Real-time task scheduling in such systems has become a challenging problem as a result. In this paper, we are presenting an optimal scheduling algorithm, which can successfully schedule any task sets with no deadline miss if the total utilization of tasks does not exceed the capacity of the involved system. The proposed algorithm called LLA introduces a so-called fixed task-scheduling plan for every time interval that is defined as the time period between two consecutive job releases. At the beginning of each interval, LAA makes the scheduling plan by predicting tasks' requested amount of execution time within the interval and then arranging these amounts to processors appropriately respecting to requirements of scheduling. By this approach, LAA can extremely reduce the number of scheduler invocations to the number of job releases. Furthermore, simulation results show that our algorithm has lower time complexity while retaining the schedulability, task preemption, and task migration competitive to the existing optimal scheduling algorithms.

关键词： Real-time operating system Scheduling algorithm Multiprocessor Runtime overhead Multiprocessor real time operating system Scheduling algorithms MULTIPROCESSOR ARCHITECTURE time schedule Simulation results Time intervals TASK SCHEDULING Optimal scheduling jobs Religious Missions execution time complexity classes

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Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-Criteria Recommender system

Adaptive Genetic Algorithm for Improving Prediction Accuracy...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Hamada Mohamed Latifat Abdulsalam Hassan Mohammed Aizu Daigaku Aizuwakamatsu Fukushima JP Department of Computer Science and Engineering African University of Science and Technology Galadimawa Abuja Nigeria Bayero University Kano Kano NG

Recommender systems are software tools used to make valuable recommendations to users. Traditionally, recommender systems use information obtained from ratings of an item by users with similar opinions to make recommendations. A user uses a single rating to represent the degree of likeness of an item in traditional recommender systems. Though this approach has reasonably shown a good prediction accuracy, however, the performance of traditional recommender systems is considered inadequate, as users could have different opinions based on some specific features of an item. Multi-criteria recommendation extends the traditional techniques by incorporating ratings for various attributes of the items. It provides better recommendations for users as the system allows the opportunity for users to specify their preferences based on different attributes of user item, which improves prediction accuracy. In this paper, we proposed an aggregation function based method that uses an adaptive genetic algorithm to efficiently incorporate the criteria ratings for improving the accuracy of the multi-criteria recommender system. We carried out an experiment using a dataset for multi-criteria recommendations of movies to users. The experimental result shows that our proposed approach provides better accuracy than the corresponding traditional technique.

关键词： Genetic algorithms Recommender systems Sociology Statistics Biological cells Collaboration

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Construction of performance model of tile CAQR and performance result of the implementation 11

Construction of performance model of tile CAQR and performan...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Takayanagi, Masatoshi Suzuki, Tomohiro Univ Yamanashi 4-3-11 Takeda Kofu Yamanashi 4008511 Japan RIKEN Adv Inst Computat Sci Chuo Ku 7-1-26 Minatojima Minami Machi Kobe Hyogo 6500047 Japan

ISBN: (纸本)9781538634417

Highly parallel computational resources can be exploited by asynchronously executing many fine-grained tasks. The tile algorithm for matrix decomposition can generate many fine-grained tasks, so is suitable for modern multicore/manycore architectures. However, the performance of this algorithm significantly depends on the tile size. We implement the tile algorithm in OpenMP/MPI hybrid fashion on a cluster system and construct a performance model that tunes the tile size by measuring the performance of simple computational kernels in our implementation. In this report, we test our communication-avoiding tile QR implementation for tall and skinny matrices on the K computer, and demonstrate the applicability of the performance model.

关键词： Matrix decomposition Kernel Task analysis Clustering algorithms multicore processing Dynamic scheduling Computational modeling matrix decomposition task analysis PERFORMANCE MODELING dynamic scheduling Clustering algorithms Tile Computational modeling Kernel Seeds

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Evaluation and Detection of Hardware Trojan for Real-Time many-core systems 8

Evaluation and Detection of Hardware Trojan for Real-Time Ma...

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8th ieee international symposium on embedded Computing and system Design (ISED)

作者： Hazra, Suvadip Sattenapalli, Jaswanth Sai Roy, Arka Dalui, Mamata NIT Durgapur CSE Dept Durgapur 713209 W Bengal India

ISBN: (纸本)9781538665756

Due to the growing complexities of Integrated Circuits (ICs) and the current trend of Intellectual Property (IP) based hardware designs, the possible threats of Hardware Trojans are inevitable. Trojans can be inserted during the design or fabrication phase of the IC design cycle by an untrustworthy third party. A Trojan once implanted in a system component can cause an unintended modification in the system functionality resulting in a considerable performance penalty or even a system crash. The malicious activity by a Trojan may include access to highly sensitive data, thus increasing the system vulnerability. A malicious Trojan once activated, can continue to inject memory transaction through the system interconnect. Such memory transactions may result in unnecessary invalidation broadcast as well as the eviction of valid cache lines and hence resulting in a huge degradation in system performance. Even a malicious activity by a Trojan can designate an upper level cache hit for a cache line to a cache miss resulting in a Denial-of-Service (DoS) attack. This type of attack in turn greatly increases lower level memory traffic. In this work, we have considered such stealthy Trojans and evaluate their effects on the performance of a real-time many-core system. We have used machine learning based techniques for run-time detection of such Trojans. Simulation results show more than 95% accuracy in detection.

关键词： Denial-of-service attack

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An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-chips 11

An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Dai, Jindun Jiang, Xin Li, Renjie Watanabe, Takahiro Waseda Univ Grad Sch Informat Prod & Syst Tokyo Japan Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai Peoples R China

ISBN: (纸本)9781538634417

Network-on-chips (NoC) has been proven as a flexible solution for chip-Multiprocessor (CMP) systems due to its reusability and scalability. To increase communication efficiency, Three-Dimensional Networks-on-chips (3D NoCs) are developed, which can shorten the wire length and improve the system performance. In this paper, we present a novel deadlock-free adaptive routing algorithm for 3D mesh NoC interconnections. The routing rules of traditional XY routing and YX routing are relaxed and used for intra-layer routing. Via multiple layers, balanced adaptiveness can be achieved. We detail the basic principle of this method and test its efficiency through simulations.

关键词： Routing Three-dimensional displays system recovery Two dimensional displays Adaptation models Load modeling system performance three-dimensional displays system performance system recovery Network routing Load modeling network-on-chip Routing algorithms Adaptation models Wire length

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Designing Compact Convolutional Neural Network for embedded Stereo Vision systems

Designing Compact Convolutional Neural Network for Embedded ...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Mohammad Loni Amin Majd Abdolah Loni Masoud Daneshtalab Mikael Sjödin Elena Troubitsyna School of Innovation Mälardalen University Västerås Sweden Department of Information Technology ÅboAkademi University Turku Finland Computer Science and Mathematics Department Allameh Tabatabai University Tehran Iran Theoretical Computer Science Department KTH Royal Institute of Technology Stockholm Sweden

ISBN: (纸本)9781538666906

Autonomous systems are used in a wide range of domains from indoor utensils to autonomous robot surgeries and self-driving cars. Stereo vision cameras probably are the most flexible sensing way in these systems since they can extract depth, luminance, color, and shape information. However, stereo vision based applications suffer from huge image sizes and computational complexity leading system to higher power consumption. To tackle these challenges, in the first step, GIMME2 stereo vision system [1] is employed. GIMME2 is a high-throughput and cost efficient FPGA-based stereo vision embedded system. In the next step, we present a framework for designing an optimized Deep Convolutional Neural Network (DCNN) for time constraint applications and/or limited resource budget platforms. Our framework tries to automatically generate a highly robust DCNN architecture for image data receiving from stereo vision cameras. Our proposed framework takes advantage of a multi-objective evolutionary optimization approach to design a near-optimal network architecture for both the accuracy and network size objectives. Unlike recent works aiming to generate a highly accurate network, we also considered the network size parameters to build a highly compact architecture. After designing a robust network, our proposed framework maps generated network on a multi/many core heterogeneous system-on-chip (SoC). In addition, we have integrated our framework to the GIMME2 processing pipeline such that it can also estimate the distance of detected objects. The generated network by our framework offers up to 24x compression rate while losing only 5% accuracy compare to the best result on the CIFAR-10 dataset.

关键词： Computer architecture Stereo vision Image coding Network architecture Cameras Sensors Computational modeling

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Designing Efficient Parallel Processing in 3D Standard-chip Stacking system with Standard Bus 11

Designing Efficient Parallel Processing in 3D Standard-chip ...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ohkawa, Takeshi Ootsu, Kanemitsu Yokota, Takashi Kikuchi, Katsuya Aoyagi, Masahiro Utsunomiya Univ Grad Sch Engn 7-1-2 Yoto Utsunomiya Tochigi 3218585 Japan Natl Inst Adv Ind Sci & Technol Nanoelect Res Inst 1-1-1 Umezono Tsukuba Ibaraki 3058568 Japan

ISBN: (纸本)9781538634417

By storing several LSI chips with various functions, combining them easily according to needs and stack them in pile, you could construct 3D-SCSS (Three-Dimensional Standard-chip Stacking system) of high performance and low power consumption within quite short period of time and low budget. In order to reduce design costs for chip recycling, it is inevitable to standardize inter-chips signal connections and power supply system. The purpose of this research is how to create a signal connection/power supply system through standard BUS for 3D-SCSS, and a HW (Hardware) / SW (Software) design system. This paper discusses how to design 3D LSI chip stacking system with cooperative HW/SW. As a case study, a mapping design for image recognition processing is evaluated, in which partial processing is mapped onto 3D-SCSS.

关键词： 3D LSI chip Stacking HW/SW cooperative design process network model driven component

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Temporal Partitioning in Mixed-Criticality NoCs using Timely Blocking 11

Temporal Partitioning in Mixed-Criticality NoCs using Timely...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ahmadian, Hamidreza Obermaisser, Roman Univ Siegen Chair Embedded Syst Siegen Germany

ISBN: (纸本)9781538634417

The ongoing trend to integrate multiple functions with different criticalities on a single platform calls for a robust on-chip communication infrastructure in which subsystems of different criticalities can coexist and interact. A fundamental challenge in the design of such systems is to prevent low-critical subsystems from interfering with safety-critical subsystems, while providing the demanded performance for low-critical subsystems. This challenge is addressed by different technical approaches for the arbitration of the resource requests, in particular when it comes to the on-chip communication. Preemption can be used to interrupt the ongoing transmission of a low-critical message in favor of the resource request by a safe-critical subsystem. Shuffling is used as an alternative to preemption and uses a priority-based arbitration for the resource requests. This approach is used often in NoCs and interrupting the ongoing transmission at the cost of a certain effect of low-critical subsystem on safety-critical one. This paper introduces a third approach in NoCs that provides temporal partitioning of the resources by maintaining guarding windows at different levels. We describe how chip-wide segregation between the communication channels of different subsystems eliminates the interference for safety-critical subsystems and assures bounded interferences for low-critical subsystems.

关键词： Resource management Task analysis Safety Real-time systems system-on-chip Interference Hardware system-on-chip SUB-system task analysis real-time systems management of resources Computer hardware Consumer safety safety interference Arbitrating NOCT gene

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