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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Design of power monitoring system on smart hotel

Design of power monitoring system on smart hotel

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作者： Wang, Juan Bao, Zhihua Yang, Yongjie School of Electronics and Information Nantong University Nantong Jiangsu China

ISBN: (纸本)9781538636749

In view of the current lack of smart hotel power statistics network, according to the specific requirements of smart hotel design, A acquisition and monitoring system for electricity quantity based on embedded technology is designed. By collecting the voltage, current, power and power consumption of the on-site power equipment, the system uploads the data to the upper computer regularly and helps the manager to monitor the power consumption in the room conveniently and in real time, It is convenient to analyze and compensate the power consumption data of the system. The hardware part of the system uses STM32 microcontroller as the control core, with data acquisition chip BL0937, the data sent through the serial -to -WiFi module, the remote control software written by Visual C# communicates with the STM32 by TCP/IP protocol. The system has been tested in the field of Simon Hotel, and the result shows that the system has high stability. It has a good application value. © 2017 ieee.

关键词： Electricity quantity acquisition embedded technology Remote monitoring TCP/IP protocol

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Optimizing Convolution Neural Network on the TI C6678 multicore DSP 1

Optimizing Convolution Neural Network on the TI C6678 multic...

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1st international symposium on Water system Operations, ISWSO 2018

作者： Zeng, Guozhao Hu, Xiao Chen, Yueyue College of Computer National University of Defence Technology Changsha Hunan Province China

Convolutional Neural Networks (CNNs) have become the most advanced algorithms for deep learning. They are widely used in image processing, object detection and automatic translation. As the demand for CNNs continues to increase, the platforms on which they are deployed continue to expand. As an excellent low-power, high-performance, embedded solution, Digital Signal Processor (DSP) is used frequently in many key areas. This paper attempts to deploy the CNN to Texas Instruments (TI)'s TMS320C6678 multi-core DSP and optimize the main operations (convolution) to accommodate the DSP structure. The efficiency of the improved convolution operation has increased by tens of times. © The Authors, published by EDP Sciences, 2018.

关键词： Digital signal processors

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OTORNoC: Optical Tree Of Rings Network on chip for 1000 core systems 7

OTORNoC: Optical Tree Of Rings Network on Chip for 1000 Core...

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7th international symposium on embedded Computing and system Design (ISED)

作者： Poddar, Soumyajit Suraj Yadav, Amit Kumar Rahaman, Hafizur Indian Inst Informat Technol Guwahati Gauhati India Indian Inst Engn Sci & Technol Shibpur Howrah India

ISBN: (纸本)9781538630327

Optical Networks on chip are an emerging communication platform for high performance multi core systems on chip. In this work a novel thousand core topology is proposed that increases optical link utilization and scales up bandwidth to enable single chip TeraFlops performance. Performance benefits of about 1.8x and 3x reduction in optical power is obtained over the existing state of the art multicore chips.

关键词： Optical network on chip multicore WDM

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MEMS-based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous many-core systems 28

MEMS-based Runtime Idle Energy Minimization for Bursty Workl...

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28th ieee international symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

作者： Aalsaud, Ali Alrudainy, Haider Shafik, Rishad Xia, Fei Yakovlev, Alex Univ Newcastle Sch EEE Newcastle Upon Tyne NE1 7RU Tyne & Wear England Al Mustansiriya Univ Sch Engn Baghdad Iraq Southern Tech Univ Basra Engn Tech Coll Basra Iraq

ISBN: (纸本)9781538663653

Heterogeneous many-core systems are increasingly being employed in modern embedded applications for high throughput at low energy cost considerations. These applications exhibit bursty workloads that provide with opportunities to minimize system energy. Traditionally, CMOS-based power gating circuitry, consisting of sleep transistors, is used for idle energy reduction in such applications. However, these transistors contribute high leakage current when driving large capacitive loads, making effective energy minimization challenging. In this paper, we propose a novel MEMS-based runtime energy minimization approach. core to our approach is an integrated sleep mode management based on the performance-energy states and bursty workloads indicated by the performance counters. For effective energy minimization we use a systematic optimization of the controller design parameters by adopting finite element analysis (FEA) in multiphysics COMSOL tool. A number of PARSEC benchmark applications are used as case studies of bursty workloads, including CPU-and memory-intensive ones. These applications are exercised on an Exynos 5422 heterogeneous many-core platform showing up to 50% energy savings when compared with ondemand governor. Furthermore, we provide all extensive trade-off analysis to demonstrate the comparative advantages of MEMS-based controller, including zero-leakage current and non-invasive implementations suitable for commercial off-the-shelf systems.

关键词： Micromechanical devices Switches Runtime Relays Optimization Tools Analytical models"

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Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-core Processor

Evaluation of Performance and Fault Containment in AUTOSAR M...

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ieee international symposium on embedded multicore/many-core system-on-chip

作者： Moises Urbina Roman Obermaisser Institute of Embedded Systems - University of Siegen

ISBN: (纸本)9781538666906

The AUTOSAR standard does not provide an approach for the mapping of its ECU software architecture to a message-based multicore system. In this work we present an analysis of performance and fault containment of a novel TIme-triggered MEssage-based multi-core architecture for AUTOSAR (TIMEA). The TIMEA platform is intended to bring the advantages of network-on-a-chip architectures to the AUTOSAR software, which lead to multiple benefits for fail operational real time systems such as temporal predictability and fault isolation. We introduce a fault hypothesis consisting of multiple fault assumptions and the definition of the fault containment regions and we describe the algorithms for the integration of a multicore monitoring service into the AUTOSAR Basic Software. A set of experiments were carried out to evaluate the performance of the system using an anti-lock braking use case in a simulation scenario under failure occurrences. The obtained results demonstrate how the TIMEA platform remains operational in the presence of failures.

关键词： fault isolation Multi-core processors system performance

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2017 ieee 23rd international symposium on On-Line Testing and Robust system Design, IOLTS 2017

2017 IEEE 23rd International Symposium on On-Line Testing an...

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23rd ieee international symposium on On-Line Testing and Robust system Design, IOLTS 2017

ISBN: (纸本)9781538603512

The proceedings contain 60 papers. The topics discussed include: a new 3-bit burst-error correcting code;automating wafer-level test of uncooled infrared detectors using wafer-prober;deterministic network on chip for deploying real time applications on many-core processors;diagnosis with transition faults on embedded segments;design-time reliability evaluation for digital circuits;voltage margins identification on commercial x86-64 multicore microprocessors;a generic embedded sequence generator for constrained-random validation with weighted distributions;an effective functional safety infrastructure for system-on-chips;and in-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.

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Modelling Bus Contention during system Early Design Stages 12

Modelling Bus Contention during System Early Design Stages

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12th ieee international symposium on Industrial embedded systems (SIES)

作者： Trilla, David Hernandez, Carles Abella, Jaume Cazorla, Francisco J. BSC Barcelona Spain UPC Barcelona Spain Spanish Natl Res Council IIIA CSIC Barcelona Spain

ISBN: (纸本)9781538631669

Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early stages applications are not yet consolidated and IP constraints may prevent sharing them across providers, challenging the estimation of contention bounds. In this paper, we propose a model to estimate the increase in applications' execution time due to on-chip bus sharing when they simultaneously execute in a multicore. The model works with information derived from the execution of each application in isolation, hence, without the need to actually run applications simultaneously. The model improves inaccuracy with respect to the existing model, and tends to over-estimate. The latter, is very important to prevent that, during late design stages, applications miss their deadline when consolidated into the same multicore, causing costly system redesign.

关键词： multicore processing Timing Program processors Load modeling Mathematical model Schedules Analytical models

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FPGA-Based Multi-core Reconfigurable system for SAR Imaging

FPGA-Based Multi-core Reconfigurable System for SAR Imaging

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ieee international Geoscience and Remote Sensing symposium

作者： Wei Di Changlin Chen Yongxiang Liu National University of Defense Technology Changsha Hunan China

With the development of the very large scale integration circuit (VLSI), multi-core processors have been developing fast and provide a novel approach to meet the requirements of modern complex computing. Real-time SAR imaging is always a hard problem to deal with since the huge amount of data and complex processing. Therefore, we design a schedulable and scalable multi-core parallel architecture based on FPGA and map the fundamental Chirp Scaling algorithm to the system. The design of the master control core makes the system highly extensible and the dedicated computing cores are designed to accelerate the process. In addition, the system can meet the real-time requirements, and it performs well in the resource utilization and the FPGA chip takes up a small space as well.

关键词： Synthetic aperture radar Task analysis Field programmable gate arrays multicore processing Parallel processing Process control Radar polarimetry

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Voltage Margins Identification on Commercial x86-64 multicore Microprocessors 23

Voltage Margins Identification on Commercial x86-64 Multicor...

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23rd ieee international symposium on On-Line Testing and Robust system Design (IOLTS)

作者： Papadimitriou, George Kaliorakis, Manolis Chatzidimitriou, Athanasios Magdalinos, Charalampos Gizopoulos, Dimitris Univ Athens Dept Informat & Telecommun Comp Architecture Lab Athens Greece

ISBN: (纸本)9781538603529

In this paper, we explore the pessimistic voltage guardbands of two multicore x86-64 microprocessor chips that belong to different microarchitectures (one ultra-low power and one high-performance microprocessor), when programs are executed on individual cores of the CPU chips. We also examine the energy and temperature gains as positive effects of lowering the voltage in both chips while preserving the functional correctness of programs. The behavior of the cores was examined executing 8 different workloads from the SPEC CPU2006 suite. Our differential experimental study is performed on two state-of-the-art x86-64 microprocessors: an ultra-low power Intel core i5-4200U and a high-performance Intel core i7-3970X. Based on the results, the cores on each microprocessor chip behave differently for different workloads when undervolted, and the voltage guardbands are more than 15% below the nominal voltage levels. We show that the energy efficiency can be increased by a maximum of 20% and the reduction of temperature can be up to 25%.

关键词： voltage scaling characterization energy efficiency multicore x86-64 CPUs error detection and correction

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Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor

Search Space Reduction for Parameter Tuning of a Tsunami Sim...

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ieee international symposium on embedded multicore/many-core system-on-chip

作者： Kazuhiko Komatsu Takumi Kishitani Masayuki Sato Akihiro Musa Hiroaki Kobayashi Cyberscience Center Tohoku University Graduate School of Information Sciences Tohoku University

ISBN: (纸本)9781538666906

The structures of recent computing systems have become complicated such as heterogeneous memory systems with a deep hierarchy and many core systems. To achieve high performance of HPC applications on such computing systems, performance tuning is mandatory. However, the number of tuning parameters has become large due to the complexities of the systems and applications. In addition, along with the improvement of computing systems, HPC applications are getting larger and complicated, resulting in long execution time of each application execution. Due to a large number of tuning parameters and a long time of each execution, a time to search for an appropriate tuning parameter combination becomes huge. This paper proposes a method to reduce the time to search for an appropriate tuning parameter combination. By considering the characteristics of a many-core processor and a simulation code, a search space of tuning parameters is reduced. Moreover, a time of each application execution for parameter search is reduced by limiting a simulation period of an application unless characteristics of the application are changed. Through the evaluation of performance tuning using the tsunami simulation code on the Intel Xeon Phi Knight Landing processor, it is clarified that a 3.67× performance improvement can be achieved by the parameter tuning. It is also clarified that the time for parameter tuning can drastically be saved by reducing the number of tuning parameters to be searched and limiting the simulation period of each application execution.

关键词： Parameter tuning many-core processor Search space reduction Tsunami simulation

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