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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Hardware and soware infrastructure to implement many-core systems in modern FPGAs 30

Hardware and soware infrastructure to implement many-core sy...

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30th symposium on Integrated Circuits and systems Design: chip on the Sands, SBCCI 2017

作者： Bortolon, Felipe T. Moraes, Fernando G. PUCRS Porto Alegre Brazil

ISBN: (纸本)9781450351065

many-core systems are increasingly popular in embedded systems due to their high-performance and exibility to execute dierent workloads. ese many-core systems provide a rich processing fabric but lack the exibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than recongurable devices, providing embedded hard-core processors with several IP cores. While FPGAs provide a rich recongurable hardware fabric, only one or two embedded hard-core processors are available to execute complex soware applications. erefore, modern FPGAs oer the possibility to merge the benets of many-core systems with the recongurability of FPGAs. e goal of this paper is to present an infrastructure to implement many-core systems in modern FPGAs. An embedded hard-core processor is used to manage the many-core area, and to communicate with a host computer. A functional proof-of-concept system is presented, paving the way to connect dedicated hardware IPs into the NoC. © 2017 ACM.

关键词： embedded systems

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Towards a Neuromorphic Implementation of Hierarchical Temporal Memory on SpiNNaker 50

Towards a Neuromorphic Implementation of Hierarchical Tempor...

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ieee international symposium on Circuits and systems (ISCAS)

作者： Walter, Florian Sandner, Marwin Roehrbein, Florian Knoll, Alois Tech Univ Munich Chair Robot & Embedded Syst Dept Informat Garching Germany

ISBN: (纸本)9781467368537

Hierarchical Temporal Memory (HTM) is a computational model of the neocortex that is capable of online learning to predict and detect anomalies from continuous data streams. To make HTM also available on power-constrained robot systems, we investigate the feasibility of implementing the model on SpiNNaker, a fully programmable energy-efficient neuromorphic many core system. Our contribution is twofold: First, we propose a mapping of the HTM model components to the SpiNNaker chip architecture. Second, a prototypic implementation of this mapping is successfully evaluated for different sets of model parameters.

关键词： Computer architecture Robots Biological system modeling Neuromorphics Brain modeling Protocols Computational modeling

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Determining the Communication Load for Self-Building embedded systems Based on Artificial DNA 20

Determining the Communication Load for Self-Building Embedde...

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20th ieee international symposium on Real-Time Distributed Computing (ISORC)

作者： Brinkschulte, Uwe Goethe Univ Frankfurt Inst Informat Frankfurt Germany

ISBN: (纸本)9781538615744

embedded systems are growing more and more complex because of the increasing chip integration density, larger number of chips in distributed applications and demanding application fields (e.g. in cars and in households). Bio-inspired techniques like self-organization are a key feature to handle this complexity. The self-organization process needs a guideline for setting up and managing the system. In biology the structure and organization of a system is coded in its DNA. This concept can be adapted to embedded systems. Since many embedded systems can be composed from a limited number of basic elements, the structure and parameters of such systems can be stored in a compact way representing an artificial DNA deposited in each processor core. Based on the DNA, the self-organization mechanisms can build the system autonomously providing a self-building system. system repair and optimization at runtime are also possible, leading to higher robustness, dependability and flexibility. However, these properties introduce a certain amount of communication load. In this paper we determine the communication load and conduct an evaluation using a flexible DNA-controlled robot vehicle.

关键词： Artificial DNA communication load evaluation real-time self-organization self-building

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On the Complexity of Mapping Feasibility in many-core Architectures

On the Complexity of Mapping Feasibility in Many-Core Archit...

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ieee international symposium on embedded multicore/many-core system-on-chip

作者： Tobias Schwarzer Sascha Roloff Valentina Richthammer Rami Khaldi Stefan Wildermann Michael Glass Jurgen Teich Friedrich-Alexander-Universitat Erlangen-Nurnberg (FAU) Ulm University

ISBN: (纸本)9781538666906

many-core architectures enable the concurrent execution of multiple application programs. In this context, the well-known problem of feasibly mapping applications, i.e., their tasks and communication, to such architectures has gained importance due to the large number of cores and limited inter-processor communication capacities. This challenge is tackled by so-called Hybrid Application Mapping (HAM) approaches: These combine a design-time analysis to extract sets of mapping constraints that characterize feasible, respectively optimal mappings with the runtime determination of a concrete mapping in dependence of these mapping constraints and the set of currently available resources. A major strength of HAM approaches has been shown as their ability to give real-time and other guarantees for statically characterized application programs even in highly dynamic workload scenarios while avoiding the pessimism of static resource partitionings. However, finding a feasible mapping is an NP-complete problem. This work discusses arising implications for HAM approaches in general and investigates two exact techniques for solving the mapping constraints at runtime in particular: (I) a problem-specific backtracking approach, and (II) an approach that adopts a generalpurpose SAT solver. Experimental results show that the overhead of the general-purpose solver and, in particular, processing and solving the required SAT formulation becomes significant, whereas the problem-specific backtracking technique achieves significantly lower execution times.

关键词： core construction MAPPING(MATHEMATICAL) Ham ARCHITECTURE Runtime time series analysis parallel execution Pessimism Backtracking Complexity SEMI-AUTOMATIC TRIM College Entrance Examination Board Scholastic Aptitude Test Communication Research

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12th international symposium on Reconfigurable Communication-Centric systems-on-chip, ReCoSoC 2017 - Proceedings

12th International Symposium on Reconfigurable Communication...

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12th international symposium on Reconfigurable Communication-Centric systems-on-chip, ReCoSoC 2017

ISBN: (纸本)9781538633441

The proceedings contain 21 papers. The topics discussed include: side-channel attack resilience through route randomisation in secure real-time networks-on-chip;high-level test generation for processing elements in many-core systems;federated system-to-service authentication and authorization combining PUFs and tokens;characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoC;programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm;exploring the performance of partially reconfigurable point-to-point interconnects;fault-resilient NoC router with transparent resource allocation;current mode detection in hard real-time automotive applications dedicated to many-core platforms;design method for asymmetric 3D interconnect architectures with high-level models;SecBoot - lightweight secure boot mechanism for Linux-based embedded systems on FPGA;system-level design for communication-centric task farm applications;ElasticSimMATE: a fast and accurate gem5 trace-driven simulator for multicore systems;computational self-awareness as design approach for visual sensor nodes;fault recovery and adaptation in time-triggered networks-on-chips for mixed-criticality systems;analysis of heterogeneous multi-core multi-hw accelerator based systems designed using PREESM and SDSoC;high-level design using Intel FPGA OpenCL: a hyperspectral imaging spatial-spectral classifier;and energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors.

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Parallel Implementation of Randomized Singular Value Decomposition and Randomized Spatial Downsampling for Real Time Ultrafast Microvessel Imaging on a Multi-core CPUs Architecture

Parallel Implementation of Randomized Singular Value Decompo...

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ieee symposium (IUS) Ultrasonics

作者： U-Wai Lok Pengfei Song Joshua D. Trzasko Eric A. Borisch Ron Daigle Shigao Chen Department of Radiology Mayo Clinic College of Medicine and Science Rochester MN USA Verasonics Inc. Kirkland WA

Singular value decomposition (SVD)-based clutter filter is widely used for functional ultrasound imaging such as super-resolution ultrasound localized microscopy and microvessel imaging. However, the demand of high computational complexity becomes one of the critical issues for the SVD-based clutter filter. Recently, randomized SVD-based (rSVD) clutter filter has been proposed for clutter suppression; the computational time can be dramatically reduced when combing with randomized spatial downsampling. In this study, we propose the use of multicore CPU architecture to implement the rSVD-based clutter filter with randomized spatial downsampling to demonstrate that it can perform in real time. The proposed multi-core CPU architecture was embedded as an external function on a Verasonics Vantage system (Verasonics Inc., Kirkland, WA, USA). As the number of ensembles and the rank of tissue subspace are set as 50 and 20, respectively, the corresponding processing time required only around 20 ms. In addition, we also demonstrated the feasibility of real time microvessel perfusion imaging by rSVD-based clutter filter and random spatial downsampling.

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Porting the Pip Proto-Kernel's Model to Multi-core Environments

Porting the Pip Proto-Kernel's Model to Multi-core Environme...

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ieee international symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Quentin Bergougnoux Julien Cartigny Gilles Grimaud Université de Lille Lille France

ISBN: (纸本)9781538675199

In order to bring integrity and confidentiality through memory isolation in embedded devices, we developed Pip, a proto-kernel ensuring only memory isolation and control flow in the Internet of Things's computing environments. Its API is verified, ensuring the correctness of the memory isolation properties. Nevertheless, today, like Cloud Computing environments, IoT environments are becoming more and more multi-core and parallelized. Those environments introduce many new issues of consistency and concurrency, and require specific software architectures. In this paper, we discuss those new aspects, and the evolution of Pip's model into a multi-core model designed for those environments.

关键词： multicore processing Kernel Hardware Adaptation models Computational modeling Virtual machine monitors Multiplexing

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Harnessing Voltage Margins for Energy Efficiency in multicore CPUs 17

Harnessing Voltage Margins for Energy Efficiency in Multicor...

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50th Annual ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Papadimitriou, George Kaliorakis, Manolis Chatzidimitriou, Athanasios Gizopoulos, Dimitris Lawthers, Peter Das, Shidhartha Univ Athens Athens Greece Appl Micro Circuits Corp Deutschland GmbH Munich Germany ARM Ltd Cambridge England

ISBN: (纸本)9781450349529

In this paper, we present the first automated system-level analysis of multicore CPUs based on ARMv8 64-bit architecture (8-core, 28nm X-Gene 2 micro-server by AppliedMicro) when pushed to operate in scaled voltage conditions. We report detailed system-level effects including SDCs, corrected/uncorrected errors and application/system crashes. Our study reveals large voltage margins (that can be harnessed for energy savings) and also large V-min variation among the 8 cores of the CPU chip, among 3 different chips (a nominal rated and two sigma chips), and among different benchmarks. Apart from the Vmin analysis we propose a new composite metric (severity) that aggregates the behavior of cores when undervolted and can support system operation and design protection decisions. Our undervolting characterization findings are the first reported analysis for an enterprise class 64-bit ARMv8 platform and we highlight key differences with previous studies on x86 platforms. We utilize the results of the system characterization along with performance counters information to measure the accuracy of prediction models for the behavior of benchmarks running in particular cores. Finally, we discuss how the detailed characterization and the prediction results can be effectively used to support design and system software decisions to harness voltage margins for energy efficiency while preserving operation correctness. Our findings show that, on average, 19.4% energy saving can be achieved without compromising the performance, while with 25% performance reduction, the energy saving raises to 38.8%.

关键词： Energy efficiency voltage and frequency scaling power consumption error detection and correction multicore CPUs characterization micro-servers

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Power mitigation of a heterogeneous multicore architecture by frequency scaling in an OFDM receiver test case

Power mitigation of a heterogeneous multicore architecture b...

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2017 ieee Nordic Circuits and systems Conference, NORCAS 2017: NORchip and international symposium of system-on-chip, SoC 2017

作者： Nouri, Sajjad Nurmi, Jari Laboratory of Electronics and Communications Engineering Tampere University of Technology P.O. Box 553 TampereFI-33101 Finland

ISBN: (纸本)9781538628447

In this paper, an integrated self-aware computing model is applied in order to mitigate the power dissipation of a Heterogeneous multicore Architecture (HMA) used for implementing the Orthogonal Frequency-Division Multiplexing (OFDM) receiver blocks for a proof-of-concept test case. The platform consists of template-based Coarse-Grained Reconfigurable Array (CGRA) devices arranged over a Network-on-chip (NoC) around a few Reduced Instruction-Set Computing (RISC) cores. The self-aware computing model is executed by the use of Feedback Control system (FCS) which constantly monitors the execution-time of each core and then dynamically scales the operating frequency based on the worst counted execution-time. Therefore, the performance of the overall system will be equalized towards a desired level besides mitigating the power dissipation. Measurement results show that up to 20.2% dynamic power dissipation and 16.8% total power dissipation savings can be obtained for a proof-of-concept test. © 2017 ieee.

关键词： Orthogonal frequency division multiplexing

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HW/SW Co-design of an ieee 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis 2017

HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq...

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8th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Nouri, Sajjad Rettkowski, Jens Goehringer, Diana Nurmi, Jari Tampere Univ Technol Lab Elect & Commun Engn Tampere Finland Ruhr Univ Bochum Applicat Specif Multicore Architectures MCA Grp Bochum Germany Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781450353168

This paper presents an implementation of an Orthogonal Frequency-Division Multiplexing (OFDM) receiver using the high-level synthesis tool, from Xilinx called Software Defined system-on-chip (SDSoC). The Zynq SoCs containing an ARM processor besides a Field Programmable Gate Array (FPGA) are introduced to improve the system performance and power efficiency. SDSoC provides an embedded C/C++ application programming interface for developing heterogeneous embedded systems. Thus, the OFDM receiver is written in C/C++ code to be realizable on the FPGA and the ARM processor. The OFDM receiver is composed of computationally intensive tasks which requires a HW/SW co-design to fulfill system requirements. In this work, the implementation of OFDM receiver blocks are evaluated on ZC706 board and compared against the Heterogeneous Accelerator-Rich Platform (HARP). Based on the achieved results, the complete execution of the ieee 802.11a/g receiver shows an overall speed-up 3.49X compared to the HARP platform.

关键词： system-on-chip

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