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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是411-420 订阅

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Parallelization, Modeling, and Performance Prediction in the Multi-/many core Area: A systematic Literature Review 7

Parallelization, Modeling, and Performance Prediction in the...

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ieee 7th international symposium on Cloud and Service Computing (ieee SC2)

作者： Frank, Markus Hilbrich, Marcus Lehrig, Sebastian Becker, Steffen Tech Univ Chemnitz Chemnitz Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9781538658628

Context: Software developers face complex, connected, and large software projects. The development of such systems involves design decisions that directly impact the quality of the software. For an early decision making, software developers can use model-based prediction approaches for (non-)functional quality properties. Unfortunately, the accuracy of these approaches is challenged by newly introduced hardware features like multiple cores within a single CPU (multicores) and their dependence on shared memory and other shared resources. Objectives: Our goal is to understand whether and how existing model-based performance prediction approaches face this challenge. We plan to use gained insights as foundation for enriching existing prediction approaches with capabilities to predict systems running on multicores. Methods: We perform a systematic Literature Review (SLR) to identify current model-based prediction approaches in the context of multicores. Results: Our SLR covers the software engineering, embedded systems, High Performance Computing, and Software Performance Engineering domains for which we examined 34 sources in detail. We found various performance prediction approaches which tries to increase prediction accuracy for multicore systems by including shared memory designs to the prediction models. Conclusion: However, our results show that the memory designs models are only in an initial phase. Further research has to be done to improve cache, memory, and memory bandwidth model as well as to include auto tuner support.

关键词： Software multicore processing Predictive models Unified modeling language Parallel programming Hardware Computational modeling

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One-instruction set computer-based multicore processors for energy-efficient streaming data processing 28

One-instruction set computer-based multicore processors for ...

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2017 28th international symposium on Rapid system Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Yokota, Minato Saso, Kaoru Hara-Azumi, Yuko Dept. of Information and Communications Engineering Tokyo Institute of Technology Japan

ISBN: (纸本)9781450354189

For architecture designs, flexibility of application-dependent optimization for better performance and energy-efficiency and productivity enhanced by application-independent versatility and reusability are both crucial but contradicting issues. In the IoT era, due to a more stringent energy constraint and more application diversity, such issues are becoming more difficult to satisfy. Even recent embedded processors prioritize the design-productivity over flexibility, leading to a lot of energy waste in unused resources for some applications. This paper proposes novel multicore processors to address the above two issues. Our processors are composed of application-independent tiny cores and application-dependent optimizable inter-core communications, which efficiently execute applications on a large amount of streaming data, in a pipeline manner. In this work, we utilize one of the simplest RISC processors, One-Instruction Set Computer (OISC), as a core. Our evaluation demonstrates that our processors outperform an existing RISC processor in terms of performance (throughput) and energy-efficiency, while having sufficient scalability, for two different types of applications. © 2017 ACM.

关键词： Energy efficiency

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PACENet: Energy Efficient Acceleration for Convolutional Network on embedded Platform 50

PACENet: Energy Efficient Acceleration for Convolutional Net...

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ieee international symposium on Circuits and systems (ISCAS)

作者： Kulkarni, Adwaya Abtahi, Tahmid Shea, Colin Kulkarni, Amey Mohsenin, Tinoosh Univ Maryland Baltimore Cty Dept Comp Sci & Elect Engn Baltimore MD 21228 USA

ISBN: (纸本)9781467368537

Lightweight convolutional neural network (CNN) on tiny embedded platforms can offer energy efficient solution for today's IoT devices. However, CNN implementation on embedded system faces processing bottleneck in convolutional layers and memory storage issues in fully connected layers. In past years, heterogeneous acceleration, where compute intensive tasks are performed on kernel specific cores, has gained attention. In this paper we propose, a domain specific and programmable accelerator "PACENet" Programmable many-core ACcElerator for convolution neural Network architecture. It consists of neural network kernel specific instruction set architecture such as convolution, maxpool and relu. To demonstrate efficiency of the proposed PACENet, we implemented ResNet-20 for CIFAR-10 dataset, where PACENet performs convolution layer, Relu activations, Maxpool layer, and fully-connected layer. We also implemented ResNet-20 for CIFAR-10 dataset on NVIDIA TX1 mobile GPU platform using Tensorflow and cuDNN libraries. Compared to NVIDIA TX1 platform implementation PACENet platform implementation performs 1.4x to 4.5x faster and saves 2.8x to 9x energy consumption respectively. PACENet achieves 2.9x to 9.3x higher throughput per watt as compared to TX1 platform implementation

关键词： Energy efficient Domain-specific many-core Convolutional Neural Network (CNN) Accelerator Machine Learning

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Proceedings - ieee international symposium on Rapid system Prototyping, RSP

Proceedings - IEEE International Symposium on Rapid System P...

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2017 28th international symposium on Rapid system Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

ISBN: (纸本)9781450354189

The proceedings contain 15 papers. The topics discussed include: energy-efficient and robust middleware prototyping for smart mobile computing;constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates;prototyping dynamic task migration on heterogeneous reconfigurable systems;PoliCym: rapid prototyping of resource management policies for HMPs;simulation-based circuit-activity estimation for FPGAs containing hard blocks;software platform dedicated for in-memory computing circuit evaluation;executable dataflow benchmark generation technique for multi-core embedded systems;time synchronization services for low-cost fog computing applications;an analysis of random cache effects on real-time multi-core scheduling algorithms;one-instruction set computer-based multicore processors for energy-efficient streaming data processing;towards end-to-end trainable hardware;mobile/embedded neural networks and applications;the extendable translating instruction set simulator (ETISS) interlined with a code generation framework for fast RISC prototyping;rapid prototyping of IoT applications with Esperanto compiler;binary synthesis implementing external interrupt handler as independent module;and speculative execution in distributed controllers for high-level synthesis.

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A Hardware Acceleration for Surface EMG Non-Negative Matrix Factorization 31

A Hardware Acceleration for Surface EMG Non-Negative Matrix ...

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31st ieee international Parallel and Distributed Processing symposium Workshops (IPDPS)

作者： Cerina, Luca Cancian, Pierandrea Franco, Giuseppe Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9780769561493

To the present day, a multitude of studies aims to understand how the Central Nervous system (CNS) translates neural pulses to muscle motor tasks, through the analysis of surface EMG (sEMG) recordings. One of the most considerable methods applies the Non-Negative Matrix Factorization (NMF) to data recorded from sEMG electrodes, to extract coordinated motor patterns, the so-called muscle synergies, which hypothesize a modular control of the muscles by the CNS. The application of NMF could lead to novel applications in muscular rehabilitation or advanced prosthesis motor control. However, its application is still restricted to research laboratories, because the complexity of the NMF algorithm does not allow an efficient implementation on embedded systems, such as portable or wearable devices. This paper presents a FPGA-based hardware acceleration of a NMF algorithm, the Projected Gradient Alternating Least Square (ALS-PG), on a Xilinx Zynq7000 system-on-chip (SoC) development board. In particular, we propose a case study for the pre-processing of sEMG in a hand prosthesis control system, where the NMF is subject to realtime processing constraints. Preliminary hardware optimizations produced a overall speed-up of 2.92x of the algorithm (23.9x considering only the accelerated sections) compared to the software implementation executed on the board ARM core. The real-time constraint could not be met because the entire process is slower than a standard CPU implementation (6.14x worse), nevertheless, the overall system shown a promising increase in the power efficiency of 1.65x.

关键词： biomedical engineering embedded development FPGA hardware acceleration motor control surface EMG

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2017 11th ieee/ACM international symposium on Networks-on-chip, NOCS 2017

2017 11th IEEE/ACM International Symposium on Networks-on-Ch...

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11th ieee/ACM international symposium on Networks-on-chip, NOCS 2017

ISBN: (纸本)9781450349840

The proceedings contain 20 papers. The topics discussed include: minimally buffered deflection routing with in-order delivery in a torus;distributed and dynamic shared-buffer router for high-performance interconnect;a novel approach to reduce packet latency increase caused by power gating in network-on-chip;improving the reliability and energy-efficiency of high-bandwidth photonic NoC architectures with multilevel signaling;energy and area efficient near field inductive coupling: a case study on 3D NoC;achieving lightweight multicast in asynchronous NoCs using a continuous-time multi-way read buffer;BiNoCHS: bimodal network-on-chip for CPU-GPU heterogeneous systems;synchoricity and NOCs could make billion gate custom hardware centric SOCs affordable;system-level design of networks-on-chip for systems-on-chip;addressing extensibility and fault tolerance in CAN-based automotive systems;JAMS: jitter-aware message scheduling for FlexRay automotive networks;hybrid automotive in-vehicle networks;fairness-oriented and location-aware NUCA for many-core SoC;on the accuracy of stochastic delay bound for network on chip;SMART: a scalable mapping and routing technique for power-gating in NoC routers;on runtime communication- and thermal-aware application mapping in 3D NoC;3D NoC-enabled heterogeneous manycore architectures for accelerating CNN training: performance and thermal trade-offs;rethinking NoCs for spatial neural network accelerators;and adaptive manycore architectures for big data computing.

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Asymmetric multiprocessing techniques in smart devices: application in a drone navigation system 25

Asymmetric multiprocessing techniques in smart devices: appl...

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25th international Conference on Software, Telecommunications and Computer Networks (SoftCOM)

作者： Nao, Laura Passaro, Pierluigi Gioia, Egidio Petracca, Matteo Scuola Super Sant Anna Pisa Italy Phoenixsoftware Venice Italy Arrow Elect Inc Milan Italy

ISBN: (纸本)9781538632123

Smart devices can be considered an essential element of the Internet-of-Things (IoT) revolution. Devices able to gather and process data to provide high-level information to other nodes will enable advanced and effective smart applications in the near future. To let IoT objects to become smarter and smarter, advanced embedded architecture must be considered. In this direction, this paper exploits the use of heterogeneous Asymmetric MultiProcessing (AMP) techniques in the IoT scenario by considering a smart device in which real-time acquisition and processing capabilities are necessary: a drone. In the paper an AMP-based drone system is first presented, considering a system-on-chip (SoC) solution based on microprocessors and microcontrollers. Then time performance in navigation parameters acquisition and processing is presented, considering a real-time operating system running on the core delegated to such task. Presented results show the benefits of the proposed approach in which high real-time constraints are satisfied in calculating navigation parameters, while other demanding IoT tasks can be executed simultaneously. Along with the selected use case, the proposed approach can be used in a wide range of smart devices in which higher computational performance are required.

关键词： Sensors Drones multicore processing Real-time systems Navigation

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Fairness-oriented and location-aware NUCA for many-core SoC 17

Fairness-oriented and location-aware NUCA for many-core SoC

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11th ieee/ACM international symposium on Networks-on-chip, NOCS 2017

作者： Wang, Zicong Chen, Xiaowen Li, Chen Guo, Yang National University of Defense Technology Changsha Hunan China KTH Royal Institute of Technology Kista Stockholm Sweden

ISBN: (纸本)9781450349840

Non-uniform cache architecture (NUCA) is often employed to organize the last level cache (LLC) by Networks-on-chip (NoC). However, along with the scaling up for network size of systems-on-chip (SoC), two trends gradually begin to emerge. First, the network latency is becoming the major source of the cache access latency. Second, the communication distance and latency gap between different cores is increasing. Such gap can seriously cause the network latency imbalance problem, aggravate the degree of non-uniform for cache access latencies, and then worsen the system performance. In this paper, we propose a novel NUCA-based scheme, named fairness-oriented and location-aware NUCA (FL-NUCA), to alleviate the network latency imbalance problem and achieve more uniform cache access. We strive to equalize network latencies which are measured by three metrics: average latency (AL), latency standard deviation (LSD), and maximum latency (ML). In FL-NUCA, the memory-to-LLC mapping and links are both non-uniform distributed to better fit the network topology and traffics, thereby equalizing network latencies from two aspects, i.e., non-contention latencies and contention latencies, respectively. The experimental results show that FL-NUCA can effectively improve the fairness of network latencies. Compared with the traditional static NUCA (SNUCA), in simulation with synthetic traffics, the average improvements for AL, LSD, and ML are 20.9%, 36.3%, and 35.0%, respectively. In simulation with PARSEC benchmarks, the average improvements for AL, LSD, and ML are 6.3%, 3.6%, and 11.2%, respectively. © 2017 Association for Computing Machinery.

关键词： Network-on-chip

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5th IFIP TC 10 international embedded systems symposium, IESS 2015

5th IFIP TC 10 International Embedded Systems Symposium, IES...

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5th IFIP TC 10 international embedded systems symposium, IESS 2015

ISBN: (纸本)9783319900223

The proceedings contain 18 papers. The special focus in this conference is on. The topics include: Modeling and analysis of SLDL-Captured NoC abstractions;taming the memory demand complexity of adaptive vision algorithms;HMC and DDR performance trade-offs;managing cache memory resources in adaptive many-core systems;A UML profile to couple the production code generator TargetLink with UML design tools;Rapid, high-level performance estimation for DSE using calibrated weight tables;Low latency FPGA implementation of Izhikevich-Neuron model;reconfigurable buffer structures for coarse-grained reconfigurable arrays;Multi-agent based implementation of an embedded image processing system in FPGA for precision agriculture using UAVs;combining service-oriented computing with embedded systems - A robotics case study;integration of robot operating system and ptolemy for design of real-time multi-robots environments;bit-precise formal verification for systemC using satisfiability modulo theories solving;Timed path conditions in MATLAB/Simulink;structural contracts – Motivating contracts to ensure extra-functional semantics;combining an iterative state-based timing analysis with a refinement checking technique;hierarchical multicore-scheduling for virtualization of dependent real-time systems.

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Power Management Controller for Online Power Saving in Network-on-chips 10

Power Management Controller for Online Power Saving in Netwo...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Friederich, Stephanie Neber, Marco Becker, Juergen Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9781509035311

Growing chip integration density and increasing frequencies lead to tremendous leakage power and henceforth to chip heat problems. Power management is one possibility to reduce the power consumption and get the temperature problem under control. Current technology mainly focuses on powergating techniques on basis of multi-core systems but leaving the network perspective out of scope. We provide a holistic concept, bringing together power-gating and frequency scaling techniques for network-on-chips. Following this, network static power consumption could be minimized without affecting the system performance. We present a light-weight power management controller for network-on-chips with online monitoring to optimize the power consumption of network resources. Our work comprises a hardware simulation model for design space exploration of varying technology specific parameters and an FPGS based prototype for verification. The power saving potential heavily depend on the network communication load. Our power controller adds only 2.1% of resources while 28.11% of the total power could be saved with clock gating.

关键词： embedded multicore/many-core systems-on-chip Network-on-chip Low-power design

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