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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Constrained Mixed-Critical Parallelization for Distributed Heterogeneous systems 9

Constrained Mixed-Critical Parallelization for Distributed H...

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9th ieee international Conference on Intelligent Data Acquisition and Advanced Computing systems - Technology and Applications (IDAACS)

作者： Hoettger, Robert Oezcelikoers, Mustafa Heisig, Philipp Krawczyk, Lukas Wolff, Carsten Igel, Burkhard IDiAL Inst Dortmund Univ Appl Sci & Arts Dortmund Germany

ISBN: (纸本)9781538606971

Distributing software effectively to multi core, many core, and distributed systems has been studied for decades but still advances successively driven by domain specific constraints. Programming vehicle ECUs is one of the most constrained domains that recently approached the need for concurrency due to advanced driver assistant systems or autonomous driving approaches. In this paper, software distribution challenges for such systems are discussed and solutions are presented for instruction precise modeling, affinity constrained distribution, and reducing task response times achieved by advanced software parallelization. Therefore, existing partitioning and mapping algorithms are advanced to consider affinity constraints, software component tags and communication costs. Our experiments along a remote controlled model car show that using our new advanced results instead of sequential implementations or software distributions provided by the operating system on a distributed heterogeneous system significantly improves its responsiveness in order to potentially reduce energy consumption and replaces error prone manual constraint considerations for mixed-critical applications.

关键词： Constrained parallelization heterogeneous systems distributed systems multicore parallel embedded systems

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embedded Toggle Generator to Control the Switching Activity during Test of Digital 2D-SoCs and 3D-SICs 27

Embedded Toggle Generator to Control the Switching Activity ...

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27th international symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

作者： Katselas, Leonidas Athanasiadis, Angelos Hatzopoulos, Alkis Jiao, Hailong Papameletis, Christos Marinissen, Erik Jan Aristotle Univ Thessaloniki Univ Campus Thessaloniki 54124 Greece IMEC Kapeldreef 75 B-3001 Leuven Belgium Cadence Design Syst 1701 North St Endicott NY 13760 USA Eindhoven Univ Technol Den Dolech 2 NL-5612 AZ Eindhoven Netherlands Peking Univ Shenzhen Grad Sch Shenzhen Peoples R China

ISBN: (纸本)9781509064625

In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked ICs (SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are being tested ('module-under-test', MUT);we refer to the modules currently not being tested as 'neighbors'. The switching activity of the MUT(s) can be controlled by ATPG constraints, but the switching activity of the neighboring modules is typically not controlled. In this work, we present two key elements for an approach to control the switching activity of both MUT(s) and neighboring modules. The first is a toggle analysis tool, that determines the switching activity of a module in either functional or test mode on the basis of a Value Change Dump (.vcd) file generated during gate-level Verilog netlist simulation. The second element is a programmable on-chip toggle generator, for which we present both its hardware scheme, as well as an algorithm to program it to achieve any target switching activity. For each module, the toggle analysis tool can be used to determine the switching activity in functional mode, which then forms the target for the ATPG tool when the module is a MUT, or for its embedded toggle generator while the module is in its role as neighbor.

关键词： Switches Generators Tools Clocks Integrated circuit modeling Switching circuits dynamos Switched circuits integrated circuit modelling Timing devices TOGGLE Switches switching MUT gene automatic test pattern generation embedded core digital logic circuit

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A Robust Methodology for Performance Analysis on Hybrid embedded multicore Architectures 10

A Robust Methodology for Performance Analysis on Hybrid Embe...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Saussard, Romain Bouzid, Boubker Vasiliu, Marius Reynaud, Roger Renault SAS Guyancourt France Univ Paris Saclay SATIE ENS Cachan Orsay France

ISBN: (纸本)9781509035311

Today's vehicles increasingly embed software intelligence in order to be safer for the driver, and to achieve autonomous driving in a close future. To answer the computational needs of these algorithms, system-on-chip (SoC) suppliers propose heterogeneous architectures. With such complex SoCs, embedding applications in vehicle becomes more and more complex for car manufacturers. Indeed, it is not trivial to find the best suited SoC for a given application, and to define load balancing strategies when working with heterogeneous architectures. These difficulties can be overcome by using performance prediction, based on computing architectures models. To build these models, we provide a set of test vectors which automatically extract key characteristics of tested architectures. Our methodology is able to perform a complete computing architecture model, by using 3 different levels of tests, each one characterizing a specific situation representative of real applications. We aim to obtain performance prediction for different applications, for any embedded SoCs based on models performed with this methodology. In this paper, we describe our characterization methodology, and show results obtained with embedded SoCs used for automotive applications.

关键词： system-on-chip

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A Data Locality and Memory Contention Analysis Method in embedded NUMA Multi-core systems 10

A Data Locality and Memory Contention Analysis Method in Emb...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Li, Lin Fussenegger, Markus Cichon, Gordon Infineon Technol AG Munich Germany Ludwig Maximilians Univ Munchen Munich Germany

ISBN: (纸本)9781509035311

Data locality in distributed memories has a significant performance impact on NUMA multi-core systems owing to non-uniform memory accesses. In addition, memory contention also influences the performance of multi-core systems. The performance degradation caused by both effects should be analyzed before performance optimization because data locality and memory contention are mutually dependent. A reduction of one effect could cancel performance gains due to another effect. A novel post-processing method based on non-intrusive tracing is proposed in this paper to analyze the performance impact incurred by both data locality and memory contention in a quantitative, comparable way. It makes use of non-intrusive tracing, which has no impact on normal execution and timing. The analysis provides results including data locality and memory contention penalties, which can be used as a reference to improve performance.

关键词： embedded system Memory contention multicore NUMA trace

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Distributed Dynamic Rate Adaptation on a Network on chip with Traffic Distortion 10

Distributed Dynamic Rate Adaptation on a Network on Chip wit...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Durand, Yves Bernard, Christian Clermidy, Fabien Univ Grenoble Alpes F-38000 Grenoble France CEA LETI MINATEC Campus F-38054 Grenoble France

ISBN: (纸本)9781509035311

A NoC-based system subject to real-time constraints requires hard bounds on end-to-end data transfer latencies. Regulating the channel injection rates solves the problem by suppressing link congestion and router queue saturation, provided that the channel rates guarantee fairness in the data distribution. We propose a distributed algorithm for the computation of a channel rate vector solution, suitable for run-time execution on the system. The algorithm takes into account the capacity constraints on every link, but also fulfills the distortion constraints. It leads to a near-optimal solution in a few iterations, with less than 10% of vector distance from the optimal solution. The algorithm is valid for software implementation on manycore systems and applicable to any Network-On-chip based system. Our hardware implementation is distributed into the network infrastructure and converges in around 500 clock cycles on a 4x4 network configuration.

关键词： many-core Network-On-chip Network Calculus

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Programming models and methods for heterogeneous parallel embedded systems 10

Programming models and methods for heterogeneous parallel em...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Casale-Brunet, Simone Bezati, Endri Mattavelli, Marco Ecole Polytech Fed Lausanne SCI STI MM Lausanne Switzerland

ISBN: (纸本)9781509035311

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded processors. Past research works have shown that raising the level of abstraction of design stages does not necessarily come at penalties in results in terms of performance or resource requirements. Dataflow programs provide a high-level behavioral descriptions capable of expressing both sequential and parallel components of application algorithms and enable natural design abstractions, modularity, and portability. This paper presents an overview of the main features, recent achievements and results of a design-flow, entirely dataflow based, and the associated tools capable of implementing and optimizing complex signal processing system applications on heterogeneous and massive parallel embedded systems.

关键词： Digital signal processing

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Design of Power Monitoring system On Smart Hotel

Design of Power Monitoring System On Smart Hotel

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10th international symposium on Computational Intelligence and Design (ISCID)

作者： Wang, Juan Bao, Zhihua Yang, Yongjie Nantong Univ Sch Elect & Informat Nantong Jiangsu Peoples R China

ISBN: (纸本)9781538636749

In view of the current lack of smart hotel power statistics network, according to the specific requirements of smart hotel design, A acquisition and monitoring system for electricity quantity based on embedded technology is designed. By collecting the voltage, current, power and power consumption of the on-site power equipment, the system uploads the data to the upper computer regularly and helps the manager to monitor the power consumption in the room conveniently and in real time, It is convenient to analyze and compensate the power consumption data of the system. The hardware part of the system uses STM32 microcontroller as the control core, with data acquisition chip BL0937, the data sent through the serial -to -WiFi module, the remote control software written by Visual C# communicates with the STM32 by TCP/IP protocol. The system has been tested in the field of Simon Hotel, and the result shows that the system has high stability. It has a good application value.

关键词： embedded technology electricity quantity acquisition TCP/IP protocol remote monitoring

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Full-system Simulation of *** multicore Architecture for Performance and Energy Exploration 10

Full-System Simulation of *** Multicore Architecture for Per...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Butko, Anastasiia Bruguier, Florent Gamatie, Abdoulaye Sassatelli, Gilles Novo, David Torres, Lionel Robert, Michel CNRS LIRMM Montpellier France Univ Montpellier Montpellier France

ISBN: (纸本)9781509035311

Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big. LITTLE. These processors offer increased energy efficiency through combining low power in-order cores with high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so as to meet the demands of targeted applications. In this paper, we explore the design of those architectures based on the ARM *** technology by modeling performance and power in gem5 and McPAT frameworks. Our models are validated w.r.t. the Samsung Exynos 5 Octa (5422) chip. We show average errors of 20% in execution time, 13% for power consumption and 24% for energy-to-solution.

关键词： Full-system simulation single-ISA heterogeneous multicore gem5 McPAT performance energy accuracy ARM big.LITTLE

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2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection systems on multicores 10

2-Step Power Scheduling with Adaptive Control Interval for N...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Lau Phi Tuong Kimura, Keiji Waseda Univ Dept Comp Sci & Engn Green Comp Syst Res & Dev Ctr Tokyo Japan

ISBN: (纸本)9781509035311

Network intrusion detection system (NIDS) is becoming an important element even in embedded systems as well as in data centers since embedded computers have been increasingly exposed to the Internet. The demand for power budget of these embedded systems is a critical issue in addition to that for performance. In this paper, we propose a technique to minimize power consumption in the NIDS by 2-step power scheduling with the adaptive control interval. In addition, we also propose a CPU-core controlling algorithm so that our scheduling technique can preserve the performance for other applications and NIDS assuming the cases of multiplexing NIDS and them simultaneously on the same device such as a home server or a mobile platform. We implement our 2-step algorithm into Suricata, which is a popular NIDS, as well as a 1-step algorithm with the adaptive interval, and a simple fixed-interval algorithm for evaluations. Experimental results show that our 2-step scheduling with both the adaptive and the fixed 30-millisecond interval achieve 75% power saving comparing with the Ondemand governor and 87% comparing with the Performance governor in Linux, respectively, without affecting their performance capability on four ARM Cortex-A15 cores at the network traffic of 1,000 packets/seconds. In contrast, when the network traffic reaches to 17,000 packets/seconds, our 2-step scheduling and the Ondemand as well as the Performance governor can maintain the packet processing capacity while the fixed 30-milliseconds interval processes only 50% packets with two and three cores, and about 80% packets on four cores.

关键词： Network Intrusion Detection system (NIDS) Dynamic Voltage Frequency Scaling (DVFS) Suricata Data Center

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Network on chip and parallel computing in embedded systems 10

Network on chip and parallel computing in embedded systems

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Belkacemi, Dihia Bouchebaba, Youcef Daoui, Mehammed Lalam, Mustapha Univ Tizi Ouzou Lab Rech Informat Tizi Ouzou Algeria ONERA Toulouse Toulouse France

ISBN: (纸本)9781509035311

In order to cope with the increasing application requirements, heterogeneous MPSoC are considered as the major solution of future embedded systems thanks to their advantages in performance and low power dissipation. However traditional communication infrastructure such as a bus or a point to point are not scalable and become communication bottleneck for large systems. Network on chip (NoC) architectures have been proposed to handle this communication problem. One of the most critical problem in NoC based heterogeneous MPSoC is how to map an application on this platform. Due to the large solution search space, design of tools that can automate this step is of major importance. In this paper, we present a new tool for mapping applications on NoC based heterogeneous MPSoC. A set of multi-objective optimization algorithms are used to explore the mapping space and to find a set of Pareto optimal solutions.

关键词： Network-on-chip

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