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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是431-440 订阅

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High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture 10

High-Precision Power Modelling of the Tegra K1 Variable SMP ...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Stokke, Kristoffer Robin Stensland, Hakon Kvale Halvorsen, Pal Griwodz, Carsten Simula Res Lab Oslo Norway Univ Oslo Oslo Norway

ISBN: (纸本)9781509035311

Energy efficiency is an important issue for many embedded systems, where limited battery lifetime and power-hungry hardware constrain the usefulness of such devices. Modern systems-on-chip (SoCs) such as the Tegra K1 employ advanced power management capabilities such as two CPU clusters, clock-gating, power-gating and dynamic frequency tuning to meet application demands. At design or runtime phases, it is challenging for system architects and software developers to understand the effects that these mechanisms have in terms of power and performance in all parts of the system. This is because it is impossible to measure directly the power usage of cores, caches, memory and other hardware components. Rate-based power models are often proposed as a solution for this, unfortunately these can mispredict substantially on the Tegra K1 up to 30 %. In this paper, we propose a power modelling method for the Tegra K1 CPU which overcomes the limitations of the most common types of models found in literature, but still only requires power measurement of the board. Through extensive empirical validation, we demonstrate an accuracy which is close to 100 %. Preliminary experiments show that our methodology is able to capture instruction power of individual system processes and applications and produce detailed power breakdowns of all components in the system.

关键词： system-on-chip

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Supporting Static Binding in Stream Rewriting for Heterogeneous many-core Architectures 10

Supporting Static Binding in Stream Rewriting for Heterogene...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Middendorf, Lars Haubelt, Christian Univ Rostock Rostock Germany

ISBN: (纸本)9781509035311

Heterogeneous multi and many-core systems offer numerous benefits like reduced energy consumption and improved throughput for both high-performance and low-power applications. However, beside the design of the actual hardware architecture, also the programming of many-core systems raises several challenges. For this purpose, we extend the existing concept of stream rewriting into a model of computation for the specification of highly concurrent applications on heterogeneous systems. In particular, our approach permits to partition the stream and to bind different sections to specialized hardware components. Since stream rewriting manages a large number of active tasks without a central scheduler, we can perform the distribution and synchronization of work-items asynchronously to improve hardware utilization. Several case studies using an FPGA prototype demonstrate the scalability of our approach.

关键词： hardware rendering shader stream rewriting streaming

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The Role of Self-Awareness and Hierarchical Agents in Resource Management for many-core systems 10

The Role of Self-Awareness and Hierarchical Agents in Resour...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Gotzinger, Maximilian Rahmani, Amir M. Pongratz, Martin Liljeberg, Pasi Jantsch, Axel Tenhunen, Hannu Univ Turku Dept Informat Technol SF-20500 Turku Finland TU Wien Inst Comp Technol Vienna Austria

ISBN: (纸本)9781509035311

The future of Moore's Law is in jeopardy. The number of cores of many-core systems is steadily increasing for every technology node generation. Voltage scaling does not keep pace with the unabated decrease of transistor size. Higher leakage power and manufacturing variabilities are the consequences and lead to extremely critical power as well as thermal issues. These phenomena can downgrade the performance or endanger system's functionality as well as its reliability if they are not properly addressed. In near future, up to 90% of a many-core chip's area may have to remain inactive;this non-active area is termed Dark Silicon. These issues make the problem of resource management challenging. Future management systems need to be intelligent, anticipatory, and self-adaptive. They are supposed to integrate management of different aspects such as thermal, power, energy, performance, quality of service, process variability, occurrence of faults and aging effects, all in one. In this paper, we study the contributions in the literature focusing on techniques for dynamic resource management in multi-and many-core systems. We put emphasis on advanced approaches that exhibit learning, self-awareness, hierarchical monitoring and management. We categorize the existing approaches from a new perspective and argue that a self-aware hierarchical agent-based model is a proper methodology to monitor and management many-core systems, in particular when they need to deal with different competing goals. In addition, we evaluate the main objectives and trends in resource management of many-core systems in order to pave the way for designing future computer systems ranging from high-performance computers to embedded processors used in the era of Internet-of-Things.

关键词： Self-Awareness Hierarchical Agent-Based system many-core Dark Silicon Power- Thermal- and Reliability Management

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A Benes Based NoC Switching Architecture for Mixed Criticality embedded systems 10

A Benes Based NoC Switching Architecture for Mixed Criticali...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Kerrison, Steve May, David Eder, Kerstin Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9781509035311

Multi-core, Mixed Criticality embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect becomes a potential point of uncertainty, introducing major challenges in proving behaviour is always within specified constraints, limiting the means of growing system performance to add more tasks, or provide more computational resources to existing tasks. We present MCENoC, a Network-on-chip (NoC) switching architecture that provides innovations to overcome this with predictable, formally verifiable timing behaviour that is consistent across the whole NoC. We show how the fundamental properties of Benes networks benefit MCE applications and meet our architecture requirements. Using systemVerilog Assertions (SVA), formal properties are defined that aid the refinement of the specification of the design as well as enabling the implementation to be exhaustively formally verified. We demonstrate the performance of the design in terms of size, throughput and predictability, and discuss the application level considerations needed to exploit this architecture.

关键词： formal verification FPGA Mixed criticality network on chip non-blocking switches timing predictable

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Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor 10

Optimizing Latencies and Customizing NoC of Time-Predictable...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Salcic, Zoran Nadeem, Muhammad Park, Heejong Teich, Juergen Univ Auckland Dept Elect & Comp Engn Auckland New Zealand Friedrich Alexander Univ Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781509035311

The Time-Predictable Heterogeneous multicore Processor (TP-HMP) is based on a NoC and fully implemented in a standard FPGA chip. The NoC uses TDMA-MIN interconnect with bounded latency, high throughput and low implementation cost. TP-HMP is used for execution of programs written in concurrent GALS language systemJ suited for both soft and hard real-time systems. It uses two types of cores in different configurations and is suitable for static analysis of schedules that implement the program control flow and concurrency. The configuration and number of cores of both types used to achieve specific performance measures can be tailored/optimized for a given application. In this paper we focus on optimization of latency of TDMA-MIN NoC, which also results in mapping of processor cores on physical ports of NoC and optimal TDMA round. We also analyze the performance of TP-HMP execution of the benchmark program used in industrial automation case study.

关键词： NoC optimal latency multicore FPGA systemJ

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Accelerating multicore Architecture Simulation Using Application Profile 10

Accelerating Multicore Architecture Simulation Using Applica...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Kimura, Keiji Taguchi, Gakuho Kasahara, Hironori Waseda Univ Dept Comp Sci & Engn Shinjuku Ku 3-4-1 Okubo Tokyo Japan

ISBN: (纸本)9781509035311

Architecture simulators play an important role in exploring frontiers in the early stages of the architecture design. However, the execution time of simulators increases with an increase the number of cores. The sampling simulation technique that was originally proposed to simulate single-core processors is a promising approach to reduce simulation time. Two main hurdles for multi/many-core are preparing sampling points and thread skewing at functional simulation time. This paper proposes a very simple and low-error sampling-based acceleration technique for multi/many-core simulators. For a parallelized application, an iteration of a large loop including a parallelizable program part, is defined as a sampling unit. We apply X-means method to a profile result of the collection of iterations derived from a real machine to form clusters of those iterations. Multiple iterations are exploited as sampling points from these clusters. We execute the simulation along the sampling points and calculate the number of total execution cycles. Results from a 16-core simulation show that our proposed simulation technique gives us a maximum of 443x speedup with a 0.52% error and 218x speedup with 1.50% error on an average.

关键词： many-core Simulator Compiler

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A Task Allocation Method for the DTTR Scheme based on the Parallelism of Tasks 10

A Task Allocation Method for the DTTR Scheme based on the Pa...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Saito, Hiroshi Imai, Masashi Yoneda, Tomohiro Univ Aizu Aizu Wakamatsu Fukushima Japan Hirosaki Univ Hirosaki Aomori Japan Natl Inst Informat Koganei Tokyo Japan

ISBN: (纸本)9781509035311

In this paper, we propose a task allocation method for multi-core systems with the Duplication with Temporary Triple Modular Redundancy and Reconfiguration (DTTR) scheme. The proposed method optimizes both performance and reliability by allocating copies of tasks (i.e., redundant tasks) based on the maximum parallelism of tasks in a give application. In the experimental results, we compare the average failure rate of task allocations obtained by the proposed method with the one obtained by a scheduling-based task allocation method and the one obtained by a task allocation method based on Simulated Annealing. The proposed method realizes both high performance and high reliability in the cases when enough cores to maximize parallel execution of tasks exist.

关键词： clique partitioning Multi-core systems reliability task allocation

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Temperature and Process-Aware Performance Monitoring and Compensation for an ULP Multi-core Cluster in 28nm UTBB FD-SOI Technology 27

Temperature and Process-Aware Performance Monitoring and Com...

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27th international symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

作者： Di Mauro, Alfio Rossi, Davide Pullini, Antonio Flatresse, Phillipe Benini, Luca Univ Bologna DEI Via Risorgimento 2 I-40136 Bologna Italy ETHZ Integrated Syst Lab Gloriastr 35 CH-8092 Zurich Switzerland STMicroelectronics 850 Rue Jean Monnet F-38920 Crolles France

ISBN: (纸本)9781509064625

Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultra low-power (ULP) devices that operate in near-threshold, due to the magnification of process variations and to the strong thermal inversion that affects advanced technology nodes. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to efficiently compensate, at run-time, these variations. The proposed method exploits on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with on-chip low-power Body Bias Generators. We characterize the response of the PMBs versus the maximum achievable frequency of the system, deriving a predictive model able to estimate such frequency with an error of 3%. We apply this model to compensate Temperature-induced performance variations, estimating the maximum frequency with an error of 7%;we eliminate the error by adding an appropriate body-bias margin resulting in a worst case global power consumption overhead of 5%. As further improvement, we generalize the methodology to compensate also process variations, obtaining an error of 28% on the estimated maximum performance and compensating this error with an overhead of 17% on the global power consumption.

关键词： Errors

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Data and commands communication protocol for neuromorphic platform configuration 10

Data and commands communication protocol for neuromorphic pl...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Siino, Alessandro Barchi, Francesco Davies, Sergio Urgese, Gianvito Acquaviva, Andrea Politecn Torino Dept Control & Comp Engn DAUIN Cso Duca Abruzzi24 I-10129 Turin Italy

ISBN: (纸本)9781509035311

In this paper, we present a new network protocol and methodology to enhance the configuration phase of the SpiNNaker spiking neural network hardware simulator. We have developed a system able to accept and process on-board a set of configuration primitives (data specification) encapsulated into ad-hoc packets, avoiding the management of chip memory from the host computer. We performed a study of the data specification generator implemented in the host software library. Afterwards, we extended the currently on-board data specification executor to cope with the newly-formed packets. The use of UDP protocol presents challenges due to its intrinsic unreliability. Furthermore, the presence of a single Ethernet link per board, and the requirement for a dedicated processor to handle all Ethernet communications limit the available communication bandwidth. A set of simulations was performed in order to tune the protocol parameters and to study the trade-offs between transmission speed and reliability. We were able to reach a throughput of a packet every 250 mu s, which corresponds to a bandwidth of similar to 10 Mb/s. This system is able to open new perspectives for the SpiNNaker architecture. Thus, including the reduction of the time required to configure a simulation, the ability to configure more instances of a simulation. This system could even to enable the simulation of neurogenesis.

关键词： configuration many core neuromorphic spinnaker

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Developing an Expert system to Improve Lesion Quantification for Personalized PET Imaging

Developing an Expert System to Improve Lesion Quantification...

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ieee Nuclear Science symposium and Medical Imaging Conference (NSS/MIC) / 24th international symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Li, Yusheng Daube-Witherspoon, Margaret E. Matej, Samuel Metzler, Scott D. Univ Penn Dept Radiol 3620 Hamilton Walk Philadelphia PA 19104 USA

ISBN: (纸本)9781538622827

The measurements of lesion standardized uptake value (SUV) in clinical PET studies are affected in a complicated way by many aspects of the data, including-but not limited to-count level, lesion size, lesion shape, lesion location, background level and structure, and patient size. Optimized reconstruction algorithms and their parameters can provide substantial improvements in lesion quantification for personalized PET imaging. Full optimization of reconstruction parameters can be too complicated/tedious for human beings, thus we propose an expert system to optimize these parameters and to improve lesion quantification. Three core techniques are explored: 1) synthetic lesion embedding technique, 2) system local impulse response (LIR) modeling, and 3) bootstrapping for uncertainty estimation. We experimentally acquire list-mode data from physical radioactive spheres of known activity concentration with different sizes at different locations using the same PET scanner as was used for acquiring the patient data. We can then synthetically embed the spheres by merging the sphere list-mode data into patient data. We also use statistical bootstrapping method to generate multiple replicates of patient data with embedded lesions to determine the variance of the estimated SUV. We also use the LIR to characterize the local properties and responses of an imaging system, which can be used as a criterion for optimizing the reconstruction parameters. We have performed simulated phantom studies to confirm the use of bootstrapping of clinical data to determine the variance of SUV, and the use of LIR to determine the recovery coefficients and the bias of SUV of each lesion with different size. We are currently integrating the expert-system tools with a graphical user interface to allow the execution and visualization of ensembles of lesions with the use of different reconstruction algorithms and parameters. The end result will be patient- and lesion-specific corrected SUVs with estima

关键词： Terms Expert system lesion embedding local impulse response (LIR) image reconstruction positron emission tomography (PET)

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