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Why Comparing system-level MPSoC Mapping Approaches is Difficult: a Case Study 10

Why Comparing System-level MPSoC Mapping Approaches is Diffi...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Goens, Andres Khasanov, Robert Castrillon, Jeronimo Polstra, Simon Pimentel, Andy Tech Univ Dresden Chair Compiler Construct Ctr Adv Elect Dresden Cfaed Dresden Germany Univ Amsterdam Inst Informat Amsterdam Netherlands

ISBN: (纸本)9781509035311

Software abstractions are crucial to effectively program heterogeneous Multi-Processor systems on chip (MPSoCs). Prime examples of such abstractions are Kahn Process Networks (KPNs) and execution traces. When modeling computation as a KPN, one of the key challenges is to obtain a good mapping, i.e., an assignment of logical computation and communication to physical resources. In this paper we compare two system-level frameworks for solving the mapping problem: Sesame and MAPS. These frameworks, while superficially similar, embody different approaches. Sesame, motivated by modeling and design-space exploration, uses evolutionary algorithms for mapping. MAPS, being a compiler framework, uses simple and fast heuristics instead. In this work we highlight the value of common abstractions, such as KPNs and traces, as a vehicle to enable comparisons between large independent frameworks. These types of comparisons are fundamental for advancing research in the area. At the same time, we illustrate how the lack of formalized models at the hardware level are an obstacle to achieving fair comparisons. Additionally, using a set of applications from the embedded systems domain, we observe that genetic algorithms tend to outperform heuristics by a factor between 1x and 5x, with notable exceptions. This performance comes at the cost of a longer computation time, between 0 and 2 orders of magnitude in our experiments.

关键词： comparison design-space-exploration genetic algorithms heuristics KPN mapping MPSoC system-level

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Portable multicore Resource Management for Applications with Performance Constraints 10

Portable Multicore Resource Management for Applications with...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Imes, Connor Kim, David H. K. Maggio, Martina Hoffmann, Henry Univ Chicago Chicago IL 60637 USA Lund Univ Lund Sweden

ISBN: (纸本)9781509035311

many modern software applications have performance requirements, like mobile and embedded systems that must keep up with sensor data, or web services that must return results to users within an acceptable latency bound. For such applications, the goal is not to run as fast as possible, but to meet their performance requirements with minimal resource usage, the key resource in most systems being energy. Heuristic solutions have been proposed to minimize energy under a performance constraint, but recent studies show that these approaches are not portable - heuristics that are near-optimal on one system can waste integer factors of energy on others. The POET library and runtime system provides a portable method for resource management that achieves near-optimal energy consumption while meeting soft real-time constraints across a range of devices. Although POET was originally designed and tested on embedded and mobile platforms, in this paper we evaluate it on a manycore server-class system. The larger scale of manycore systems adds some overhead to adjusting resource allocations, but POET still meets timing constraints and achieves near-optimal energy consumption. We demonstrate that POET achieves portable energy efficiency on platforms ranging from low-power ARM big. LITTLE architectures to powerful x86 server-class systems.

关键词： Energy utilization

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A scalability analysis of many cores and on-chip mesh networks on the TILE-Gx platform 10

A scalability analysis of many cores and on-chip mesh networ...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Liu, Ye Sasaki, Hiroshi Kato, Shinpei Edahiro, Masato Nagoya Univ Grad Sch Informat Sci Nagoya Aichi Japan Columbia Univ Dept Comp Sci New York NY 10027 USA Nagoya Univ Inst Innovat Future Soc Nagoya Aichi 4648601 Japan Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan

ISBN: (纸本)9781509035311

TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing manycore processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor. We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the twodimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.

关键词： Scalability many core Mesh Network TILE-Gx platform

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The CASE tool for programming of the multi-core system-on-a-chip with the data flow computation control

The CASE tool for programming of the multi-core System-on-a-...

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international symposium on Applied Machine Intelligence and Informatics (SAMI)

作者： Branislav Madoš Norbert Ádám Anton Baláž Katarína Šinaľová Department of Computers and Informatics Technical University of Kosice Kosice Slovak Republic

The paper describes Computer Aided Software Engineering (CASE) tool, that supports programming of the experimental multi-core tile based system-on-a-chip (SoC). SoC comprises cores, which are based on the data flow computation control principle. Proposed CASE tool allows creation of the program code in graphical form using Data Flow Graph (DFG) or in text representation using assembly language or machine code. Automatic transformations between those representations are supported. CASE tool brings sequential, mask based and global multi-mapping of the program code, which was introduced in our previous research. Another output lies in introduction of altered assembly language and machine code that allow multi-mapping of the program code on the instructions level. The aim of the solution lies in optimization of the program load phase in multi-core microprocessors that comprise tens or potentially hundreds of cores.

关键词： Computer aided software engineering multicore processing Flow graphs Ports (Computers) system-on-chip Informatics

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On constructing cost models for online automatic tuning using ATMathcoreLib: Case studies through the SVD computation on a multicore processor 10

On constructing cost models for online automatic tuning usin...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Nagashima, Seiji Fukaya, Takeshi Yamamoto, Yusaku Kobe Univ Dept Computat Sci Nada Ku 1-1 Rokkodai Kobe Hyogo 6578501 Japan Hokkaido Univ Informat Initiat Ctr JST CREST Kita Ku W5N11 Sapporo Hokkaido 0600811 Japan Univ Electrocommun JST CREST Dept Commun Engn & Informat 1-5-1 Chofugaoka Chofu Tokyo 1828585 Japan

ISBN: (纸本)9781509035311

We consider the problem of online automatic tuning. In this setting, we execute the target program with some tuning parameters N times, where N is given, while optimizing the parameters to minimize some objective function such as the total execution time. Thus we have to choose the parameters for each execution by taking into account the trade-off between exploration and exploitation. The ATMathcoreLib library developed by Suda is a set of software that solves this problem. To model the performance of the target software, ATMathcoreLib uses a linear statistical model, and its basis functions must be provided by the user. In this paper, we investigate how to choose the basis functions appropriately, using the singular value decomposition of a square matrix as an example. We consider three cases, namely, (I) when the performance characteristics of the target problem are well understood by the user, (II) when the tuning parameter has a complicated structure, as occurs in the case of simultaneous selection of an algorithm and its parameter, and (III) when the performance characteristics of the target problem are not known to the user. The results of using ATMathcoreLib with different basis functions for each case are given. They help one understand the tuning by ATMathcoreLib and contribute to the progress of ATMathcoreLib.

关键词： ATMathcoreLib online automatictuning singular value decomposition statistics

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Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for multicore Processor system 10

Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2016

作者： Ooi, Joo On Hussin, Fawnizu Azmadi B. Zakaria, Nordin Dept.of Computer and Communication Technology Universiti Tunku Abdul Rahman Bandar Barat Kampar Perak Malaysia Department of Electrical and Electronics Engineering Universiti Teknologi Petronas Bandar Seri Iskandar Perak Malaysia Department of Computer and Information Sciences Universiti Teknologi Petronas Bandar Seri Iskandar Perak Malaysia

ISBN: (纸本)9781509035304

The emergence of new era of Internet of Things or IoT have encouraged intensive if not extensive usage of modern mobile apps, thus multi-ISA equipped multicore processor gain great potential to be used for more efficient instruction binary processing in near future. In order to support this ISA diversity of computing platforms, mix modes of statically and dynamically Binary Translation and Optimization system, popularly consists of QEMU and LLVM or similar system, is the default technique used. However this complex system exhibits heavy slowdown (60x slowdown as compare to generic QEMU) [21] which impede its performance especially for short running application codes, typically used in IoT based apps applications. This research introduce a dual binary code translation engines to support apps based and kernel based application codes, through utilising multithreaded supported apart of original single thread supported binary translation processing in run-time. The dual engine consists of TCG generator from QEMU, and LLVM which include rich optimisations library. The evaluation through PARSEC-3.0 Benchmark shows our Hybrid DBTO system achieved performance improvement approaching 2.0x for apps based programs and 1.25x for kernel based programs, for x86 to X86-64 emulation. This technique possess great potential and serve as research based platform for future binary translation technique development, including adaptive method. © 2016 ieee.

关键词： Engines

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Determining the Communication Load for Self-Building embedded systems Based on Artificial DNA

Determining the Communication Load for Self-Building Embedde...

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international symposium on Object-Oriented Real-Time Distributed Computing

作者： Uwe Brinkschulte Institut für Informatik Johann Wolfgang Goethe Universität Frankfurt Germany

ISBN: (纸本)9781538615751

embedded systems are growing more and more complex because of the increasing chip integration density, larger number of chips in distributed applications and demanding application fields (e.g. in cars and in households). Bio-inspired techniques like self-organization are a key feature to handle this complexity. The self-organization process needs a guideline for setting up and managing the system. In biology the structure and organization of a system is coded in its DNA. This concept can be adapted to embedded systems. Since many embedded systems can be composed from a limited number of basic elements, the structure and parameters of such systems can be stored in a compact way representing an artificial DNA deposited in each processor core. Based on the DNA, the self-organization mechanisms can build the system autonomously providing a self-building system. system repair and optimization at runtime are also possible, leading to higher robustness, dependability and flexibility. However, these properties introduce a certain amount of communication load. In this paper we determine the communication load and conduct an evaluation using a flexible DNA-controlled robot vehicle.

关键词： DNA embedded systems Sensors Real-time systems Organizations Biochemistry

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Accelerating Graph and Machine Learning Workloads Using a Shared Memory multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging

Accelerating Graph and Machine Learning Workloads Using a Sh...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： Halit Dogan Farrukh Hijaz Masab Ahmad Brian Kahne Peter Wilson Omer Khan University of Connecticut Storrs CT USA NXP Semiconductors Austin TX USA

Shared Memory stands out as a sine qua non for parallel programming of many commercial and emerging multicore processors. It optimizes patterns of communication that benefit common programming styles. As parallel programming is now mainstream, those common programming styles are challenged with emerging applications that communicate often and involve large amount of data. Such applications include graph analytics and machine learning, and this paper focuses on these domains. We retain the shared memory model and introduce a set of lightweight in-hardware explicit messaging instructions in the instruction set architecture (ISA). A set of auxiliary communication models are proposed that utilize explicit messages to accelerate synchronization primitives, and efficiently move computation towards data. The results on a 256-core simulated multicore demonstrate that the proposed communication models improve performance and dynamic energy by an average of 4× and 42% respectively over traditional shared memory.

关键词： Message systems system recovery Computer architecture Synchronization Protocols Pipelines Radiation detectors

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Analysis of Adaptive Mapping of Parallelized Application on multicore system. 30

Analysis of Adaptive Mapping of Parallelized Application on ...

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30th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Bizot, Gilles Avreskyt, Dimiter Chaix, Fabien UJF CNRS INP TIMA Lab Grenoble France IRIANC Boston MA USA

ISBN: (纸本)9781509036820

In previous publications, a self-recovering strategy ([1]), which is able to "re-map" dynamically application tasks on a multi-core system, was presented. Based on run-time failure aware techniques, this Self-Recovering strategy guarantees seamlessly termination and delivering the expected results, despite multiple node and link failures in a 2D mesh topology chip. Its efficiency has already been shown for several scenario (computation, communication time) in [2]. In this article, new experiments with a more realistic NoC models (i.e. a NoC with a only port, four ports, multicast) are given. A Motion JPEG-2000 application is used as a case study to analyze the impact of real NoC models on our self-recovering strategy. The results shown, as expected, a deterioration in term of performance at very low computation-to-communication ratio (CCR), mainly due to the NoC bottleneck. Furthermore, different scenario are applied to enhancement the overall speedup and compared all together.

关键词： Self-Recovering Multi-core chip Seamless Execution Parallel Streaming Application Adaptive Fault-Tolerant Routing

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A heterogeneous time-triggered architecture on a hybrid system-on-a-chip platform 25

A heterogeneous time-triggered architecture on a hybrid syst...

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25th ieee international symposium on Industrial Electronics (ISIE)

作者： Isakovic, Haris Grosu, Radu Vienna Univ Technol Inst Comp Engn Vienna Austria

ISBN: (纸本)9781509008735

There is a huge discrepancy between off-the-shelf (COTS) hardware architectures and requirements for embedded industrial applications. Industrial systems are getting more complex by the day, and an interaction of highly diverse components within these systems is unavoidable. An implementation of such systems on COTS hardware is challenging. Platforms based on single-core CPUs is becoming limited, and use of multi-core architectures yields safety risks, and overall inefficiency. Tailored architectures provide adequate service but they lack flexibility and therefore their economic justification is limited. Emerging technologies i.e., hybrid system-on-chip combined with novel architectural concepts are filling blind spots between COTS architectures and embedded industrial applications. The paper presents the implementation of an MPSoC architecture on a hybrid system-on-a-chip platform. This architecture provides unique capabilities for embedded applications, in particular, the possibility to host mixed-criticiality and cross-domain applications.

关键词： Hybrid systems

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