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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是461-470 订阅

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On-the-Fly Load Data Value Tracing in multicores

On-the-Fly Load Data Value Tracing in Multicores

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international Conference on Compliers, Architectures, and Synthesis of embedded systems (CASES)

作者： Ponugoti, Mounika Tewar, Amrish K. Milenkovic, Aleksandar Univ Alabama Dept Elect & Comp Engn 301 Sparkman Dr Huntsville AL 35899 USA

ISBN: (纸本)9781450344821

Software testing and debugging of modern multicore-based embedded systems is a challenging proposition because of growing hardware and software complexity, increased integration, and tightening time-to-market. To find more bugs faster, software developers of real-time embedded systems increasingly rely on on-chip trace and debug resources, including hefty on-chip buffers and wide trace ports. However, these resources often offer limited visibility of the system, increase the system cost, and do not scale well with a growing number of cores. This paper introduces mlvCFiat, a hardware/software mechanism for capturing and filtering load data value traces in multicores. It relies on first access tracking in data caches and equivalent modules in the software debugger to significantly reduce the number of trace events streamed out of the target platform. Our experimental evaluation explores the effectiveness of the proposed technique as a function of cache sizes, encoding mechanism, and the number of cores. The results show that mlvCFiat significantly reduces the total trace port bandwidth. The improvements relative to the existing Nexus-like load data value tracing range from 15 to 33 times for a single core and from 14 to 20 times for an octa core.

关键词： Real-time embedded systems multicores Software testing and debugging Program Tracing

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Message from the ieee MCSoC-16 General Chair and Steering Committee Chair

Proceedings - IEEE 10th International Symposium on Embedded ...

引用

Proceedings - ieee 10th international symposium on embedded multicore/many-core systems-on-chip, MCSoC 2016 2016年 x页

作者： Le Beux, Sébastien Ben Abdallah, Abderazek

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Message from the ieee MCSoC-16 General Chair and Steering Committee Chair

Message from the IEEE MCSoC-16 General Chair and Steering Co...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.

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Migrating a Bare PC Web Server to a Multi-core Architecture 40

Migrating a Bare PC Web Server to a Multi-core Architecture

引用

40th Annual ieee Computer Software and Applications Conference symposium (COMPSAC) / symposium on Software Engineering Technology and Applications (SETA)

作者： Chang, Hojin Karne, Ramesh Wijesinha, Alexander Towson Univ Dept Comp & Informat Sci Towson MD 21252 USA

ISBN: (纸本)9781467388450

Bare PC applications run without the support of any OS, kernel, or embedded software. many bare PC applications such as Web servers, mail servers, SIP servers and VoIP clients have been developed previously for the x86 Intel architecture. We migrate a bare PC Web server application enabling it to run on a 64-bit multicore desktop processor. Migration poses many challenges as this application runs on a bare PC. The 64bit CPU architecture is significantly different from its 32-bit counterpart, making migration non-trivial. First, an attempt was made to run the existing code as is on the 64-bit processor without using any 64-bit CPU architectural features. Second, paging required by the 64-bit architecture was implemented. This requires many design changes to deal with paging and virtual memory issues since the Web server application is based on real memory without any paging. Finally, multitasked execution of the Web server on multicore is undertaken. This phase of migration is complex due to the complexity in 64 bit architecture and its intricacies. We give technical details underlying the migration process and present results of testing functional operations with some preliminary data to validate this approach.

关键词： Bare Machine Computing Bare PC Intel x86 Multi-core 64-bit architecture Web server

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Prototypic Implementation and Evaluation of an Artificial DNA for Self-Descripting and Self-Building embedded systems 19

Prototypic Implementation and Evaluation of an Artificial DN...

引用

19th ieee international symposium on Real-Time Distributed Computing (ISORC)

作者： Brinkschulte, Uwe Goethe Univ Frankfurt Inst Informat Frankfurt Germany

ISBN: (纸本)9781467390323

embedded systems are growing more and more complex because of the increasing chip integration density, larger number of chips in distributed applications and demanding application fields (e.g. in cars and in households). Bio-inspired techniques like self-organization are a key feature to handle this complexity. However, self-organization needs a guideline for setting up and managing the system. In biology the structure and organization of a system is coded in its DNA. In this paper we present an approach to use an artificial DNA for that purpose. Since many embedded systems can be composed from a limited number of basic elements, the structure and parameters of such systems can be stored in a compact way representing an artificial DNA deposited in each processor core. This leads to a self-describing system. Based on the DNA, the self-organization mechanisms can build the system autonomously providing a self-building system. system repair and optimization at runtime are also possible, leading to higher robustness, dependability and flexibility. We present a prototypic implementation and conduct a real-time evaluation using a flexible robot vehicle. Depending on the DNA, this vehicle acts as a self-balancing vehicle, an autonomous guided vehicle, a follower or a combination of these.

关键词： Artificial DNA prototypic implementation evaluation real-time self-organization self-building self-description

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LinROS: A Linux-based Runtime system for Reconfigurable MPSoCs 30

LinROS: A Linux-based Runtime System for Reconfigurable MPSo...

引用

30th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Rettkowski, Jens Wehner, Philipp Cutiscev, Evgheni Goehringer, Diana Ruhr Univ Bochum Applicat Specif Multicore Architectures MCA Grp Bochum Germany

ISBN: (纸本)9781509036820

Modern FPGA-based Multiprocessor systems-on-chip (MPSoCs) support dynamic reconfiguration of processing elements (PEs) such as processors and accelerators. The reconfiguration improves the flexibility of the system due to the dynamic and partial exchange of PEs. However, the design of reconfigurable MPSoCs leads also to higher complexity in programming due to the huge design space. To bridge this gap, this paper presents a runtime system consisting of a software layer called LinROS. It dynamically schedules and reconfigures PEs. LinROS uses a novel Linux device driver that automatically manages the software and hardware of the reconfigurable MPSoC at runtime. In addition, an IP core developed for LinROS facilitates an easy hardware integration of PEs using High-Level-Synthesis tools such as VivadoHLS. Data exchange between PEs is managed by the IP core. The entire system is evaluated on a Xilinx Zynq SoC performing image processing algorithms. The results show a negligible overhead of the scheduling while the programming of reconfigurable MPSoCs is significantly simplified by the device driver. Furthermore, the hardware design of PEs is also simplified due to the High-Level Synthesis.

关键词： Reconfigurable MPSoCs Zynq Vivado HLS Runtime system Dynamic and Partial Reconfiguration Linux Device Driver

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core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs 22

Core Tunneling: Variation-Aware Voltage Noise Mitigation in ...

引用

22nd ieee international symposium on High-Performance Computer Architecture (HPCA)

作者： Thomas, Renji Barber, Kristin Sedaghati, Naser Zhou, Li Teodorescu, Radu Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9781467392112

Voltage noise and manufacturing process variation represent significant reliability challenges for modern microprocessors. Voltage noise is caused by rapid changes in processor activity that can lead to timing violations and errors. Process variation is caused by manufacturing challenges in low-nanometer technologies and can lead to significant heterogeneity in performance and reliability across the chip. To ensure correct execution under worst-case conditions, chip designers generally add operating margins that are often unnecessarily conservative for most use cases, which results in wasted energy. This paper investigates the combined effects of process variation and voltage noise on modern GPU architectures. A distributed power delivery and process variation model at functional unit granularity was developed and used to simulate supply voltage behavior in a multicore GPU system. We observed that, just like in CPUs, large changes in power demand can lead to significant voltage droops. We also note that process variation makes some cores much more vulnerable to noise than others in the same GPU. Therefore, protecting the chip against large voltage droops by using fixed and uniform voltage guardbands is costly and inefficient. This paper presents core tunneling, a variation-aware solution for dynamically reducing voltage margins. The system relies on hardware critical path monitors to detect voltage noise conditions and quickly reacts by clock-gating vulnerable cores to prevent timing violations. This allows a substantial reduction in voltage margins. Since clock gating is enabled infrequently and only on the most vulnerable cores, the performance impact of core tunneling is very low. On average, core tunneling reduces energy consumption by 15%.

关键词： Program processors

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Programming Models and Methods for Heterogeneous Parallel embedded systems

Programming Models and Methods for Heterogeneous Parallel Em...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Simone Casale-Brunet Endri Bezati Marco Mattavelli EPFL SCI STI MM École Polytechnique Federale de Lausanne Switzerland

ISBN: (纸本)9781509035328

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded processors. Past research works have shown that raising the level of abstraction of design stages does not necessarily come at penalties in results in terms of performance or resource requirements. Dataflow programs provide a high-level behavioral descriptions capable of expressing both sequential and parallel components of application algorithms and enable natural design abstractions, modularity, and portability. This paper presents an overview of the main features, recent achievements and results of a design-flow, entirely dataflow based, and the associated tools capable of implementing and optimizing complex signal processing system applications on heterogeneous and massive parallel embedded systems.

关键词： Programming Computational modeling Unified modeling language Computer architecture system analysis and design Hardware Software

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Full-system Simulation of *** multicore Architecture for Performance and Energy Exploration

Full-System Simulation of *** Multicore Architecture for Per...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Anastasiia Butko Florent Bruguier Abdoulaye Gamatié Gilles Sassatelli David Novo Lionel Torres Michel Robert Gilles Sassatelli University of Montpellier Montpellier France Communaute d'Universites et Etablissements Languedoc-Roussillon Universites Montpellier Languedoc-Roussillon FR

ISBN: (纸本)9781509035328

Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM ***. These processors offer increased energy efficiency through combining low power in-order cores with high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so as to meet the demands of targeted applications. In this paper, we explore the design of those architectures based on the ARM *** technology by modeling performance and power in gem5 and McPAT frameworks. Our models are validated w.r.t. the Samsung Exynos 5 Octa (5422) chip. We show average errors of 20% in execution time, 13% for power consumption and 24% for energy-to-solution.

关键词： multicore processing Computational modeling Program processors Random access memory Linux Kernel

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Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality systems

Time-Triggered and Rate-Constrained On-chip Communication in...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Hamidreza Ahmadian Roman Obermaisser Mohammed Abuteir University of Siegen Germany

ISBN: (纸本)9781509035328

The ongoing trend to integrate multiple functions with different criticalities on a single platform calls for a robust on-chip communication infrastructure in which subsystems of different criticalities can coexist and interact. A fundamental prerequisite for such a platform is to eliminate any interference between safety-critical functions and non safety-critical ones. Furthermore, as mixed-criticality systems often comprise heterogeneous subsystems, the platform shall support different timing models (e.g., periodic and sporadic activities). This paper introduces an extension layer for the Network Interface (NI) of a network-on-a-chip in order to establish temporal and spatial partitioning over the entire chip. We describe how chip-wide segregation between different subsystems assures the absence of interference for time-triggered messages and bounded latencies for rate-constrained messages. The configuration of the NIs establishes guarding windows for time-triggered messages and traffic shaping of rate-constrained messages.

关键词： system-on-chip Ports (Computers) Hardware Nickel Real-time systems Interference Schedules

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