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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是471-480 订阅

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Heuristic Based Routing Algorithm for Network on chip

Heuristic Based Routing Algorithm for Network on Chip

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Asma Benmessaoud Gabis Marc Sevaux Pierre Bomel Mouloud Koudil Karima Benatchba Université Bretagne-Sud Lab-STICC France École nationale Supérieure d'Informatique LMCS Algeria

ISBN: (纸本)9781509035328

Deadlocks, livelock, congestion and faults are the four most important factors that reduce the NoC routing efficiency [1]. This paper proposes a new fully adaptive routing protocol for 2D-mesh NoC. It is inspired from the A-star search algorithm and called HRA (Heuristic based Routing Algorithm). The latter is distributed, congestion-aware and fault-tolerant by using only the local information of each router neighbors. HRA does not use VCs (Virtual Channels) but tries to reduce the risk of deadlock by avoiding the 2-nodes and the 4-nodes loops. Results show that HRA ensures a good reliability rate despite of the presence of many faulty links. In addition, it has interesting latencies values in different NoC sizes.

关键词： system recovery Routing Heuristic algorithms Routing protocols Fault tolerance Fault tolerant systems Topology

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Supporting Static Binding in Stream Rewriting for Heterogeneous many-core Architectures

Supporting Static Binding in Stream Rewriting for Heterogene...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Lars Middendorf Christian Haubelt University of Rostock Germany

ISBN: (纸本)9781509035328

Heterogeneous multi and many-core systems offer numerous benefits like reduced energy consumption and improved throughput for both high-performance and low-power applications. However, beside the design of the actual hardware architecture, also the programming of many-core systems raises several challenges. For this purpose, we extend the existing concept of stream rewriting into a model of computation for the specification of highly concurrent applications on heterogeneous systems. In particular, our approach permits to partition the stream and to bind different sections to specialized hardware components. Since stream rewriting manages a large number of active tasks without a central scheduler, we can perform the distribution and synchronization of work-items asynchronously to improve hardware utilization. Several case studies using an FPGA prototype demonstrate the scalability of our approach.

关键词： Hardware Pipelines Rendering (computer graphics) Computer architecture Graphics processing units Synchronization

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Portable multicore Resource Management for Applications with Performance Constraints

Portable Multicore Resource Management for Applications with...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Connor Imes David H. K. Kim Martina Maggio Henry Hoffmann University of Chicago Lund University

ISBN: (纸本)9781509035328

many modern software applications have performance requirements, like mobile and embedded systems that must keep up with sensor data, or web services that must return results to users within an acceptable latency bound. For such applications, the goal is not to run as fast as possible, but to meet their performance requirements with minimal resource usage, the key resource in most systems being energy. Heuristic solutions have been proposed to minimize energy under a performance constraint, but recent studies show that these approaches are not portable - heuristics that are near-optimal on one system can waste integer factors of energy on others. The POET library and runtime system provides a portable method for resource management that achieves near-optimal energy consumption while meeting soft real-time constraints across a range of devices. Although POET was originally designed and tested on embedded and mobile platforms, in this paper we evaluate it on a manycore server-class system. The larger scale of manycore systems adds some overhead to adjusting resource allocations, but POET still meets timing constraints and achieves near-optimal energy consumption. We demonstrate that POET achieves portable energy efficiency on platforms ranging from low-power ARM *** architectures to powerful x86 server-class systems.

关键词： Software multicore processing Resource management Timing Runtime Data structures Energy consumption

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A Scalability Analysis of many cores and On-chip Mesh Networks on the TILE-Gx Platform

A Scalability Analysis of Many Cores and On-Chip Mesh Networ...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Ye Liu Hiroshi Sasaki Shinpei Kato Masato Edahiro Graduate School of Information Science Nagoya University Nagoya Japan Department of Computer Science Columbia University New York USA Institute of Innovation for Future Society Nagoya University Nagoya Japan Graduate School of Information Science and Technology The University of Tokyo Tokyo Japan

ISBN: (纸本)9781509035328

TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing many-core processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor. We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the two-dimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.

关键词： Program processors Mesh networks Scalability system-on-chip Computer architecture Benchmark testing Linux

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A Data Locality and Memory Contention Analysis Method in embedded NUMA Multi-core systems

A Data Locality and Memory Contention Analysis Method in Emb...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Lin Li Markus Fussenegger Gordon Cichon Infineon Technologies AG LMU Munich

ISBN: (纸本)9781509035328

Data locality in distributed memories has a significant performance impact on NUMA multi-core systems owing to non-uniform memory accesses. In addition, memory contention also influences the performance of multi-core systems. The performance degradation caused by both effects should be analyzed before performance optimization because data locality and memory contention are mutually dependent. A reduction of one effect could cancel performance gains due to another effect. A novel post-processing method based on non-intrusive tracing is proposed in this paper to analyze the performance impact incurred by both data locality and memory contention in a quantitative, comparable way. It makes use of non-intrusive tracing, which has no impact on normal execution and timing. The analysis provides results including data locality and memory contention penalties, which can be used as a reference to improve performance.

关键词： embedded systems Hardware multicore processing Optimization Resource management Electronic mail

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A Benes Based NoC Switching Architecture for Mixed Criticality embedded systems

A Benes Based NoC Switching Architecture for Mixed Criticali...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Steve Kerrison David May Kerstin Eder Department of Computer Science University of Bristol Bristol United Kingdom

ISBN: (纸本)9781509035328

Multi-core, Mixed Criticality embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect becomes a potential point of uncertainty, introducing major challenges in proving behaviour is always within specified constraints, limiting the means of growing system performance to add more tasks, or provide more computational resources to existing tasks. We present MCENoC, a Network-on-chip (NoC) switching architecture that provides innovations to overcome this with predictable, formally verifiable timing behaviour that is consistent across the whole NoC. We show how the fundamental properties of Benes networks benefit MCE applications and meet our architecture requirements. Using systemVerilog Assertions (SVA), formal properties are defined that aid the refinement of the specification of the design as well as enabling the implementation to be exhaustively formally verified. We demonstrate the performance of the design in terms of size, throughput and predictability, and discuss the application level considerations needed to exploit this architecture.

关键词： Switches Computer architecture Safety Timing Hardware Real-time systems Routing

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A Robust Methodology for Performance Analysis on Hybrid embedded multicore Architectures

A Robust Methodology for Performance Analysis on Hybrid Embe...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Romain Saussard Boubker Bouzid Marius Vasiliu Roger Reynaud Renault S.A.S Guyancourt France SATIE Université Paris Saclay Orsay France

ISBN: (纸本)9781509035328

Today's vehicles increasingly embed software intelligence in order to be safer for the driver, and to achieve autonomous driving in a close future. To answer the computational needs of these algorithms, system-on-chip (SoC) suppliers propose heterogeneous architectures. With such complex SoCs, embedding applications in vehicle becomes more and more complex for car manufacturers. Indeed, it is not trivial to find the best suited SoC for a given application, and to define load balancing strategies when working with heterogeneous architectures. These difficulties can be overcome by using performance prediction, based on computing architectures models. To build these models, we provide a set of test vectors which automatically extract key characteristics of tested architectures. Our methodology is able to perform a complete computing architecture model, by using 3 different levels of tests, each one characterizing a specific situation representative of real applications. We aim to obtain performance prediction for different applications, for any embedded SoCs based on models performed with this methodology. In this paper, we describe our characterization methodology, and show results obtained with embedded SoCs used for automotive applications.

关键词： Computer architecture Kernel Graphics processing units Benchmark testing Image processing Vehicles

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A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks

A Task Allocation Method for the DTTR Scheme Based on the Pa...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Hiroshi Saito Masashi Imai Tomohiro Yoneda The University of Aizu Japan Hirosaki University Japan National Institute of Informatics Japan

ISBN: (纸本)9781509035328

In this paper, we propose a task allocation method for multi-core systems with the Duplication with Temporary Triple Modular Redundancy and Reconfiguration (DTTR) scheme. The proposed method optimizes both performance and reliability by allocating copies of tasks (i.e., redundant tasks) based on the maximum parallelism of tasks in a give application. In the experimental results, we compare the average failure rate of task allocations obtained by the proposed method with the one obtained by a scheduling-based task allocation method and the one obtained by a task allocation method based on Simulated Annealing. The proposed method realizes both high performance and high reliability in the cases when enough cores to maximize parallel execution of tasks exist.

关键词： multicore processing Resource management Tunneling magnetoresistance Parallel processing Redundancy Time factors

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Vivado HLS-based Implementation of a Fall Detection Decision core on an FPGA platform 11

Vivado HLS-based Implementation of a Fall Detection Decision...

引用

11th international Design and Test symposium (IDT)

作者： Abdelhedi, Sahar Baklouti, Mouna Bourguiba, Riad Mouine, Jaouhar Univ Tunis El Manar Ecole Natl Ingenieurs Tunis Lab Anal Concept & Commande Syst LR11ES20 1002 Tunis 1002 Tunisia TELNET Grp TELNET Innovat Labs Parc Technol El Ghazala Tunis Tunisia Prince Sattam Bin Abdulaziz Univ Dept Elect Engn Al Kharj Saudi Arabia

ISBN: (纸本)9781509049004

New ultra-low power FPGAs provide system designers the flexibility to create completely customizable low power solutions to bring new classes of applications to life. Fall detection is one of the major problems the elderly population is facing. This paper aims to present the design of an heterogeneous wearable system built with Zynq system-On-chip (SoC) for fall detection. The design has been validated on ARM A9 processor for the software side and using Vivado High Level Synthesis (HLS) for hardware implementation on a Zynq-7010 SoC. The implementation results of the fall detection core showed less power consumed and 50% less on-chip logic resources used compared to the software implementation.

关键词： e-health embedded systems fall detection FPGA Vivado HLS

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Network on chip and Parallel Computing in embedded systems

Network on Chip and Parallel Computing in Embedded Systems

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Dihia Belkacemi Youcef Bouchebaba Mehammed Daoui Mustapha Lalam Laboratoire de Recherche en Informatique Université de Tizi-Ouzou Algeria ONERA-Toulouse France

ISBN: (纸本)9781509035328

In order to cope with the increasing application requirements, heterogeneous MPSoC are considered as the major solution of future embedded systems thanks to their advantages in performance and low power dissipation. However traditional communication infrastructure such as a bus or a point to point are not scalable and become communication bottleneck for large systems. Network on chip (NoC) architectures have been proposed to handle this communication problem. One of the most critical problem in NoC based heterogeneous MPSoC is how to map an application on this platform. Due to the large solution search space, design of tools that can automate this step is of major importance. In this paper, we present a new tool for mapping applications on NoC based heterogeneous MPSoC. A set of multi-objective optimization algorithms are used to explore the mapping space and to find a set of Pareto optimal solutions.

关键词： Program processors Cost function Energy consumption Memory management Encoding

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