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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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A Dual-core FPGA-based embedded system Development Platform

A Dual-core FPGA-based Embedded System Development Platform

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3rd international symposium on Computer, Consumer and Control (IS3C)

作者： Huang, Chun-Ming Yang, Chih-Chyau Wu, Chien-Ming Chen, Chun-Yu Cheng, Chun-Wen Liu, Yi-Jun Natl Chip Implementat Ctr Natl Appl Res Labs Hsinchu 300 Taiwan

ISBN: (纸本)9781509030712

A dual-core FPGA-based embedded system development platform named MorFPGA Duo is presented in this paper. The MorFPGA Duo platform adopts the modular design concept and is capable of a dual core employing the ARM Cortex A9, two channel SDI cameras with Full-HD resolution, versatile built-in peripherals and high expandability to satisfy users' eager needs for state-of-the-art research topics. This platform consists of two boards: The core modular board mainly includes a dual core Zynq and versatile peripherals, while the multimedia modular board supports the two-channel video sources with SDI interface to support 3D video applications. With the standardized PMOD and FMC connectors, the various kinds of daughter boards are enabled to integrate into MorFPGA Duo system. The MediaWiki online forum is adopted to deliver users the latest lab materials. The design flow and two system design examples are presented to show the MorFPGA Duo is workable. One design example introduces how the software and hardware design can be integrated and demonstrated in this platform, while the other example shows the duo SDI cameras for 3D video applications.

关键词： MorFPGA MorFPGA Duo SoC FPGA All-programmable SoC

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Accelerating multicore Architecture Simulation Using Application Profile

Accelerating Multicore Architecture Simulation Using Applica...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Keiji Kimura Gakuho Taguchi Hironori Kasahara Department of Computer Science and Engineering Waseda University Tokyo Japan

ISBN: (纸本)9781509035328

Architecture simulators play an important role in exploring frontiers in the early stages of the architecture design. However, the execution time of simulators increases with an increase the number of cores. The sampling simulation technique that was originally proposed to simulate single-core processors is a promising approach to reduce simulation time. Two main hurdles for multi/many-core are preparing sampling points and thread skewing at functional simulation time. This paper proposes a very simple and low-error sampling-based acceleration technique for multi/many-core simulators. For a parallelized application, an iteration of a large loop including a parallelizable program part, is defined as a sampling unit. We apply X-means method to a profile result of the collection of iterations derived from a real machine to form clusters of those iterations. Multiple iterations are exploited as sampling points from these clusters. We execute the simulation along the sampling points and calculate the number of total execution cycles. Results from a 16-core simulation show that our proposed simulation technique gives us a maximum of 443x speedup with a 0.52% error and 218x speedup with 1.50% error on an average.

关键词： Computational modeling Computer architecture Mathematical model Transform coding Clocks Instruction sets

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Faster Method for Tuning the Tile Size for Tile Matrix Decomposition

Faster Method for Tuning the Tile Size for Tile Matrix Decom...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Tomohiro Suzuki Department of Interdisciplinary Research University of Yamanashi Yamanashi Japan

ISBN: (纸本)9781509035328

Matrices are frequently decomposed in various ways in order to meet the conditions of an application, and therefore, algorithms for doing this are very important in the field of numerical linear algebra. In the tile algorithm, it is very critical to find a tile size that is suitable for the size of the matrix and the run-time environment. Smaller tiles can generate many fine-grained tasks. This can resolve load imbalances, but it causes a decline in the performance of the level three Basic Linear Algebra Subprograms (L3 BLAS) because L3 BLAS routines show higher performance with a larger size of data. Agullo et al. presented a pruned search routine for determining the size of the tile and the width of the inner blocks for tile matrix decomposition routines. To further reduce the parameter search time, we reduce the candidates by considering the number of tasks, which varies with the tile size.

关键词： Matrix decomposition Kernel Plasmas multicore processing Libraries Tuning

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Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor

Optimizing Latencies and Customizing NoC of Time-Predictable...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Zoran Salcic Muhammad Nadeem Heejong Park Juergen Teich Department of Electrical and Computer Engineering University of Auckland New Zealand Department of Computer Science Friedrich-Alexander University Erlangen Germany

ISBN: (纸本)9781509035328

The Time-Predictable Heterogeneous multicore Processor (TP-HMP) is based on a NoC and fully implemented in a standard FPGA chip. The NoC uses TDMA-MIN interconnect with bounded latency, high throughput and low implementation cost. TP-HMP is used for execution of programs written in concurrent GALS language systemJ suited for both soft and hard real-time systems. It uses two types of cores in different configurations and is suitable for static analysis of schedules that implement the program control flow and concurrency. The configuration and number of cores of both types used to achieve specific performance measures can be tailored/optimized for a given application. In this paper we focus on optimization of latency of TDMA-MIN NoC, which also results in mapping of processor cores on physical ports of NoC and optimal TDMA round. We also analyze the performance of TP-HMP execution of the benchmark program used in industrial automation case study.

关键词： Nickel Real-time systems Time division multiple access Schedules Ports (Computers) multicore processing Clocks

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The Role of Self-Awareness and Hierarchical Agents in Resource Management for many-core systems

The Role of Self-Awareness and Hierarchical Agents in Resour...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Maximilian Götzinger Amir M. Rahmani Martin Pongratz Pasi Liljeberg Axel Jantsch Hannu Tenhunen Department of Information Technology University of Turku Finland Institute of Computer Technology Wien TU Austria

The future of Moore's Law is in jeopardy. The number of cores of many-core systems is steadily increasing for every technology node generation. Voltage scaling does not keep pace with the unabated decrease of transistor size. Higher leakage power and manufacturing variabilities are the consequences and lead to extremely critical power as well as thermal issues. These phenomena can downgrade the performance or endanger system's functionality as well as its reliability if they are not properly addressed. In near future, up to 90% of a many-core chip's area may have to remain inactive, this non-active area is termed Dark Silicon. These issues make the problem of resource management challenging. Future management systems need to be intelligent, anticipatory, and self-adaptive. They are supposed to integrate management of different aspects such as thermal, power, energy, performance, quality of service, process variability, occurrence of faults and aging effects, all in one. In this paper, we study the contributions in the literature focusing on techniques for dynamic resource management in multi-and many-core systems. We put emphasis on advanced approaches that exhibit learning, self-awareness, hierarchical monitoring and management. We categorize the existing approaches from a new perspective and argue that a self-aware hierarchical agent-based model is a proper methodology to monitor and management many-core systems, in particular when they need to deal with different competing goals. In addition, we evaluate the main objectives and trends in resource management of many-core systems in order to pave the way for designing future computer systems ranging from high-performance computers to embedded processors used in the era of Internet-of-Things.

关键词： Resource management Power demand Clocks Computers Reliability Dynamic scheduling Transistors

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Why Comparing system-Level MPSoC Mapping Approaches is Difficult: A Case Study

Why Comparing System-Level MPSoC Mapping Approaches is Diffi...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Andres Goens Robert Khasanov Jeronimo Castrillon Simon Polstra Andy Pimentel Chair for Compiler Construction Center for Advancing Electronics Dresden (cfaed) Dresden Germany Informatics Institute University of Amsterdam Amsterdam Netherlands

ISBN: (纸本)9781509035328

Software abstractions are crucial to effectively program heterogeneous Multi-Processor systems on chip (MPSoCs). Prime examples of such abstractions are Kahn Process Networks (KPNs) and execution traces. When modeling computation as a KPN, one of the key challenges is to obtain a good mapping, i.e., an assignment of logical computation and communication to physical resources. In this paper we compare two system-level frameworks for solving the mapping problem: Sesame and MAPS. These frameworks, while superficially similar, embody different approaches. Sesame, motivated by modeling and design-space exploration, uses evolutionary algorithms for mapping. MAPS, being a compiler framework, uses simple and fast heuristics instead. In this work we highlight the value of common abstractions, such as KPNs and traces, as a vehicle to enable comparisons between large independent frameworks. These types of comparisons are fundamental for advancing research in the area. At the same time, we illustrate how the lack of formalized models at the hardware level are an obstacle to achieving fair comparisons. Additionally, using a set of applications from the embedded systems domain, we observe that genetic algorithms tend to outperform heuristics by a factor between 1× and 5×, with notable exceptions. This performance comes at the cost of a longer computation time, between 0 and 2 orders of magnitude in our experiments.

关键词： Computational modeling Hardware Space exploration Programming multicore processing Genetic algorithms

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The ForeC Synchronous Deterministic Parallel Programming Language for multicores

The ForeC Synchronous Deterministic Parallel Programming Lan...

引用

ieee international symposium on embedded multicore Socs (MCSoC)

作者： Eugene Yip Alain Girault Partha S. Roop Morteza Biglari-Abhari Software Technologies Research Group University of Bamberg Germany Inria Lab. LIG Grenoble France. CNRS Lab. LIG Grenoble France Department of ECE The University of Auckland New Zealand

ISBN: (纸本)9781509035328

Cyber-physical systems (CPSs) are embedded systems that are tightly integrated with their physical environment. The correctness of a CPS depends on the output of its computations and on the timeliness of completing the computations. This paper proposes the ForeC language for the deterministic parallel programming of CPS applications on multi-core execution platforms. ForeC's synchronous semantics is designed to greatly simplify the understanding and debugging of parallel programs. ForeC allows programmers to express many forms of parallel patterns while ensuring that programs are amenable to static timing analysis. One of ForeC's main innovation is its shared variable semantics that provides thread isolation and deterministic thread communication. Through benchmarking, we demonstrate that ForeC can achieve better parallel performance than Esterel, a widely used synchronous language for concurrent safety-critical systems, and OpenMP, a popular desktop solution for parallel programming. We demonstrate that the worst-case execution time of ForeC programs can be estimated precisely.

关键词： Instruction sets multicore processing Semantics Parallel programming embedded systems Timing Technological innovation

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Data and Commands Communication Protocol for Neuromorphic Platform Configuration

Data and Commands Communication Protocol for Neuromorphic Pl...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Alessandro Siino Francesco Barchi Sergio Davies Gianvito Urgese Andrea Acquaviva Dept. of Control and Computer Engineering-DAUIN Politecnico di Torino Torino Italy

ISBN: (纸本)9781509035328

In this paper, we present a new network protocol and methodology to enhance the configuration phase of the SpiNNaker spiking neural network hardware simulator. We have developed a system able to accept and process on-board a set of configuration primitives (data specification) encapsulated into ad-hoc packets, avoiding the management of chip memory from the host computer. We performed a study of the data specification generator implemented in the host software library. Afterwards, we extended the currently on-board data specification executor to cope with the newly-formed packets. The use of UDP protocol presents challenges due to its intrinsic unreliability. Furthermore, the presence of a single Ethernet link per board, and the requirement for a dedicated processor to handle all Ethernet communications limit the available communication bandwidth. A set of simulations was performed in order to tune the protocol parameters and to study the trade-offs between transmission speed and reliability. We were able to reach a throughput of a packet every 250 μs, which corresponds to a bandwidth of ~10 Mb/s. This system is able to open new perspectives for the SpiNNaker architecture. Thus, including the reduction of the time required to configure a simulation, the ability to configure more instances of a simulation. This system could even to enable the simulation of neurogenesis.

关键词： Protocols Biological system modeling Neurons Brain modeling Biological neural networks Memory management

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Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for multicore Processor system

Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Joo-On Ooi Fawnizu Azmadi B. Hussin Nordin Zakaria Universiti Tunku Abdul Rahman Petaling Jaya Selangor MY Universiti Teknologi PETRONAS Seri Iskandar Perak MY Universiti Teknologi Petronas Iskandar Perak Malaysia

ISBN: (纸本)9781509035328

The emergence of new era of Internet of Things or IoT have encouraged intensive if not extensive usage of modern mobile apps, thus multi-ISA equipped multicore processor gain great potential to be used for more efficient instruction binary processing in near future. In order to support this ISA diversity of computing platforms, mix modes of statically and dynamically Binary Translation and Optimization system, popularly consists of QEMU and LLVM or similar system, is the default technique used. However this complex system exhibits heavy slowdown (60x slowdown as compare to generic QEMU) [21] which impede its performance especially for short running application codes, typically used in IoT based apps applications. This research introduce a dual binary code translation engines to support apps based and kernel based application codes, through utilising multithreaded supported apart of original single thread supported binary translation processing in run-time. The dual engine consists of TCG generator from QEMU, and LLVM which include rich optimisations library. The evaluation through PARSEC-3.0 Benchmark shows our Hybrid DBTO system achieved performance improvement approaching 2.0x for apps based programs and 1.25x for kernel based programs, for x86 to X86-64 emulation. This technique possess great potential and serve as research based platform for future binary translation technique development, including adaptive method.

关键词： Optimization Instruction sets Emulation multicore processing Kernel Registers Virtual machining

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Sniper-TEVR: core-variation simulation platform with register-level fault injection for robust computing in CMP system

Sniper-TEVR: Core-variation simulation platform with registe...

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2016 international symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

作者： Chou, Ching-Yao Ho, Yi-Chieh Li, Huai-Ting Wu, An-Yeu Andy Graduate Institute Electronics Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9781467394987

Technology scaling enables chip Multiprocessors (CMPs) a promising approach to powerful performance within a chip. However, increasing transistor density makes them more susceptible to transient faults. Even worse, process variation due to unstable manufacturing makes the reliability problem more complicated. In recent years, there is a trend towards exploiting the inherent core redundancy characteristic in multi-core systems for error resilience. Nevertheless, traditional multi-core simulators lack of features to support reliability research. For fault environment simulation, high-level fault injection techniques make soft error effect unreal. Besides, core-variation error environment is not supported. For N Modular Redundancy (NMR) system simulation, there is no thread duplicate and thread affinity assignment feature. In this paper, we present a core-variation simulation platform with register-level fault injection based on intel's Sniper multi-core simulator. In addition to modifications of internal mechanism, an application program interface (API) is also provided. The validation result shows that the fault model in our simulator is consistent with exponential distribution model. In case study, NMR-system is validated. Hence, the proposed platform can be used for robust computing on multicore and other related researches in the future. © 2016 ieee.

关键词： Errors

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