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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Daichi Mukunoki Toshiyuki Imamura Daisuke Takahashi RIKEN Advanced Institute for Computational Science Kobe Hyogo Japan Center for Computational Sciences University of Tsukuba Tsukuba Ibaraki Japan

ISBN: (纸本)9781509035328

The performance of a CUDA kernel often depends on the number of threads per thread-block (thread-block size), and the optimal configuration differs according to the graphics processing unit (GPU) hardware and the given data size to the kernel. In particular, in linear algebra libraries such as Basic Linear Algebra Subprograms (BLAS), most routines support a wide range of problem sizes and various processors with different architectures or number of cores. Therefore, we need a method to adjust the thread-block size automatically in an economical and theoretical manner as much as possible depending on the circumstances of the routine call. In this study, we propose a method to adjust the thread-block size for several memory-bound BLAS kernels on NVIDIA GPUs. Our method is a model-driven approach that can automatically determine the thread-block size on the basis of three occupancy models on the warp, thread-block, and grid level before every launch of the kernel. We demonstrate that our method determines nearly optimal thread-block size for several kernels on Kepler and Maxwell architecture GPUs.

关键词： Instruction sets Graphics processing units Kernel Message systems Computer architecture Linear algebra Biological system modeling

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High Performance 3D CMP Design with Stacked Hybrid Memory Architecture in the Dark Silicon Era Using a Convex Optimization Model

High Performance 3D CMP Design with Stacked Hybrid Memory Ar...

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ieee international symposium on Circuits and systems (ISCAS)

作者： Onsori, Salman Asad, Arghavan Raahemifar, Kaamran Fathy, Mahmood Bilkent Univ Dept Comp Engn Ankara Turkey Dept Comp Engn Ankara Iran Iran Univ Sci & Technol Tehran Iran Ryerson Univ Elect & Comp Engn Dept Toronto ON Canada

ISBN: (纸本)9781479953417

In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chipmultiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energydelay product (EDP) and performance of the 3D CMP compared to the Baseline memory design.

关键词： Dark silicon Non-Volatile Memory (NVM) Hybrid memory Architecture embedded chip-multiprocessor (eCMP) Convex-optimization power management

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Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous many-core systems 16

Power-Aware Performance Adaptation of Concurrent Application...

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21st ieee/ACM international symposium on Low Power Electronics and Design (ISLPED)

作者： Aalsaud, Ali Shafik, Rishad Rafiev, Ashur Xia, Fei Yang, Sheng Yakovlev, Alex Newcastle Univ Sch EEE Newcastle Upon Tyne NE1 7RU Tyne & Wear England Univ Southampton Sch ECS Southampton SO17 1BJ Hants England

ISBN: (纸本)9781450341851

Modern embedded systems execute multiple applications, both sequentially and concurrently. These applications are exercised on heterogeneous platforms generating varying power consumption and system workloads (CPU or memory intensive or both). As a result, determining the most energy-efficient system configuration (i.e. the number of parallel threads, their core allocations and operating frequencies) tailored for each kind of workload and application scenario is extremely challenging. In this paper, we propose a novel runtime optimization approach with the aim of achieving maximized power normalized performance considering dynamic variation of workload and application scenarios. Fundamental to this approach is a comprehensive study to investigate the tradeoffs between inter-application concurrency with performance and power consumption under different system configurations. Using real experimental measurements on an Odroid XU-3 heterogeneous platform with a number of PARSEC benchmark applications, we model power normalized performance (in terms of IPS/Watt) underpinning analytical power and performance models, derived through multivariate linear regression (MLR). Using these models, we show that with increasing number of concurrent CPU intensive applications show variable gains in IPS/Watt compared to the memory intensive applications in both sequential and concurrent application scenarios. Furthermore, we demonstrate that it is possible to continuously adapt system configuration through a low-cost and linear-complexity runtime algorithm, which can improve the IPS/Watt by up to 125% compared to the existing approach.

关键词： Electric power utilization

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A Performance Model and Efficiency-Based Assignment of Buffering Strategies for Automatic GPU Stencil Code Generation

A Performance Model and Efficiency-Based Assignment of Buffe...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Yue Hu David M. Koppelman Steven R. Brandt Division of Electrical & Computer Engineering Louisiana State University Baton Rouge LA USA Division of Computer Science Louisiana State University Baton Rouge LA USA

ISBN: (纸本)9781509035328

Stencil computations form the basis for computer simulations across almost every field of science, such as computational fluid dynamics, data mining, and image processing. Their mostly regular data access patterns potentially enable them to take advantage of the high computation and data bandwidth of GPUs, but only if data buffering and other issues are handled properly. Finding a good code generation presents a number of challenges, one of which is the best way to make use of memory. GPUs have three types of on-chip storage: registers, shared memory, and read-only cache. The choice of type of storage and how it's used, a buffering strategy, for each stencil array (grid function, (GF)) not only requires a good understanding of its stencil pattern, but also the efficiency of each type of storage for the GF, to avoid squandering storage that would be more beneficial to another GF. Our code-generation framework supports five buffering strategies. For a stencil computation with N GFs, the total number of possible assignments is 5N. Large, complex stencil kernels may consist of dozens of GFs, resulting in significant search overhead. In this work, we present an analytic performance model for stencil computations on GPUs, and study the behavior of readonly cache and L2 cache. Next, we propose an efficiency-based assignment algorithm, which operates by scoring a change in buffering strategy for a GF using a combination of (a) the predicted execution time and (b) on-chip storage usage. By using this scoring an assignment for N GFs and b strategy types can be determined in (b - 1)N(N + 1)/2 steps. Results show that the performance model has good accuracy and that the assignment strategy is highly efficient.

关键词： Registers Computational modeling Instruction sets Graphics processing units Kernel system-on-chip Buffer storage

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On Constructing Cost Models for Online Automatic Tuning Using ATMathcoreLib: Case Studies through the SVD Computation on a multicore Processor

On Constructing Cost Models for Online Automatic Tuning Usin...

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ieee international symposium on embedded multicore Socs (MCSoC)

作者： Seiji Nagashima Takeshi Fukaya Yusaku Yamamoto Department of Computational Science Kobe University Hyogo Japan Information Initiative Center Hokkaido University/JST CREST Hokkaido Japan Department of Communication Engineering and Informatics The University of Electro-Communications/JST CREST Tokyo Japan

ISBN: (纸本)9781509035328

We consider the problem of online automatic tuning. In this setting, we execute the target program with some tuning parameters N times, where N is given, while optimizing the parameters to minimize some objective function such as the total execution time. Thus we have to choose the parameters for each execution by taking into account the trade-off between exploration and exploitation. The ATMathcoreLib library developed by Suda is a set of software that solves this problem. To model the performance of the target software, ATMathcoreLib uses a linear statistical model, and its basis functions must be provided by the user. In this paper, we investigate how to choose the basis functions appropriately, using the singular value decomposition of a square matrix as an example. We consider three cases, namely, (I) when the performance characteristics of the target problem are well understood by the user, (II) when the tuning parameter has a complicated structure, as occurs in the case of simultaneous selection of an algorithm and its parameter, and (III) when the performance characteristics of the target problem are not known to the user. The results of using ATMathcoreLib with different basis functions for each case are given. They help one understand the tuning by ATMathcoreLib and contribute to the progress of ATMathcoreLib.

关键词： Tuning Computational modeling Matrix decomposition Standards Electronic mail Libraries Software

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A heterogeneous time-triggered architecture on a hybrid system-on-a-chip platform

A heterogeneous time-triggered architecture on a hybrid syst...

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ieee international symposium on Industrial Electronics (ISIE)

作者： Haris Isakovic Radu Grosu Institute of Computer Engineering Vienna University of Technology

There is a huge discrepancy between off-the-shelf (COTS) hardware architectures and requirements for embedded industrial applications. Industrial systems are getting more complex by the day, and an interaction of highly diverse components within these systems is unavoidable. An implementation of such systems on COTS hardware is challenging. Platforms based on single-core CPUs is becoming limited, and use of multicore architectures yields safety risks, and overall inefficiency. Tailored architectures provide adequate service but they lack flexibility and therefore their economic justification is limited. Emerging technologies i.e., hybrid system-on-chip combined with novel architectural concepts are filling blind spots between COTS architectures and embedded industrial applications. The paper presents the implementation of an MPSoC architecture on a hybrid system-on-a-chip platform. This architecture provides unique capabilities for embedded applications, in particular, the possibility to host mixed-criticiality and cross-domain applications.

关键词： Computer architecture Field programmable gate arrays Hardware system-on-chip Safety Performance evaluation Computers

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Introduction: Special Section on Architecture of Future many core systems

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MICROPROCESSORS AND MICROsystemS 2016年 46卷 219-220页

作者： Asadi, Hossein Ienne, Paolo Sarbazi-Azad, Hamid Sharif Univ Technol Tehran Iran Ecole Polytech Fed Lausanne Microcomp Lab LAMI CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne MANTRA Ctr Neuromimet Syst CH-1015 Lausanne Switzerland Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran

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Memory Access Analysis of many-core system with Abundant Bandwidth 9

Memory Access Analysis of Many-Core System with Abundant Ban...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Tang, Chuan Liu, Dan Xing, Zuocheng Yang, Peng Wang, Zhe Xu, Jiang Natl Univ Def Technol Parallel & Distributed Proc Lab Changsha Hunan Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781479986705

many-core system is main architecture trend currently. One of the dominating challenges for on-chip many-core system is the memory wall. However traditional research primarily focus on the limited bandwidth. To solve this problem, many-core system is aided with large cache, and a lot of complex approaches about memory and cache are adopted aiming at relaxing the pressure of bandwidth and improving the efficiency of cache. All these methods generate much cost of area and power. In this paper, we are motivated by the feature of abundant bandwidth and low latency of optical interconnect. We analyze the characteristics of memory access on 64 cores system under the case of high bandwidth which can be assumed to benefit from optical interconnect, considering the sensibility with bandwidth and cache for different benchmarks. Finally, we discuss about promising basic frameworks suitable for many-core system with optical interconnect.

关键词： abundant bandwidth Cache many-core optical interconnect

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ADRENALINE: an OpenVX environment to optimize embedded vision applications on many-core accelerators 9

ADRENALINE: an OpenVX environment to optimize embedded visio...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Tagliavini, Giuseppe Haugou, Germain Marongiu, Andrea Benini, Luca Univ Bologna I-40126 Bologna Italy Swiss Fed Inst Technol Zurich Switzerland Univ Bologna I-40126 Bologna Italy

ISBN: (纸本)9781479986705

The acceleration of Computer Vision algorithms is an important enabler to support the more and more pervasive applications of the embedded vision domain. Heterogeneous systems featuring a clustered many-core accelerator are a very promising target for embedded vision workloads, but the code optimization for these platforms is a challenging task. In this work we introduce ADRENALINE(1), a novel framework for fast prototyping and optimization of OpenVX applications for heterogeneous SoCs with many-core accelerators. ADRENALINE consists of an optimized OpenVX run-time system and a virtual platform, and it is intended to provide support to a wide range of end users. We highlight the benefits of this approach in different optimization contexts.

关键词： embedded vision OpenVX virtual platform accelerator

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Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS multicore Platform with Resource Contentions

Poster Abstract: Slot-Level Time-Triggered Scheduling on COT...

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ieee symposium on Real-Time and embedded Technology and Applications

作者： Ankit Agrawal Gerhard Fohler Jan Nowotsch Sascha Uhrig Michael Paulitsch Chair of Real-Time Systems TU Kaiserslautern Germany Airbus Group Innovations Munich Germany Thales Austria GmbH Vienna Austria

In this work, we present an initial step towards enabling TT scheduling on a real COTS multicore platform P4080. It takes into account inter-core interferences in the on-chip network and the memory sub-system. We propose an approach comprising a runtime mechanism and an offline phase. For the runtime mechanism, we propose two servers running on each core-processing time server and memory access server implemented using built-in hardware monitors. Jointly, the two servers on each core, enforce slot-level offline computed server budget reservations, thereby limiting the maximum inter-core interferences introduced and experienced by each task considering different inter-core interference latencies. In the offline phase, we propose a procedure that can be used by any offline scheduler to compute the bound on variability in execution time of each task while allowing different slot-level memory access server budget reservations. We also did a preliminary bare-metal implementation of our proposed runtime mechanism on a real COTS multicore platform P4080. Overall, our proposed method facilitates integration of COTS multicore platforms in TT systems, while maintaining features of TT architecture like slot-level determinism, clock synchronization, etc.

关键词： multicore processing Runtime Servers Hardware Real-time systems Technological innovation Schedules

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