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Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models 17

Performance analysis of a hardware accelerator of dependence...

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17th international symposium on Performance Analysis of systems and Software, ISPASS 2016

作者： Tan, Xubin Bosch, Jaume Jiménez-González, Daniel Álvarez-Martínez, Carlos Ayguadé, Eduard Valero, Mateo Barcelona Supercomputing Center Universitat Politécnica de Catalunya Barcelona Spain

ISBN: (纸本)9781509019526

Along with the popularity of multicore and manycore, task-based dataflow programming models obtain great attention for being able to extract high parallelism from applications without exposing the complexity to programmers. One of these pioneers is the OpenMP Superscalar (OmpSs). By implementing dynamic task dependence analysis, dataflow scheduling and out-of-order execution in runtime, OmpSs achieves high performance using coarse and medium granularity tasks. In theory, for the same application, the more parallel tasks can be exposed, the higher possible speedup can be achieved. Yet this factor is limited by task granularity, up to a point where the runtime overhead outweighs the performance increase and slows down the application. To overcome this handicap, Picos was proposed to support task-based dataflow programming models like OmpSs as a fast hardware accelerator for fine-grained task and dependence management, and a simulator was developed to perform design space exploration. This paper presents the very first functional hardware prototype inspired by Picos. An embedded system based on a Zynq 7000 All-Programmable SoC is developed to study its capabilities and possible bottlenecks. Initial scalability and hardware consumption studies of different Picos designs are performed to find the one with the highest performance and lowest hardware cost. A further thorough performance study is employed on both the prototype with the most balanced configuration and the OmpSs software-only alternative. Results show that our OmpSs runtime hardware support significantly outperforms the software-only implementation currently available in the runtime system for fine-grained tasks. © 2016 ieee.

关键词： system-on-chip

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Demo Abstract: Predictable SoC Architecture Based on COTS Multi-core

Demo Abstract: Predictable SoC Architecture Based on COTS Mu...

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ieee symposium on Real-Time and embedded Technology and Applications

作者： Nitin Shivaraman Sriram Vasudevan Arvind Easwaran Nanyang Technological University

Summary form only given. With the increasing complexity of real-time embedded applications and the availability of Commercial-Off-The-Shelf (COTS) multi-cores, time-predictable execution on these platforms has become a necessity. However, there are several challenges to achieving this predictability, primarily arising due to hardware resources shared between the cores (memory controllers, caches and shared interconnect). In this demo, we present a novel system-on-chip (SoC) architecture based on COTS multi-cores that address some of these challenges. Specifically, we develop an architecture that enables COTS multi-cores to predictably access external memory. This SoC is designed using hybrid hardware platforms comprising a COTS multi-core and closely coupled Field Programmable Gate Array (FPGA), e.g., Xilinx Zynq ZC706. In our design, the COTS multi-core (ARM Cortex-A9 dual-core) is integrated using a high-speed interconnect with an arbiter module and the Memory Interface Generator (MIG) Xilinx memory controller on the FPGA. Through experiments we show that the proposed architecture has a precisely predictable worst-case memory access latency when compared to a COTS-only design.

关键词： Field programmable gate arrays Hardware Complexity theory Real-time systems multicore processing system-on-chip Logic gates

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Hierarchical Transactional Memory Protocol for Distributed Mixed-Criticality embedded systems

Hierarchical Transactional Memory Protocol for Distributed M...

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ieee international symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Zaher Owda Moisés Urbina Roman Obermaisser Mohammed Abuteir Institute of Embedded Systems University of Siegen

Transactional memories with support for real-time and reliability requirements are a research challenge for the deployment in safety-critical embedded systems. In addition, at present there are no transactional-memory architectures considering hierarchical systems of networked multi-core chips with both on-chip and off-chip networks. The presented work offers a predictable transactional memory solution for hierarchical distributed systems by executing a transactional memory protocol spanning both on-chip and off-chip networks to manage the memory operations of the cores at different multi-core chips. This includes relocating memory pages between the local caches at cores and the external memories while preserving the mixed-criticality requirements of the distributed system. The proposed protocol provides temporal predictability, fault isolation and bounded execution time assurances for safety-critical applications. An automotive use case with a simulation framework serves for the evaluation of the proposed solution.

关键词： Protocols multicore processing Logic gates Memory management system-on-chip embedded systems Real-time systems

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Expandable chip Stacking Method for many-core Architectures Consisting of Tiny chips 9

Expandable Chip Stacking Method for Many-Core Architectures ...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Nakahara, Hiroshi Ozaki, Tomoya Matsutani, Hiroki Koibuchi, Michihiro Amano, Hideharu Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informatcs Chiyoda Ku Tokyo Japan

ISBN: (纸本)9781479986705

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large system-on-chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling Thruchip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

关键词： multiprocessing systems system-on-chip NAS parallel benchmark SoC TCI deadlock-free routing design expandable chip stacking method inductive coupling thruchip interface interchip communication many-core architecture staggered stacking method Coils Network topology Routing Stacking system recovery Three-dimensional displays Topology Inductive coupling interconnect Interconnection network system-on-chip Stacking core construction three-dimensional displays system recovery Multiprocessing systems Haptocorrin Interconnection networks Computer chips Network topology Coils Network routing topology DNA Microarrays

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Top-down profiling of application specific many-core neuromorphic platforms 9

Top-down profiling of application specific many-core neuromo...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Urgese, Gianvito Barchi, Francesco Macii, Enrico Politecn Torino Dept Control & Comp Engn DAUIN Cso Duca degli Abruzzi 24 I-10129 Turin Italy

ISBN: (纸本)9781479986705

In this paper we present a top-down methodology aimed at evaluating the scalability of Spiking Neural Network (SNN) simulations on massively many-core and densely interconnected platforms. Spiking neural networks mimic brain activity by emulating spikes sent among neurons populations. many-core platforms are emerging computing targets to achieve real-time simulation SNN. Neurons are mapped to parallel cores and spikes are sent over the on-chip and off-chip network. However, due to the heterogeneity and complexity of neuron population activity, achieving an efficient exploitation of platforms resources is a challenging problem, often impacting simulation reliability and limiting the biological network size. To address this challenge, the proposed methodology, based on customized SNN configurations, extracts detailed profiling information about network usage of on-chip and off-chip resources. We first show the results of the application of our methodology to the SpiNNaker neuromorphic many-core platform. Then, we demonstrate how the profiling information can be used to improve the reliability of biologically plausible SNN simulations.

关键词： multiprocessing systems neural nets SNN configuration SpiNNaker neuromorphic many-core platform application specific many-core neuromorphic platform biologically plausible SNN simulation densely interconnected platforms neuron population activity spiking neural network top-down profiling Analytical models Biological system modeling Brain modeling Neurons Routing Sociology Statistics many-core Multi-chip Neuromorphic Profiling Neural network Brain modeling Biological system modeling Multiprocessing systems Neuromorphics Sociology ANALYSIS MODELS Neurons Network routing SNN gene Platform

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Enabling Scalable and Fine-Grained Nested Parallelism on embedded many-cores 9

Enabling Scalable and Fine-Grained Nested Parallelism on Emb...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Capotondi, Alessandro Marongiu, Andrea Benini, Luca Univ Bologna DEI I-40126 Bologna Italy Univ Bologna IIS I-40126 Bologna Italy Swiss Fed Inst Technol Zurich ETHZ Zurich Switzerland

ISBN: (纸本)9781479986705

Current high-end embedded systems are designed as heterogeneous systems-on-chip (SoCs), where a general-purpose host processor is coupled to a programmable manycore accelerator (PMCA). Such PMCAs typically leverage hierarchical interconnect and distributed memory with non-uniform access (NUMA). Nested parallelism is a convenient programming abstraction for large-scale cc-NUMA systems, which allows to hierarchically (and dynamically) create multiple levels of fine-grained parallelism whenever it is available. Available implementations for cc-NUMA systems introduce large overheads for nested parallelism management, which cannot be tolerated due to the extremely fine-grained nature of embedded parallel workloads. In particular, creating a team of parallel threads has a cost that increases linearly with the number of threads, which is inherently non scalable. This work presents a software cache mechanism for frequently-used parallel team configurations to speed up parallel thread creation overheads in PMCA systems. When a configuration is found in the cache the cost for parallel team creation has a constant time, providing a scalable mechanism. We evaluated our support on the STMicroelectronics STHORM many-core. Compared to the state-of-the art, our solution shows that: i) the cost for parallel team creation is reduced by up to 67%;ii) the tangible effect on real ultra-fine-grained parallel kernels is a speedup of up to 80%.

关键词： cache storage embedded systems multiprocessing systems parallel programming system-on-chip PMCA STMicroelectronics STHORM many-core SoC distributed memory with nonuniform access embedded many-cores fine-grained parallelism heterogeneous systems-on-chip nested parallelism parallel team configuration parallel thread creation overhead programmable manycore accelerator programming abstraction software cache mechanism Fabrics Instruction sets Message systems Parallel processing Programming Recruitment embedded many-core Architectures OpenMP Parallel Programming Models embedded systems Computer based information systems Parallel programming instruction sets system-on-chip Multiprocessing systems cache storage PARALLEL PROCESSING (COMPUTERS) Programming Textile fabrics parallelism fabric Synclitism THREADS Parallel Lines

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Co-simulation framework for AUTOSAR multi-core processors with message-based Network-on-chips

Co-simulation framework for AUTOSAR multi-core processors wi...

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ieee international Conference on Industrial Informatics (INDIN)

作者： Moises Urbina Hamidreza Ahmadian Roman Obermaisser Institute of Embedded Systems University of Siegen

ISBN: (纸本)9781509028719

Simulation environments play a very important role in the development of embedded systems helping system architects in exploring design decisions. However, the simulation of AUTOSAR multi-core processors with Network-on-chips (NoCs) for inter-core communication is still a significant research problem. Message-based NoCs provide significant advantages for real-time embedded systems as in the case of the automobile industry. Such a simulation would provide early insights into the real-time behavior of the AUTOSAR application on the message-based multi-core chip. This paper presents as a novel contribution a co-simulation framework supporting the integration of the AUTOSAR architecture with NoC-based platforms. We describe a simulation model for application cores playing the role of virtual AUTOSAR ECUs on the MPSoC platform. The framework introduces an interface for the co-simulation of simulation models for the AUTOSAR-based software (virtual ECUs), the natural environment and the NoC behavior. This co-simulation interface combines a Functional Mock-up Unit (FMU) and a local coordinator for the synchronization and the data exchange between the simulators hosting the simulation models. The implementation is performed using the VEOS simulator for the AUTOSAR-based software and physical environment models, and the GEM5 simulator for the on-chip communication level. An anti-lock braking use case serves for the evaluation of the co-simulation framework. 1

关键词： system-on-chip Standards Software multicore processing Data models Ports (Computers)

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Splitting tasks for migrating real-time automotive applications to multi-core ECUs

Splitting tasks for migrating real-time automotive applicati...

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international symposium on Industrial embedded systems

作者： Martin Lowinski Dirk Ziegenbein Sabine Glesner Software Engineering for Embedded Systems Technische Universität Berlin Germany Robert Bosch GmbH Corporate Research Germany

Real-time automotive software becomes increasingly complex due to the integration of more functionalities. At the same time, the computation power of electronic control units grows by increasing the number of cores instead of the core performance. Thus, in the near future a single task will require more computation power than a single core can offer. We propose an approach that solves this problem by splitting a task into multiple parallel task partitions with minimal synchronization overhead while maintaining all data dependencies of the functionalities inside the original task. The approach is successfully validated on a real-world engine management system.

关键词： Synchronization multicore processing Software Automotive applications Software algorithms Resource management

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The Network Performance Analysis Platform and its Application to Network Buffer Evaluation of the embedded system 9

The Network Performance Analysis Platform and its Applicatio...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Sakurai, Yuichi Shimbo, Kenichi Toba, Tadanobu Osaka, Hideki Hitachi Ltd Ctr Technol Innovat Prod Engn Res & Dev Grp Yokohama Kanagawa 2440817 Japan

ISBN: (纸本)9781479986705

In this work, a network simulator is developed to predict the amount of hardware resources required for an embedded large-scale data processing system. It is difficult to simulate with the existing hardware simulator because the calculation time of processors lasts several days. This large time-consumption is caused by the fact that the processor module is made up of many components like CPU cores and shared buses. The target of this work is to complete the transmission simulation with one million packets in six hours. To reduce the analysis time, we focused on the shared bus of the processor and found that it is possible to estimate the amount of network buffer usage in a congestion state of packets in the shared bus. We have developed a shared bus timing model for calculating the packet transmission capacity by using the parameters related to the CPU core bus access time of the processor. Thereby, its simulation throughput can be increased up to 13 thousand packets per minute. The simulation results show that one million packets could be completed in two and a half hours by using the proposed techniques and confirmed that the proposed simulator can be used to optimize a large-scale data processing system.

关键词： Network simulation embedded system Serial RapidIO interconnect network

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A 101.4 GOPS/W reconfigurable and scalable control-centric embedded processor for domain-specific applications

A 101.4 GOPS/W reconfigurable and scalable control-centric e...

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international symposium on Circuits and systems

作者： Ning Ma Zhuo Zou Zhonghai Lu Lirong Zheng Yuxiang Huan Stefan Blixt iPack Vinn Excellence Center KTH Forum 120 164 40 Stockholm-Kista Sweden Fudan University Shanghai China Imsys AB Stockholm Sweden

ISBN: (纸本)9781479953424

Increasing the energy efficiency and performance while providing the customizability and scalability is vital for embedded processors adapting to domain-specific applications such as Internet of Things. In this paper, we proposed a reconfigurable and scalable control-centric architecture, and implemented the design consisting of two cores and an on-chip multi-mode router in 65 nm technology. The reconfigurability is enabled by the restructurable sequence mapping table (SMT) thus the reorganizable functional units. Owing to the integration of the multi-mode router, on-chip or inter-chip network for multi-/many-core computing can be composed for performance extension on demand even in the post-fabrication stage. Control-centric design simplifies the control logic, shrinks the non-functional units and orchestrates the operations to increase the hard are utilization and reduce the excessive data movement for high energy efficiency. As a result, the processor can both conduct general-purpose processing with 29% smaller code size and application-specific processing with over 10 times performance improvement when implementing AES by SMT. The dual-core processor consumes 19.7 μW/MHz with die size of 3.5 mm~2. The achieved energy efficiency is 101.4GOPS/W.

关键词： Process control system-on-chip Logic gates Hardware Switching circuits Power demand Scalability

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