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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Cross By Pass-Mesh Architecture for on-chip Communication 9

Cross By Pass-Mesh Architecture for on-Chip Communication

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Gulzari, Usman Ali Anjum, Sheraz Agha, Shahrukh COMSATS Inst Informat Technol Dept Elect Engn Islamabad Pakistan COMSATS Inst Informat Technol Dept Elect Engn Wah Cantt Pakistan

ISBN: (纸本)9781479986705

Network-on-chip (NoC) is a new paradigm of system on chip (SoC). It has become a great focus of research by many groups during this era. Among all the on chip communication architectures that have been proposed until now, Mesh has proved to be the best architecture for implementation due to its simple and regular interconnection structure. In this paper, we present a new interconnect network architecture known as cross by pass mesh (CBP-Mesh) for on chip communication. The CBP-Mesh is much like traditional Mesh with the addition of two cross by pass links. By adding these cross by pass links, the number of hops in the networks and overall latency is reduced. The comparative analysis with other similar topologies like Mesh, Tours, 2DDgl-Mesh, SD-Mesh, X-Mesh and C2-Mesh, shows that the proposed topology outperforms in terms of latency. In the proposed architecture, the packets are routed towards their destinations in less time. These architectures are analyzed and compared in terms of topology characteristic, performance and cost of networks. Moreover results show that the proposed architecture perform better with respect to area utilization and power consumption.

关键词： Network-on-chip system-on-chip Router Topology design

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Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks 49

Snatch: Opportunistically reassigning power allocation betwe...

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ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Dimitrios Skarlatos Renji Thomas Aditya Agrawal Shibin Qin Robert Pilawa-Podgurski Ulya R. Karpuzcu Radu Teodorescu Nam Sung Kim Josep Torrellas University of Illinois Urbana-Champaign Ohio State University NVIDIA Corp. University of Minnesota Twin Cities

ISBN: (纸本)9781509035090

The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this paper, we propose to reduce the number of P/G pins of both processor and memory in a 3D design, and dynamically and opportunistically divert some power between the two PDNs on demand. To perform the power transfer, we use a small bidirectional on-chip voltage regulator that connects the two PDNs. Our concept, called Snatch, is effective. It allows the computer to execute code sections with high processor or memory power requirements without having to throttle performance. We evaluate Snatch with simulations of an 8-core multicore stacked with two memory dies. In a set of compute-intensive codes, the processor snatches memory power for 30% of the time on average, speeding-up the codes by up to 23% over advanced turbo-boosting; in memory-intensive codes, the memory snatches processor power. Alternatively, Snatch can reduce the package cost by about 30%.

关键词： Pins system-on-chip Three-dimensional displays Voltage control Resource management multicore processing

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core tunneling: Variation-aware voltage noise mitigation in GPUs

Core tunneling: Variation-aware voltage noise mitigation in ...

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ieee symposium on High-Performance Computer Architecture

作者： Renji Thomas Kristin Barber Naser Sedaghati Li Zhou Radu Teodorescu Department of Computer Science and Engineering The Ohio State University

ISBN: (纸本)9781467392129

Voltage noise and manufacturing process variation represent significant reliability challenges for modern microprocessors. Voltage noise is caused by rapid changes in processor activity that can lead to timing violations and errors. Process variation is caused by manufacturing challenges in low-nanometer technologies and can lead to significant heterogeneity in performance and reliability across the chip. To ensure correct execution under worst-case conditions, chip designers generally add operating margins that are often unnecessarily conservative for most use cases, which results in wasted energy. This paper investigates the combined effects of process variation and voltage noise on modern GPU architectures. A distributed power delivery and process variation model at functional unit granularity was developed and used to simulate supply voltage behavior in a multicore GPU system. We observed that, just like in CPUs, large changes in power demand can lead to significant voltage droops. We also note that process variation makes some cores much more vulnerable to noise than others in the same GPU. Therefore, protecting the chip against large voltage droops by using fixed and uniform voltage guardbands is costly and inefficient. This paper presents core tunneling, a variation-aware solution for dynamically reducing voltage margins. The system relies on hardware critical path monitors to detect voltage noise conditions and quickly reacts by clock-gating vulnerable cores to prevent timing violations. This allows a substantial reduction in voltage margins. Since clock gating is enabled infrequently and only on the most vulnerable cores, the performance impact of core tunneling is very low. On average, core tunneling reduces energy consumption by 15%.

关键词： Graphics processing units Tunneling Histograms Power demand Monitoring Delays Kernel

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Trio: A triple class on-chip network design for efficient multicore processors 17

Trio: A triple class on-chip network design for efficient mu...

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2015 ieee 17th international Conference on High Performance Computing and Communications (HPCC)

作者： Xu, Thomas Canhao Leppanen, Ville Liljeberg, Pasi Plosila, Juha Tenhunen, Hannu Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9781479989379

We propose and analyse an on-chip interconnect design for improving the efficiency of multicore processors. Conventional interconnection networks are usually based on a single homogeneous network with uniform processing of all traffic. While the design is simplified, this approach can have performance bottlenecks and limitations on system efficiency. We investigate the traffic pattern of several real world applications. Based on a directory cache coherence protocol, we characterise and categorize the traffic in terms of various aspects. It is discovered that control and unicast packets dominated the network, while the percentages of data and multicast messages are relatively low. Furthermore, we find most of the invalidation messages are multicast messages, and most of the multicast messages are invalidation message. The multicast invalidation messages usually have higher number of destination nodes compared with other multicast messages. These observations lead to the proposed triple class interconnect, where a dedicated multicast-capable network is responsible for the control messages and the data messages are handled by another network. By using a detailed full system simulation environment, the proposed design is compared with the homogeneous baseline network, as well as two other network designs. Experimental results show that the average network latency and energy delay product of the proposed design have improved 24.4% and 10.2% compared with the baseline network.

关键词： cache storage multiprocessing systems multiprocessor interconnection networks network synthesis network-on-chip Trio average network latency dedicated multicast-capable network destination nodes directory cache coherence protocol energy delay product full system simulation environment homogeneous baseline network multicast invalidation messages multicore processors on-chip interconnect design traffic pattern triple class on-chip network design unicast packets Coherence multicore processing Ports (Computers) Program processors Protocols system-on-chip Unicast cache design efficient multicore

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Providing Fairness in Heterogeneous multicores with a Predictive, Adaptive Scheduler

Providing Fairness in Heterogeneous Multicores with a Predic...

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ieee international symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Saeid Barati Hank Hoffmann University of Chicago

ISBN: (纸本)9781509036837

multicore applications contend for resources -- especially memory bandwidth -- reducing both quality-of-service and overall system performance. Contention-aware schedulers have been proposed to provide fairness and predictable behavior through thread-level scheduling. Prior approaches have two drawbacks, however. First, many introduce overhead that reduces overall performance. Second, the emergence of heterogeneous multicores has made handling contention and providing fairness much more difficult as the scheduler must now account for both application interference and the performance effects of different core types. This paper proposes augmenting existing contention-aware approaches with predictive and adaptive components to providefair memory access and performance improvements on heterogeneous multicores. The predictive component's closed-loop approach anticipates how different processes will perform with different core types, while the adaptive component dynamically tunes key scheduling parameters to the current workload. We implement and evaluate this approach on a real Linux/x86system with a variety of memory and compute intensive benchmarks. We find that adding prediction improves fairness and performance by 38% and 4% (respectively) compared to aprior state-of-the-art contention-aware approach. The additionof adaptation allows users to select for fairness or performance optimization, providing an additional 24% improvement infairness or a 9% improvement in performance beyond the predictive approach.

关键词： Levee Instruction sets multicore processing Hardware Runtime Processor scheduling Predictive models

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Evaluation of Memory Access Arbitration Algorithm on Tilera's TILEPro64 platform 17

Evaluation of Memory Access Arbitration Algorithm on Tilera'...

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2015 ieee 17th international Conference on High Performance Computing and Communications (HPCC)

作者： Shekhar, Mayank Ramaprasad, Harini Mueller, Frank Southern Illinois Univ Carbondale Carbondale IL 62901 USA Univ North Carolina Charlotte Charlotte NC USA North Carolina State Univ Raleigh NC USA

ISBN: (纸本)9781479989379

As real-time embedded systems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-time applications on multi-core platforms introduce several predictability challenges. One of these challenges is bounding the latency of memory accesses issued by real-time tasks. This challenge is exacerbated as the number of cores and, hence, the degree of resource sharing increases. Over the last several years, researchers have proposed techniques to overcome this challenge. In prior work, we proposed an arbitration policy for memory access requests over a Network-on-chip. In this paper, we implement and evaluate variants of our arbitration policy on a real hardware platform, namely Tilera's TilePro64 platform.

关键词： embedded systems multiprocessing systems network-on-chip storage management TILEPro64 platform memory access arbitration algorithm multicore platforms real-time embedded systems Dynamic scheduling Engines Hardware Instruction sets Memory management Real-time systems system-on-chip

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Managing the Latency of Data-Dependent Tasks in embedded Streaming Applications 9

Managing the Latency of Data-Dependent Tasks in Embedded Str...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Do, Xuan Khanh Louise, Stephane Cohen, Albert CEA LIST F-91191 Gif Sur Yvette France INRIA F-75005 Paris France ENS F-75005 Paris France

ISBN: (纸本)9781479986705

Streaming languages are well suited to the development of embedded many-core applications that process large volumes of data with high throughput. Because they enable periodic scheduling, cyclo-static models of computation and their variants are well fitted to modern real-time applications. Nevertheless, while schedules may be functionally correct-by-construction, they can still violate timing constraints and safety requirements of critical real-time embedded systems (e.g. avionics). Such violations are usually caused by delays that are not accounted for, due to resource sharing (e.g. the communication medium). In this paper, we investigate the applicability of the theory of hard-real-time scheduling for periodic tasks in the context of streaming applications. More specifically, we consider Cyclo-Static Dataflow (CSDF) graphs with variable interprocessor communication (IPC) times, and real-time constraints imposed by hardware devices or control engineers. As a result, we establish a latency constraint on the initiation times of predecessor actors on which a given actor is dependent. Based on this constraint, we show how to guarantee real-time services and reduce inconsistencies in a CSDF application by introducing a fault-tolerant procedure. We evaluate the performance of our scheduling policy for a set of 12 real-life streaming applications. We find that in most of the cases, our approach yields the maximum achievable throughput as obtained under Self-Timed scheduling (STS).

关键词： cyclo-static dataflow real-time scheduling latency fault-tolerant

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An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUs 9

An Enhanced Profiling Framework for the Analysis and Develop...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Bombieri, Nicola Busato, Federico Fummi, Franco Univ Verona Dept Comp Sci I-37100 Verona Italy

ISBN: (纸本)9781479986705

Parallelizing software applications through the use of existing optimized primitives is a common trend that mediates the complexity of manual parallelization and the use of less efficient directive-based programming models. Parallel primitive libraries allow software engineers to map any sequential code to a target many-core architecture by identifying the most computational intensive code sections and mapping them into one ore more existing primitives. On the other hand, the spreading of such a primitive-based programming model and the different GPU architectures have led to a large and increasing number of third-party libraries, which often provide different implementations of the same primitive, each one optimized for a specific architecture. From the developer point of view, this moves the actual problem of parallelizing the software application to selecting, among the several implementations, the most efficient primitives for the target platform. This paper presents a profiling framework for GPU primitives, which allows measuring the implementation quality of a given primitive by considering the target architecture characteristics. The framework collects the information provided by a standard GPU profiler and combines them into optimization criteria. The criteria evaluations are weighed to distinguish the impact of each optimization on the overall quality of the primitive implementation. The paper shows how the tuning of the different weights has been conducted through the analysis of five of the most widespread existing primitive libraries and how the framework has been eventually applied to improve the implementation performance of a standard primitive.

关键词： graphics processing units parallel programming GPU GPU profiler directive-based programming models graphics processing unit many-core architecture parallel primitives primitive-based programming model profiling framework software applications parallelization Graphics processing units Instruction sets Kernel Libraries Optimization Synchronization Graphics Processing Unit instruction sets Libraries Parallel programming GRAPPER PICK UP core construction Primitive Applications software Kernel Frameworks sequential codes

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Towards Automatic Code Generation of Run-Time Power Management for embedded systems using Formal Methods 9

Towards Automatic Code Generation of Run-Time Power Manageme...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Fathabadi, Asieh Salehi Maeda-Nunez, Luis Alfonso Butler, Michael J. Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Elect & Comp Sci Southampton SO9 5NH Hants England

ISBN: (纸本)9781479986705

Run-Time Management (RTM) systems are used to control energy hooks at run-time to minimise the energy consumption of embedded systems with single and many-core processors. Typically, such RTM systems are aware of application requirements and utilise workload prediction and machine learning algorithms to estimate the optimal configuration. An RTM mechanism should not compromise the reliability or performance of the platform it is managing. Because of the potential complexity and interaction with the platform and its applications, we are using rigorous design methods that allow us to master the complexity and verify the correctness of our designs in a formal way. The formal RTM design can be verified earlier in the development process before implementation, which early verification can reduce the cost of fixing potential failures which can be very demanding in testing the system after implementation. In addition, the formal model of a RTM system can be automatically translated into executable code to be executed on the hardware. Automatic code generation reduces the efforts of hand-coded implementation and is portable across different architectures and Operating systems (OSs). In this paper we propose a formal approach toward automatic generation of RTM system code, for a video decoder application, from a verified formal model of a RTM. The formal model of the RTM system is developed using the Event-B formal modelling language and is verified using theorem proving and model checking. The automatically generated RTM system has been integrated in an embedded platform as a Linux governor, and provides up to 4% improvement over Linux's default Ondemand governor.

关键词： Linux embedded systems formal verification power aware computing program compilers theorem proving Event-B formal modelling language Linux governor RTM system code automatic code generation formal methods model checking run-time power management video decoder Algorithm design and analysis Decoding Hardware Learning (artificial intelligence) Mathematical model Monitoring Prediction algorithms embedded systems theorem proving power aware computing Transfer molding Video Decoder Algorithm design and analysis compilers Prediction algorithms Linux Model checking Formal verification Computer hardware DECODING Code generation Runtime

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Automatic Runtime Customization for Variability Awareness on multicore Platforms 9

Automatic Runtime Customization for Variability Awareness on...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Ayad, Gasser Nittala, Ramakrishna Lemaire, Romain Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy Univ Grenoble Alpes F-38000 Grenoble France CEA LETI F-38054 Grenoble France

ISBN: (纸本)9781479986705

Driven by increasingly aggressive CMOS technology scaling, sub-wavelength lithography is incurring more evident variability in the technology parameters of the semiconductors fabrication process. That variability results in otherwise identical designs displaying very different performances, power consumption levels and lifespans once fabricated. Hence, process variability may lead to execution uncertainties, impacting the expected quality of service and energy efficiency of the running software. As such uncertainties are intolerable in certain application domains such as automotive and avionic infotainment systems, it has become a persistent necessity to customize runtime engines to introduce measures for variability awareness in task allocation decisions. The purpose of compensating process variability is to avoid performance degradation and energy inefficiency. And customization is meant to take place automatically through exporting the variability-impacted platform characteristics - such as per-core manufactured clock frequency - for the runtime library to perform variability-aware workload sharing on the target cores of the hardware platform. Hence, we can eventually achieve noticeable optimization results, not only on the system performance and energy consumption levels, but also in increasing productivity in systems development, testing, integration, and marketing. This paper presents a holistic approach starting from a system model of the target multicore platform, to building and integrating the runtime library, and finally highlighting the optimization results achieved through the proposed runtime customization paradigm.

关键词： CMOS integrated circuits energy consumption lithography microprocessor chips multiprocessing systems power aware computing software libraries aggressive CMOS technology scaling automatic runtime customization automotive systems avionic infotainment systems energy consumption levels energy efficiency energy inefficiency multicore platform multicore platforms per-core manufactured clock frequency performance degradation power consumption levels runtime customization paradigm runtime engines runtime library semiconductors fabrication process subwavelength lithography task allocation decisions variability awareness variability-aware workload sharing Hardware multicore processing Resource management Runtime Runtime library Software Unified modeling language Runtime library Runtime power aware computing energy consumption Software libraries Multiprocessing systems UML degradation of performance Microprocessor chips CMOS integrated circuits Lithography Energy efficiency management of resources Computer hardware computer software

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