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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是541-550 订阅

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Memory-Access Aware Work-Load Distribution for Peak-Temperature Reduction of 3D Multi-core embedded systems

Memory-Access Aware Work-Load Distribution for Peak-Temperat...

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ieee international Conference on Digital Signal Processing (DSP)

作者： Mohanty, Basant K. Chaturvedi, Vivek Rathore, Vijeta Srikanthan, Thambipillai Jaypee Univ Engn & Tech Dept Elect & Comm Engn Guna Madhya Pradesh India Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781479980581

Multiple cores are preferred to meet the ever increasing computation demand of embedded systems. A multicore system is communication intensive with on-chip wire delays and on-chip interconnects accounting for half the dynamic power dissipation. A three-dimensional (3D) stacking of dies enables low intra-chip distances for signal transmission and helps to overcome the interconnect bottleneck of multi-core systems. The 3D integration by through silicon via (TSV) can significantly improve memory-logic communication bandwidth of multi-core systems. However, the 3D multi-core system has poor heat removal capability due to position of the heat-sink. In this paper, we made a study on the thermal profile of DRAM memory layers of 3-D multi-core system. In this study, workloads are distributed to memory layers based on its thermal efficiency such that work load of heavier applications is allocated to the memory layer having highest thermal efficiency and those of lighter applications is allocated to the memory layer with lower thermal efficiency. Experimental result shows that with selective work load distribution, the average peak temperature of the 3D multi-core system is reduced than randomly allocated work load to the memory layers. A memory controller could be designed for run-time distribution of work load to the memory layers which will be addressed in the future work.

关键词： Efficiency

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An Hybrid Architecture for Consolidating Mixed Criticality Applications on multicore systems 21

An Hybrid Architecture for Consolidating Mixed Criticality A...

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21st ieee international On-Line Testing symposium (IOLTS)

作者： Avramenko, Serhiy Esposito, Stefano Violante, Massimo Sozzi, Marco Traversone, Massimo Binello, Marco Terrone, Marco Politecn Torino Dipartimento Automat & Informat Turin Italy Selex ES Nerviano Italy Alenia Aermacchi Turin Italy

ISBN: (纸本)9781467379052

The paper proposes a novel hybrid architecture to consolidate avionic applications with different levels of criticality in a multicore processor. The architecture stems from the need of deploying into one computer different applications with conflicting requirements in terms of criticalities that today are mapped into multiple independent computers. The architecture relies on a type-1 hypervisor to separate the applications exposing different criticalities levels, to avoid that low-criticality applications might corrupt high-criticality applications. Moreover, the architecture exploits custom-designed hardware watchdogs to enforce error detection. Fault-injection results are presented to illustrate the robustness of the architecture.

关键词： avionic multi-core mixed-criticality consolidation fault-tolerance system-on-programmable-chip (SoPC) hypervisor (HV) intellectual property (IP) critical partition (CP) critical application (CA) non-critical partition (NCP) non-critical application (NCA) system watchdog timer (SWDT) watchdog (WD) single event upset (SEU) software bug (SwB)

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Why Race-to-Finish is Energy-Inefficient for Continuous Multimedia Workloads 9

Why Race-to-Finish is Energy-Inefficient for Continuous Mult...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Stokke, Kristoffer Robin Stensland, Hakon Kvale Halvorsen, Pal Griwodz, Carsten Simula Res Lab Fornebu Norway Univ Oslo N-0316 Oslo Norway

ISBN: (纸本)9781479986705

It is often believed that a "race-to-finish" approach, where processing is finished quickly, is the best way to conserve energy on modern mobile architectures. However, from earlier work we know that for continuous multimedia workloads, the best way to conserve energy is to minimise processor frequency such that application deadlines are met. In this paper, we investigate the reasons behind this. We develop an original method to model dynamic and static power on individual power rails of the Tegra K1 by only measuring the total power usage of the board. Our model has an average error of only 8 %. We find that the way an application scales performance with frequency is very important for energy efficiency. We demonstrate a 37 % energy saving by minimising processor and memory frequency of a video processing filter such that a framerate of 20 FPS is met.

关键词： image filtering system-on-chip video signal processing Tegra K1 application deadlines average error continuous multimedia workloads dynamic power model energy conservation energy efficiency energy saving memory frequency minimisation mobile architectures power rails processor frequency minimisation race-to-finish approach static power model total power usage measurement video processing filter Clocks Current measurement Frequency estimation Leakage currents Power measurement Rails Voltage measurement Energy modelling multimedia optimisation power Energy conservation Energy sources MULTI-MEDIA system Rail Railway Rail image filtering Power measurement Electric current measurement voltage measurement Current measuring Video signal processing Frequency estimation Timing devices system-on-chip Energy efficiency

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Runtime 3-D Stacked Cache Data Management for Energy Minimization of 3-D chip-Multiprocessors

Runtime 3-D Stacked Cache Data Management for Energy Minimiz...

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15th international symposium on Quality Electronic Design (ISQED)

作者： Lee, Seunghan Kang, Kyungsu Jung, Jongpil Kyung, Chong-Min Korea Adv Inst Sci & Technol SSAL Taejon South Korea Ecole Polytech Fed Lausanne LSI Labs Lausanne Switzerland

ISBN: (纸本)9781479939466

In a 3-D processor-memory system, multiple cache dies can be stacked onto multi-core die to reduce latency and power of the on-chip wires connecting the cores and the cache, which finally increases the power efficiency. However, there are two challenging issues. The first is the high power density (resulting from multiple die stacking) that incurs many temperature-related problems including temperature-dependent leakage power. The second is the processor-cache traffic congestions that occur at through-silicon vias (TSVs) shared by multiple stacked caches. In this paper, a runtime cache data mapping is proposed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The proposed method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows that the proposed method achieves up to 22.88% energy reduction compared to an existing solution which considers only the temperature distribution.

关键词： cache storage multiprocessing systems temperature distribution three-dimensional integrated circuits 3D chip-multiprocessors 3D processor-memory system 3D stacked L2 caches TSV cache dies die stacking energy minimization energy reduction latency reduction memory traffic multicore die multiple-stacked caches on-chip wire power power density power efficiency processor-cache traffic congestion runtime 3D stacked cache data management runtime cache data mapping temperature distribution temperature-dependent leakage power temperature-related problem through-silicon vias Energy consumption Instruction sets Memory management multicore processing Random access memory Runtime Temperature distribution

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Comparison of Shared and Private L1 Data Memories for an embedded MPSoC in 28nm FD-SOI 9

Comparison of Shared and Private L1 Data Memories for an Emb...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Sievers, Gregor Daberkow, Julian Ax, Johannes Flasskamp, Martin Kelly, Wayne Jungeblut, Thorsten Porrmann, Mario Rueckert, Ulrich Univ Bielefeld CITEC Cognitron & Sensor Syst Grp Bielefeld Germany Queensland Univ Technol Fac Sci & Engn Brisbane Qld Australia

ISBN: (纸本)9781479986705

Tightly coupling CPUs within clusters allows for low latency, high bandwidth communication in MPSoCs. Our coreVA-MPSoC integrates multiple clusters using an on-chip network. In this work we introduce a shared L1 data memory that can be accessed by all CPUs of a cluster with low latency. A Mesh-of-Trees (MoT) and a crossbar as topology for the shared memory interconnect are presented. A cluster that integrates the shared L1 memory is compared with an architecture that features an AXI interconnect and a local L1 data memory for each CPU. In addition, we consider an architecture that integrates both. We present implementation results using a 28nm FD-SOI standard cell technology. The shared L1 memory shows similar area results compared to the local memory architecture. Place and route results of a cluster with 8 CPUs, 128 kB local- and 128 kB shared L1 data memory divided into 16 memory banks show a frequency of 728MHz and an area of 1.77mm(2). To map programs to the different CPU cluster configurations a compiler for streaming applications is used. An architecture with both local and shared L1 data memory and 4 memory banks shows best performance results in combination with a high resource efficiency.

关键词： embedded systems memory architecture multiprocessor interconnection networks network topology program compilers system-on-chip AXI interconnect CPU cluster configurations coreVA-MPSoC FD-SOI standard cell technology MoT compilers crossbar embedded MPSoC local memory architecture memory banks mesh-of-trees multiple cluster integration on-chip network private L1 data memories shared L1 data memories shared memory interconnect streaming applications tightly-coupled CPU topology Central Processing Unit Clocks Memory management Routing Standards Topology 28nm FD-SOI CPU cluster MPSoC multi-banked memory shared L1 memory compilers central processing units Memory Bank network-on-chip topology crossrail multiprocessor interconnection networks Memory architecture Store management Timing devices system-on-chip LU1 Data storage devices embedded systems Network topology

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Cross-Layer Exploration of Heterogeneous multicore Processor Configurations 28

Cross-Layer Exploration of Heterogeneous Multicore Processor...

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28th international Conference on VLSI Design (VLSID) / 14th international Conference on embedded systems

作者： Sarma, Santanu Dutt, Nikil Univ Calif Irvine Dept Comp Sci Irvine CA 92717 USA

ISBN: (纸本)9781479966585

Heterogeneous multicore processors (HMP) present significant advantages over homogenous multiprocessors due to their improved power, performance, and energy efficiency for a given chip/die area. However, due to their diverse and vast design space, selecting a suitable HMP configuration with different core types within a given area-power budget is an extremely challenging task. In this paper, we present a cross-layer approach for exploring and configuring a HMP for a given system goal under system level constraints (such as equal area or power budget) as an optimization problem. Unlike the state-of-the-art approaches, we jointly consider cross-layer features of the application, operating system (task allocation strategies), and hardware architecture while deploying computationally efficient predictive models (of performance and power) in configuring the HMP platform resources (number and types of cores) in an evolutionary optimization framework. Our predictive cross-layer approach enables the designer to comparatively evaluate and select the most promising (e.g., energy and performance efficient) HMP configuration in over two order of magnitude less simulation time especially during the early design and verification stages when the design space is at its largest.

关键词： Design Space Exploration Cross-Layer Design Heterogeneous multicore processor Task Allocation and Scheduling Multi-Processor systems-on-chip

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On-chip Watchdog to monitor RTOS activity in MPSoC exposed to noisy environment 10

On-chip Watchdog to monitor RTOS activity in MPSoC exposed t...

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10th international Workshop on the Electromagnetic Compatibility of Integrated Circuits, EMC Compo 2015

作者： De Oliveira, Christofer Bolzani Poehls, Leticia Vargas, Fabian Electrical Engineering Dept. Catholic University - PUCRS Av. Ipiranga 6681 Porto Alegre90619-900 Brazil

ISBN: (纸本)9781467378963

The use of Real-Time Operating system (RTOS) became a mandatory condition to design safety-critical real-time embedded systems based on multicore processors. At the same time, these systems are becoming more and more sensitive to transient faults originated from a large spectrum of noisy sources such as conducted and radiated Electromagnetic Interference (EMI). Therefore, the system's reliability degrades. In this work, we present a hardware-based infrastructure intellectual property (I-IP) core able to monitor the RTOS' activity in a multicore processor system-on-chip (MPSoC). The final goal is to detect faults that corrupt the task scheduling process in embedded systems based on preemptive RTOS. The I-IP core, namely RTOS-Watchdog (RTOS-WD), was described in VHDL and is connected to the address busses between the cores and their local iCache memories. A case-study based on a MPSoC running different test programs under the control of a typical preemptive RTOS was implemented and exposed to conducted EMI. The obtained results demonstrate that the proposed approach provides higher fault coverage when compared to the native fault detection mechanisms embedded in the kernel of the RTOS. © 2015 ieee.

关键词： system-on-chip

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An Efficient Technique for chip Temperature Optimization of Multiprocessor systems in the Dark Silicon Era 17

An Efficient Technique for Chip Temperature Optimization of ...

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2015 ieee 17th international Conference on High Performance Computing and Communications (HPCC)

作者： Li, Mengquan Yi, Juan Liu, Weichen Zhang, Wei Yang, Lei Sha, Edwin H. M. Chongqing Univ Coll Comp Sci Chongqing Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781479989379

In the dark silicon era, a fundamental problem is: given a real-time computation demand represented by a set of independent applications with their own power consumption, how to determine if an on-chip multiprocessor system is able to respond to this demand and maintain its reliability by keeping every core within the safe temperature range. In this paper, we first present a novel thermal model for the prediction of chip peak temperature assuming the application-to-core mapping is determined. The mathematical model combines linearized steady-state thermal model with empirical scaling factors to achieve significantly improved accuracy and running efficiency. Based on it, a MILP-based approach is presented to find the optimal application-to-core assignment such that the computation demand is met and the chip temperature is minimized. At last, if the minimized temperature still exceeds the safe temperature threshold, a novel heuristic algorithm, called temperature threshold-aware result handling (TTRH), is proposed to drop certain applications selectively from immediate execution, and lower the chip peak temperature to the safety threshold. Extensive performance evaluation shows that the MILP-based approach can reduce the chip peak temperature by 9.1 degrees C on average compared to traditional techniques. TTRH algorithm can further lower the chip peak temperature by 1.38 degrees C on average with the application dropping rate of less than 4.35%.

关键词： Mathematical model Power demand Silicon Temperature Temperature sensors Thermal resistance

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PETS: Power and Energy Estimation Tool at system-Level

PETS: Power and Energy Estimation Tool at System-Level

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15th international symposium on Quality Electronic Design (ISQED)

作者： Rethinagiri, Santhosh-Kumar Palomar, Oscar Unsal, Osman Cristal, Adrian Ben-Atitallah, Rabie Niar, Smail Barcelona Supercomp Ctr Barcelona Spain Univ Valenciennes LAMIH Valenciennes France

ISBN: (纸本)9781479939466

In this paper, we introduce PETS, a simulation based tool to estimate, analyse and optimize power/energy consumption of an application running on complex state-of-the-art heterogeneous embedded processor based platforms. This tool is integrated with power and energy models in order to support comprehensive design space exploration for low power multicore and heterogeneous multiprocessor platforms such as OMAP, CARMA, Zynq 7000 and Virtex II Pro. Moreover, PETS is equipped with power optimization techniques such as dynamic slack reduction and work load balancing. The development of PETS involves two steps. First step: power model generation. For the power model development, functional-level parameters are used to set up generic power models for the different components of the system. So far, seven power models have been developed for different architectures, starting from the simple low power architecture ARM9 to the very complex DSP TI C64x. Second step: a simulation based virtual platform framework is developed using systemC IP's and JIT/ISS compilers to accurately grab the activities to estimate power. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks. Estimated power and energy values are compared to real board measurements. The power estimation results are less than 4% of error for single core processor, 4.6% for dual-core processor, 5% for quad-core, 6.8% multi-processor based system and effective optimisation of power/energy for the applications

关键词： embedded systems low-power electronics multiprocessing systems CARMA DSP TI C64x JIT-ISS compilers OMAP PETS systemC IP Virtex II Pro Zynq 7000 comprehensive design space exploration dual-core processor dynamic slack reduction energy estimation tool functional-level parameters generic power models heterogeneous embedded processor based platforms heterogeneous multiprocessor platforms industrial benchmarks low power architecture ARM9 multicore platforms power estimation tool power optimization techniques quad-core real board measurements single core processor virtual platform framework work load balancing Estimation Hardware Load modeling Optimization Positron emission tomography Process control Solid modeling

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Message from the ieee MCSoC-15 Honorary Chairs

Message from the IEEE MCSoC-15 Honorary Chairs

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ieee international symposium on embedded multicore Socs (MCSoC)

Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.

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