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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Energy and Performance Analysis of STTRAM Caches for Mobile Applications 13

Energy and Performance Analysis of STTRAM Caches for Mobile ...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Kuan, Kyle Adegbija, Tosiron Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781728148823

Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency. Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications. We analyze the characteristics of mobile applications' cache blocks and how those characteristics dictate the appropriate retention time for mobile device caches. We show that due to their inherently interactive nature, mobile applications' execution characteristics-and hence, STTRAM cache design requirements-differ from other kinds of applications. We also explore various STTRAM cache designs in both single and multicore systems, and at different cache levels, that can efficiently satisfy mobile applications' execution requirements, in order to maximize energy savings without introducing substantial latency overhead.

关键词： Spin-Transfer Torque RAM (STTRAM) cache mobile applications performance analysis retention time non-volatile memory energy efficient multicore processor

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Comparative Study on Edge Detection Algorithms using OpenACC and OpenMPI on multicore systems 11

Comparative Study on Edge Detection Algorithms using OpenACC...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Goyal, Aakashdeep Li, Zuqing Kimm, Haklin East Stroudsburg Univ Dept Comp Sci East Stroudsburg PA 18301 USA

ISBN: (纸本)9781538634417

In this paper, we present a comparative study on parallel edge detection algorithms upon high-resolution satellite images, implemented on OpenACC, Hybrid OpenMP/MPI, OpenMP, and MPI models on which the Sobel, Prewitt and Canny algorithms were developed using C++ language and OpenCV. The performance of these computing models were measured in terms of speedup and execution time by implementing the edge detection algorithms using various sized images and programming constructs. The program implementations using OpenACC display the largest speedup in CPU time, which is followed by the Hybrid OpenMP/MPI model. The parallel detection algorithms using OpenACC obtain the greatest speedup of around 6.5 over OpenMP model. The parallel Sobel and Prewitt algorithms are relatively 2 times faster than the Canny in all respects.

关键词： Edge Detection OpenACC OpenMP OpenMPI multicore

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2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection systems on multicores 10

2-Step Power Scheduling with Adaptive Control Interval for N...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Lau Phi Tuong Kimura, Keiji Waseda Univ Dept Comp Sci & Engn Green Comp Syst Res & Dev Ctr Tokyo Japan

ISBN: (纸本)9781509035311

Network intrusion detection system (NIDS) is becoming an important element even in embedded systems as well as in data centers since embedded computers have been increasingly exposed to the Internet. The demand for power budget of these embedded systems is a critical issue in addition to that for performance. In this paper, we propose a technique to minimize power consumption in the NIDS by 2-step power scheduling with the adaptive control interval. In addition, we also propose a CPU-core controlling algorithm so that our scheduling technique can preserve the performance for other applications and NIDS assuming the cases of multiplexing NIDS and them simultaneously on the same device such as a home server or a mobile platform. We implement our 2-step algorithm into Suricata, which is a popular NIDS, as well as a 1-step algorithm with the adaptive interval, and a simple fixed-interval algorithm for evaluations. Experimental results show that our 2-step scheduling with both the adaptive and the fixed 30-millisecond interval achieve 75% power saving comparing with the Ondemand governor and 87% comparing with the Performance governor in Linux, respectively, without affecting their performance capability on four ARM Cortex-A15 cores at the network traffic of 1,000 packets/seconds. In contrast, when the network traffic reaches to 17,000 packets/seconds, our 2-step scheduling and the Ondemand as well as the Performance governor can maintain the packet processing capacity while the fixed 30-milliseconds interval processes only 50% packets with two and three cores, and about 80% packets on four cores.

关键词： Network Intrusion Detection system (NIDS) Dynamic Voltage Frequency Scaling (DVFS) Suricata Data Center

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Parallel Verification in RISC-V Secure Boot 16

Parallel Verification in RISC-V Secure Boot

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Saiki, Akihiro Omori, Yu Kimura, Keiji Waseda Univ Tokyo Japan

ISBN: (纸本)9798350393613

Assuring the reliability of the OS boot process is essential to realize reliable computer systems. Secure Boot enables it by introducing the verification of the boot image with digital signature and hash values. This can be the basis for various security mechanisms. However, Secure Boot requires a long boot time due to their expensive computation costs, resulting in extended downtime. In this paper, we first implement Secure Boot in an ordinary RISC-V boot process on U-Boot, a representative open-source bootloader, and clarify the overhead introduced by the verification process. Based on the insight obtained above, we propose a parallelization of the verification process on a multi-core in Secure Boot. It accelerates the boot process while securely authenticating the boot image. We implement the proposed parallel verification process on U-Boot. The evaluation on a HiFive Unmatched RISC-V board shows that the parallelized hash computation on four cores achieves 3.96 times better performance than the original.

关键词： Parallelization Multi-core Processing RISC-V Secure Boot

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A many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference 16

A Many-core Architecture for an Ensemble Ternary Neural Netw...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Kayanoma, Ryota Jinguji, Akira Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9798350393613

Machine learning is expanding in various applications, such as image processing in data centers. With the spread of deep learning, neural-network-based models have frequently been adopted in recent years. Due to the slow processing speed of machine learning evaluation on a CPU, high-speed, dedicated hardware accelerators are often used. In particular, the demand for hardware accelerators in data centers is increasing, with a need for low power consumption and high-speed processing in a limited space. Here, we propose an implementation method for a ternary neural network, utilizing the rewritable look-up table (LUT) of a field-programmable gate array (FPGA). Ternary neural networks (TNNs), quantized to 2 bits, can be realized with LUT-based combinational circuits, allowing inference processing in a single cycle. Thus, a very high-speed inference system can be realized. Moreover, we have reduced the hardware quantity by 70% by introducing sparsity, i.e., approximating the parameters to zero. However, there was a downside of reduced recognition accuracy due to the low-bit representation. In this paper, we used an ensemble to achieve recognition accuracy equivalent to that of the 32-bit float model to prevent the decrease in recognition accuracy. We also designed a voting circuit for the ensemble TNN that does not decrease throughput. By implementing it on the AMD Alveo U50 FPGA card, we achieved a high processing speed of 100 Mega Frames Per Second (MFPS). Our FPGA-based system was 1,286 times faster than the CPU and 1,364 times faster than the GPU. Therefore, we achieve a high-speed inference system without compromising recognition accuracy.

关键词： Ensemble nueral network FPGA many core Neural Network

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Real-time UAV Attitude Heading Reference system Using Extended Kalman Filter for Programmable SoC 11

Real-time UAV Attitude Heading Reference System Using Extend...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Mie, Shunsuke Okuyama, Yuichi Sato, Yusuke Chan, Ye Dang, Nam Khanh Abderazek, Ben Abdellash Univ Aizu Grad Sch Comp Sci & Engn Aizu Wakamatsu Fukushima Japan Univ Yangon UniversitiesRes Ctr Yangon Myanmar

ISBN: (纸本)9781538634417

We implemented an extended Kalman filter (EKF) hardware for a real-time attitude heading reference system (AHRS). Attitude estimation is an important process for small unmanned aerial vehicle (UAV) control. Small UAVs mounts smaller sensors due to the limitation of space and power. However, effects of noise components in sensor output become large if the size of sensors become smaller. We considered using EKF to reduce effects of noises by sensor fusion. Moreover, real-time and highly accurate attitude estimation is required for an autonomous flight of UAVs. To reduce loads of processors in a real-time calculation of EKF, we implemented a circuit of EKF by C-based hardware design in Programmable SoC. We achieved five times faster EKF processing on FPGA than the processing on ARM Cortex-A9@677Hz with single core processing.

关键词： Attitude Heading Reference system Extended Kalman Filter FPGA C-based hardware design

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Runtime support for automatic placement of workloads on heterogeneous processors 16

Runtime support for automatic placement of workloads on hete...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Benoit, Nicolas Louise, Stephane Sorbonne Univ 4 Pl Jussieu F-75252 Paris 05 France Univ Paris Saclay CEA LIST F-91120 Palaiseau France

ISBN: (纸本)9798350393613

In order to maintain the continuous growth of the performance of computers while keeping their energy consumption under control, the microchip industry develops architectures capable of processing more and more tasks concurrently. Thus, the upcoming generations of processors may count hundreds of independent processing elements that may differ in their functions and features. As an extensive knowledge of their internals cannot be a prerequisite to their programming, and for the sake of portability, these forthcoming computers necessitate the compilation flow to evolve. In this article, we aim to explore solutions to several challenges that awaits the programming tools of such emerging architectures: by relying on a compilation tool to extract and characterize several levels of execution granularity available in a program, we aim at mapping the detected parallelism on the cores of the system taking into account the costs of communication, managing the execution scheduling in an effective way. Most of that should be amenable without much help or tips from the programmer, and more importantly without over-specializing the source code toward a given architecture. One code should fit for all with a desired performance close enough to hand tuned code so that most of programmer would not have to consider to hand-tune a code. An evaluation is done on an old school Cell-BE processor from the PS3 era to check feasibility on a heterogeneous platform. We show we can obtain performance which can surpass state of the art Cell-BE parallel frameworks.

关键词： heterogeneous computing many-core processors Programming runtime

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Full-system Simulation of *** multicore Architecture for Performance and Energy Exploration 10

Full-System Simulation of *** Multicore Architecture for Per...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Butko, Anastasiia Bruguier, Florent Gamatie, Abdoulaye Sassatelli, Gilles Novo, David Torres, Lionel Robert, Michel CNRS LIRMM Montpellier France Univ Montpellier Montpellier France

ISBN: (纸本)9781509035311

Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big. LITTLE. These processors offer increased energy efficiency through combining low power in-order cores with high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so as to meet the demands of targeted applications. In this paper, we explore the design of those architectures based on the ARM *** technology by modeling performance and power in gem5 and McPAT frameworks. Our models are validated w.r.t. the Samsung Exynos 5 Octa (5422) chip. We show average errors of 20% in execution time, 13% for power consumption and 24% for energy-to-solution.

关键词： Full-system simulation single-ISA heterogeneous multicore gem5 McPAT performance energy accuracy ARM big.LITTLE

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Lightweight Semantics-Preserving Communication for Real-Time Automotive Software 13

Lightweight Semantics-Preserving Communication for Real-Time...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Yip, Eugene Lalo, Erjola Luettgen, Gerald Sailer, Andreas Univ Bamberg Software Technol Res Grp D-96045 Bamberg Germany Vector Informatik GmbH D-93053 Regensburg Germany

ISBN: (纸本)9781728148823

The automotive industry is confronting the multi-core challenge, where legacy and modern software must run correctly and efficiently in parallel, by designing their software around the Logical Execution Time (LET) model. While such designs offer implementations that are platform independent and time predictable, task communications are assumed to complete instantaneously. Thus, it is critical to implement timely data transfers between LET tasks, which may be on different cores, in order to preserve a design's data-flow. In this paper, we develop a lightweight Static Buffering Protocol (SBP) that satisfies the LET communication semantics and supports signal-based communication with multiple signal writers. Our simulation-based evaluation with realistic industrial automotive benchmarks shows that the execution overhead of SBP is at most half that of the traditional Point-To-Point (PTP) communication method. Moreover, SBP needs on average 60% less buffer memory than PTP.

关键词： buffering protocol logical execution time multi-core

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Board Allocation Algorithm for the Resource Management system of FiC 16

Board Allocation Algorithm for the Resource Management Syste...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Inage, Takumi Iizuka, Kensuke Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan

ISBN: (纸本)9798350393613

When using FPGA clusters for Multi-access Edge Computing (MEC), some tasks need multiple FPGA boards, so it is necessary to allocate each task to several boards that are not currently in use on the FPGA cluster. In order to maintain constant communication bandwidth and latency, we should allocate them in contiguous areas of a group of FPGAs. The current task allocation method for our FPGA clusters searches for Maximum Empty Rectangles (MER) based on Scan Line Algorithm (SLA). However, in this algorithm, the allocation target is restricted to a rectangular shape, which makes the cluster utilization inefficient. In this paper, we devise a more flexible algorithm called Non-Rectangular (NR) allocation and attempt to improve allocation efficiency. NR allocation provides the hybrid method, which chooses column-major allocation and row-major allocation. By using this proposed hybrid method, we have made it possible to allocate non-rectangular areas while maintaining contiguous regions by considering the board's position after allocation. Simulation results show a 42% improvement in the total waiting time compared to the conventional method.

关键词： FPGA cluster Multi-access Edge Computing Resource allocation Resource management multi-FPGA

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