检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,186 篇 会议
21 篇 期刊文献

馆藏范围

1,207 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

634 篇 工学
- 484 篇 计算机科学与技术...
- 339 篇 电气工程
- 170 篇 软件工程
- 103 篇 电子科学与技术（可...
- 58 篇 控制科学与工程
- 40 篇 信息与通信工程
- 18 篇 仪器科学与技术
- 15 篇 动力工程及工程热...
- 14 篇 机械工程
- 14 篇 材料科学与工程（可...
- 7 篇 生物工程
- 7 篇 安全科学与工程
- 5 篇 光学工程
- 5 篇 化学工程与技术
- 4 篇 环境科学与工程（可...
- 4 篇 生物医学工程（可授...
- 3 篇 冶金工程
- 3 篇 建筑学
- 3 篇 土木工程
- 3 篇 石油与天然气工程
63 篇 理学
- 26 篇 数学
- 19 篇 物理学
- 15 篇 系统科学
- 8 篇 生物学
- 4 篇 化学
45 篇 管理学
- 39 篇 管理科学与工程(可...
- 10 篇 工商管理
- 5 篇 图书情报与档案管...
6 篇 法学
- 4 篇 社会学
4 篇 经济学
- 4 篇 应用经济学
3 篇 农学
2 篇 医学
1 篇 文学

主题

400 篇 multicore proces...
160 篇 hardware
145 篇 system-on-chip
83 篇 computer archite...
77 篇 embedded systems
70 篇 system-on-a-chip
62 篇 program processo...
58 篇 computational mo...
57 篇 real-time system...
53 篇 field programmab...
47 篇 benchmark testin...
46 篇 throughput
46 篇 random access me...
44 篇 kernel
42 篇 memory managemen...
40 篇 power demand
38 篇 instruction sets
37 篇 parallel process...
37 篇 energy consumpti...
37 篇 multiprocessing ...

机构

5 篇 tampere universi...
5 篇 school of comput...
5 篇 department of in...
5 篇 institute for co...
5 篇 department of co...
4 篇 national institu...
4 篇 univ grenoble al...
4 篇 infineon technol...
4 篇 engineering prod...
4 篇 department of co...
4 篇 tokyo inst techn...
4 篇 school of comput...
3 篇 univ siegen chai...
3 篇 school of comput...
3 篇 singapore univer...
3 篇 dept. of informa...
3 篇 graduate school ...
3 篇 international co...
3 篇 chiba univ grad ...
3 篇 eecs department ...

作者

10 篇 benini luca
10 篇 hideharu amano
9 篇 kise kenji
8 篇 nurmi jari
8 篇 hamada mohamed
8 篇 amano hideharu
7 篇 mohamed hamada
7 篇 luca benini
6 篇 obermaisser roma...
6 篇 kenji kise
5 篇 pasi liljeberg
5 篇 roman obermaisse...
5 篇 t. hui teo
5 篇 marongiu andrea
5 篇 yuichi okuyama
5 篇 jungpil shin
4 篇 hiroki matsutani
4 篇 hannu tenhunen
4 篇 goehringer diana
4 篇 dutt nikil

语言

1,201 篇 英文
5 篇 中文
1 篇 其他

检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

共 1207 条记录，以下是61-70 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A low cost and portable mini motor car system with a BNN accelerator on FPGA 14

A low cost and portable mini motor car system with a BNN acc...

引用

14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hamanaka, Fumio Kanamori, Takuto Kise, Kenji Tokyo Inst Technol Sch Comp Tokyo Japan

ISBN: (纸本)9781665438605

To realize autonomous driving, a deep neural network (DNN) is one of the key technologies. However, since DNN needs a lot of computation, it is challenging for an edge device to support DNN with limited computation resources. A binarized neural network (BNN) has been proposed to reduce latency and parameter size and is suited for hardware implementation. Since current DNN technology is a growing and better algorithm change with time, implementing DNN on an FPGA is preferable to an ASIC. In this paper, we propose a low cost and portable mini motor car system with a BNN accelerator on an FPGA. We compare the road tracking demonstration with a similar motor car using Raspberry Pi and show the effectiveness of FPGA in a DNN implementation. The proposed system is implemented on Nexys A7, one of the most popular FPGA development boards using an Artix-7 FPGA.

关键词： BNN FPGA Verilog HDL Motor car Artix-7

来源：评论

学校读者我要写书评

暂无评论

Integrating Intra- and Intercellular Simulation of a 2D HL-1 Cardiac Model based on embedded GPUs 13

Integrating Intra- and Intercellular Simulation of a 2D HL-1...

引用

ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Liu, Baohua Shen, Wenfeng Zhu, Xin Wangchen, Xingyu Shanghai Univ Sch Comp Engn & Sci Shanghai Inst Adv Commun & Data Sci Shanghai Peoples R China Univ Aizu Biomed Informat Technol Lab Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9781728148823

Simulation of electrophysiological cardiac models enables researchers to investigate the activity of heart under various circumstances. Fortunately, recent development in embedded parallel computing architectures has made it possible for one to efficiently simulate sophisticated electrophysiological models that match up to real conditions on embedded computing devices, which typically relies on large scale CPU or GPU clusters in the past. In this paper, a simultaneous implementation of a 2D Takeuchi-HL-1 cardiac model combining unicellular and intercellular solver is proposed and conducted on NVIDIA Jetson Tegra X2 embedded computer. The experiment results demonstrate that our implementation yields considerable efficiency improvement compared with that using non-simultaneous methods, without loss of simulation accuracy. Moreover, it's also proved that embedded devices are much more energy-efficient than conventional systems on the simulation.

关键词： Takeuchi-HL-1 Electrophysiology Parallelization Scheduling

来源：评论

学校读者我要写书评

暂无评论

Trends and Challenges in Ensuring Security for Low-Power and High-Performance embedded SoCs 14

Trends and Challenges in Ensuring Security for Low-Power and...

引用

14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Rahimi, Parisa Singh, Amit Kumar Wang, Xiaohang Prakash, Alok Univ Essex Colchester Essex England South China Univ Technol Guangzhou Peoples R China Nanyang Technol Univ Singapore Singapore

ISBN: (纸本)9781665438605

In recent years, security, power consumption, and performance have become the important issues in embedded SoCs' design. With the growing number of embedded devices for automotive electronic and electric vehicles, real-time systems, robotics, artificial intelligence, smart technologies, or telecommunication, it is highly likely that these systems will be exposed to attacks or threats. Therefore, it is not easy to implement the security measure of such devices, and it becomes challenging while considering the performance and power issues due to limited available computing resources and often operating on batteries. In this paper, we survey the weaknesses of the embedded SoCs and examine the attacks, power consumption, and performance more closely with the main focus on Physical and Side-Channel attacks, which have not been surveyed previously. Along with the current trends and challenges, upcoming trends and challenges are also elaborated. This paper is intended to help the researchers and system designers in gaining deep insight into designing secure, power-efficient, and high-performance embedded SoCs in the future.

关键词： embedded system Physical and Side-channel attacks Power Optimization High performance Multi-core systems

来源：评论

学校读者我要写书评

暂无评论

A Multi-scale Binarized Neural Network Application based on All programmable system on chip 14

A Multi-scale Binarized Neural Network Application based on ...

引用

14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Xiang, Maoyang Teo, T. Hui Singapore Univ Technol & Design Engn Prod Dev Singapore Singapore Singapore Univ Technol & Design Sci Math & Technol Cluster Engn Prod Dev Singapore Singapore

ISBN: (纸本)9781665438605

Binary neural networks (BNNs) are particularly well-suited for low-power embedded devices with limited computational capabilities. Due to the binary weight parameters, it significantly reduces memory footprint and arithmetic logic unit operations. Nevertheless, one of the disadvantages of BNN is low accuracy and sharp optimization space. Several studies of BNNs have recently shown improved accuracy in various tests via more operations and more complicated topologies. This approach, however, is incompatible with the embedded BNN application since it requires complicated data type translation. Hence, We propose a novel approach for the BNN application on the embedded system with multi-scale neural network topology in this research from two optimization perspectives: hardware structure and BNN topology, which preserves more low-level information during the feed-forward process with few operations. Our network topology achieves 91.3% accuracy for the CIFAR-10 dataset, one of the highest recorded by BNN and can process 537 tiny pictures per second when deployed on an All programmable system on chip (APSoc) device with 4.4W power consumption.

关键词： binarized neural networks bit-wise operation All programmable system on chip

来源：评论

学校读者我要写书评

暂无评论

Network on chip and parallel computing in embedded systems 10

Network on chip and parallel computing in embedded systems

引用

10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Belkacemi, Dihia Bouchebaba, Youcef Daoui, Mehammed Lalam, Mustapha Univ Tizi Ouzou Lab Rech Informat Tizi Ouzou Algeria ONERA Toulouse Toulouse France

ISBN: (纸本)9781509035311

In order to cope with the increasing application requirements, heterogeneous MPSoC are considered as the major solution of future embedded systems thanks to their advantages in performance and low power dissipation. However traditional communication infrastructure such as a bus or a point to point are not scalable and become communication bottleneck for large systems. Network on chip (NoC) architectures have been proposed to handle this communication problem. One of the most critical problem in NoC based heterogeneous MPSoC is how to map an application on this platform. Due to the large solution search space, design of tools that can automate this step is of major importance. In this paper, we present a new tool for mapping applications on NoC based heterogeneous MPSoC. A set of multi-objective optimization algorithms are used to explore the mapping space and to find a set of Pareto optimal solutions.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

Adaptive V-Set Cache for Multi-core Processors 8

Adaptive V-Set Cache for Multi-core Processors

引用

8th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： El-Moursy, Ali A. Univ Sharjah Dept Elect & Comp Engn Sharjah U Arab Emirates

ISBN: (纸本)9781479943050

Development in VLSI design allows multi-to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the Last Level Cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput due to the increasing gap between processor speed and memory speed. In this paper the author proposes distributed-shared v-set cache design that allows an adaptive and dynamic utilization of the cache blocks across the cores while keeps the h/w complexity, which reflects on the system scalability, matching the partitioned design. On four-core microprocessor, the proposed distributed-shared v-set cache design can achieve a maximum speedup of 25%, 15%, and 21% and an average speedup of 12%, 5%, and 9% compared to conventional partitioned-private cache, monolithic shared cache, and private/shared NUCA cache designs respectively.

关键词： Adaptive cache Cache design Multi-core NUCA

来源：评论

学校读者我要写书评

暂无评论

Hypervisor-Induced Negative Interference in Virtualized Multi-core Platforms: The P4080 Case 11

Hypervisor-Induced Negative Interference in Virtualized Mult...

引用

11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Dutta, Sourav Kagaris, Dimitri Ramaprasad, Harini Southern Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA Univ N Carolina Dept Comp Sci Charlotte NC USA

ISBN: (纸本)9781538634417

Modern real-time (RT) applications heavily depend on multi-core processors to meet the increasing computing demands within strict time-constraints. To reduce the cost of overall hardware, most of these applications run along with general purpose workloads on the same hardware platform which may create data contention in shared resources and incur delay for the time critical RT applications. Virtualization of the hardware platform under the supervision of a Virtual Machine Monitor (VMM) or hypervisor allows the isolation of shared resources among concurrent applications from different domains. However, the actual partitioning of hardware resources among the hosted operating systems as well as the hypervisor play a significant role in the performance of the RT applications. In this paper we report results of an experimental investigation for this purpose on a particular multi-core platform, the P4080 developed by Freescale Semiconductor Inc. Using the actual (not simulated) P4080 hardware platform and the Topaz hypervisor, we examined the effect that the partition of the last-level cache (LLC) among a Real-Time Operating system (RTOS), a General Purpose Operating system (GPOS) and the hypervisor has on the performance of the RT tasks. We have identified inverted bell-shaped curves that seem to govern the optimal allocation of resources for P4080.

关键词： Virtual machine monitors Hardware Operating systems Interference Task analysis Time factors Real-time systems Virtual machine monitors Operating systems task analysis Time Factors real-time systems Hardware Platform Computer hardware Resource utilization general purpose operating system interference Room temperature centromere interference

来源：评论

学校读者我要写书评

暂无评论

MSCU: Accelerating CNN Inference with Multiple Sizes of Compute Unit on FPGAs 14

MSCU: Accelerating CNN Inference with Multiple Sizes of Comp...

引用

14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Bao Zhenshan Guo Junnan Li Xiaqing Zhang Wenbo Beijing Univ Technol Fac Informat Technol Beijing Peoples R China

ISBN: (纸本)9781665438605

The FPGA-based accelerators have shown great potential in improving the performance of CNN inference. However, the existing FPGA-based approaches suffer from a low Compute Unit (CU) efficiency due to a large amount of invalid computation, thus leading to a great performance degradation. In this paper, we find that no single CU can perform the best across all the convolutional layers (Conv-layers). To this end, we propose multiple sizes of compute unit (MSCU), an approach to accelerating CNN inference on FPGAs. The key idea of MSCU is to select the best combination of CUs via dynamic programming scheduling for each Conv-layer, and then assembles each Convlayer combination into a computing solution of the given CNN to deploy on FPGAs. The experimental results show that MSCU can achieve 3.36E-03 GOPs/Slice on Xilinx Zynq ZU3EG for performance density which is 4.29x higher than other approaches.

关键词： Degradation Processor scheduling multicore processing Dynamic scheduling Dynamic programming Computational efficiency Copper

来源：评论

学校读者我要写书评

暂无评论

High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture 10

High-Precision Power Modelling of the Tegra K1 Variable SMP ...

引用

10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Stokke, Kristoffer Robin Stensland, Hakon Kvale Halvorsen, Pal Griwodz, Carsten Simula Res Lab Oslo Norway Univ Oslo Oslo Norway

ISBN: (纸本)9781509035311

Energy efficiency is an important issue for many embedded systems, where limited battery lifetime and power-hungry hardware constrain the usefulness of such devices. Modern systems-on-chip (SoCs) such as the Tegra K1 employ advanced power management capabilities such as two CPU clusters, clock-gating, power-gating and dynamic frequency tuning to meet application demands. At design or runtime phases, it is challenging for system architects and software developers to understand the effects that these mechanisms have in terms of power and performance in all parts of the system. This is because it is impossible to measure directly the power usage of cores, caches, memory and other hardware components. Rate-based power models are often proposed as a solution for this, unfortunately these can mispredict substantially on the Tegra K1 up to 30 %. In this paper, we propose a power modelling method for the Tegra K1 CPU which overcomes the limitations of the most common types of models found in literature, but still only requires power measurement of the board. Through extensive empirical validation, we demonstrate an accuracy which is close to 100 %. Preliminary experiments show that our methodology is able to capture instruction power of individual system processes and applications and produce detailed power breakdowns of all components in the system.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Supporting Static Binding in Stream Rewriting for Heterogeneous many-core Architectures 10

Supporting Static Binding in Stream Rewriting for Heterogene...

引用

10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Middendorf, Lars Haubelt, Christian Univ Rostock Rostock Germany

ISBN: (纸本)9781509035311

Heterogeneous multi and many-core systems offer numerous benefits like reduced energy consumption and improved throughput for both high-performance and low-power applications. However, beside the design of the actual hardware architecture, also the programming of many-core systems raises several challenges. For this purpose, we extend the existing concept of stream rewriting into a model of computation for the specification of highly concurrent applications on heterogeneous systems. In particular, our approach permits to partition the stream and to bind different sections to specialized hardware components. Since stream rewriting manages a large number of active tasks without a central scheduler, we can perform the distribution and synchronization of work-items asynchronously to improve hardware utilization. Several case studies using an FPGA prototype demonstrate the scalability of our approach.

关键词： hardware rendering shader stream rewriting streaming

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共121页 << < 3 4 5 6 7 8 9 10 11 12 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：