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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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Top-down profiling of application specific many-core neuromorphic platforms 9

Top-down profiling of application specific many-core neuromo...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Urgese, Gianvito Barchi, Francesco Macii, Enrico Politecn Torino Dept Control & Comp Engn DAUIN Cso Duca degli Abruzzi 24 I-10129 Turin Italy

ISBN: (纸本)9781479986705

In this paper we present a top-down methodology aimed at evaluating the scalability of Spiking Neural Network (SNN) simulations on massively many-core and densely interconnected platforms. Spiking neural networks mimic brain activity by emulating spikes sent among neurons populations. many-core platforms are emerging computing targets to achieve real-time simulation SNN. Neurons are mapped to parallel cores and spikes are sent over the on-chip and off-chip network. However, due to the heterogeneity and complexity of neuron population activity, achieving an efficient exploitation of platforms resources is a challenging problem, often impacting simulation reliability and limiting the biological network size. To address this challenge, the proposed methodology, based on customized SNN configurations, extracts detailed profiling information about network usage of on-chip and off-chip resources. We first show the results of the application of our methodology to the SpiNNaker neuromorphic many-core platform. Then, we demonstrate how the profiling information can be used to improve the reliability of biologically plausible SNN simulations.

关键词： multiprocessing systems neural nets SNN configuration SpiNNaker neuromorphic many-core platform application specific many-core neuromorphic platform biologically plausible SNN simulation densely interconnected platforms neuron population activity spiking neural network top-down profiling Analytical models Biological system modeling Brain modeling Neurons Routing Sociology Statistics many-core Multi-chip Neuromorphic Profiling Neural network Brain modeling Biological system modeling Multiprocessing systems Neuromorphics Sociology ANALYSIS MODELS Neurons Network routing SNN gene Platform

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multicore Power Estimation using Independent Component Analysis based Modeling 13

Multicore Power Estimation using Independent Component Analy...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Sagi, Mark Nguyen Anh Vu Doan Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Chair Integrated Syst Munich Germany

ISBN: (纸本)9781728148823

State-of-the-art power estimation research for multi-core processors combine performance counters that collect runtime activity information with an offline-generated power model. To generate these power models, the package power is measured and the activity information is traced while synthetic workloads are executed. These workloads stress distinct core components in order to expose power responses so that the activity information has low collinearity. The measurements are then combined into a power model describing the general power behavior. However, one of the main drawbacks of these synthetic workloads is that they are most of the time custom-designed for a given multi-core architecture and are hardly available. In this paper, we present a methodology to generate power models using freely available benchmarks, e.g. PARSEC/Splash-2. To minimize the collinearity of the activity information due to the uncontrolled/unspecified behavior of these more general benchmarks, we propose to use independent component analysis. This allows to avoid the use of synthetic workloads and a reduction of the relative error by 24% in the average case, when compared to prior state-of-the-art work. Although, we also observe an increase of 22% relative error in the worst case for our approach, this can easily be improved by using either different or more training benchmarks. These promising results give a strong indication that independent component analysis could directly be used with real application workload, leading to the possibility to build/improve power models during runtime.

关键词： multicore power estimation performance counters independent component analysis accuracy

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Enhancing Road Safety with Cloud-Integrated IoT Road Signal Detection system. 16

Enhancing Road Safety with Cloud-Integrated IoT Road Signal ...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hitayezu, Antoine Umutoni, Ritha Marie Tuyishime, Emmanuel Jayavel, Kayalvizhi Kabiri, Charles Univ Rwanda Dept African Ctr Excellence Internet Things Kigali Rwanda Transilvania Univ Brasov Dept Elect & Comp Brasov Romania Univ Arts Dept Creat Comp Inst London England

ISBN: (纸本)9798350393613

In our modern society, the imperative of road safety, crucial for mitigating vehicular accidents, stands as a pivotal goal, as it directly correlates with the prevention of loss of both human life and valuable property. Addressing this imperative, we propose an IoT-integrated Road Signal Detection system for Automatic Speed Control. The system leverages GPS and real-time communication to enhance road safety. By discerning speed limits from roadside signals using GPS coordinates, our system promptly notifies the vehicle occupants through intuitive alerts, creating an instant awareness of the permissible speed and prompting the driver to take corrective actions. Our study focuses on public and private transportation as well as goods carriers. Technical implementation involves the strategic integration of central component, NodeMCU (ESP8266) microcontroller orchestrates the system's operations, acting as the nerve center that governs all functionalities. In addition, a GPS device accurately pinpoints the coordinates of relevant traffic signs, while a GSM module facilitates seamless communication between moving vehicles and the registered traffic sign locations. The proposed solution promises timely alerts, mitigating accidents due to high-speed driving and averting unanticipated fines. This research contributes to reshaping road safety measures, fostering responsible driving behavior, and potentially curbing accidents.

关键词： Speed limit NodeMCU GPS IoT

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A function-rich FPGA system of camera image processing for video meeting 14

A function-rich FPGA system of camera image processing for v...

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14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Odan, Takashi Kanamori, Takuto Kise, Kenji Tokyo Inst Technol Sch Comp Tokyo Japan

ISBN: (纸本)9781665438605

A video conference is used as a means of meeting in remote places for research and education purposes. The video conference system provides some enhanced functions, such as virtual background function, slide sharing function, nonverbal feedback function. However, there is a problem that some computers cannot support such functions because the video conference system may require high-performance processors and the latest software stacks. In this paper, we describe a function-rich web camera system using an FPGA. We design and implement the core module named video processing module (VPM) for video processing. VPM provides various video processing functions such as virtual background, displaying messages, and the resize of the human face suitable for video meetings. We show that our camera system can be implemented using a low-end FPGA. Our evaluations show that our camera system is 11.7 times lower latency against a software implementation, providing rich functions with high frame rates at 60fps of 1280x720 pixels.

关键词： FPGA video processing real-time video conferencing

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Parallel Longest Common Sequence Algorithm on multicore systems Using OpenACC, OpenMP and OpenMPI 11

Parallel Longest Common Sequence Algorithm on Multicore Syst...

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11th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Li, Zuqing Goyal, Aakashdeep Kimm, Haklin East Stroudsburg Univ Penn Dept Comp Sci East Stroudsburg PA 18301 USA

ISBN: (纸本)9781538634417

The longest common subsequence (LCS) problem is one of the most useful algorithms being applied in various research areas. This problem is known to be NP-hard for arbitrary data. In this paper, we present a parallel LCS algorithm using the GPU-based OpenACC model, which is based on the existing dynamic approach and parallel anti-diagonal scheme that is applied in order to eliminate the data dependencies. The proposed algorithm in this paper has been benchmarked using four different computing models: OpenMPI, OpenMP, hybrid OpenMPI & OpenMP, and OpenACC model. The parallel LCS algorithm has been implemented using Swiss-Prot databases over these computing models, so that their execution times, speed-ups and speed-ratios have been measured and analogized among them extensively. Our experimental results reveal that the computation of our algorithm on OpenACC (on GPU) is around 16 times faster than the execution on a single CPU, and around 2 times faster than on the octa-core processor systems. The performance of the OpenACC model stands out among the four tested models in solving the LCS problem.

关键词： Heuristic algorithms Dynamic programming Graphics processing units Computational modeling Programming multicore processing Parallel algorithms Computational modeling Parallel algorithms Heuristic algorithms dynamic programming Programming Graphics Processing Unit LCS1 gene Legal Executions Parallel Lines Multi-core processors algorithms

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Scalable Dynamic Task Scheduling on Adaptive many-core 12

Scalable Dynamic Task Scheduling on Adaptive Many-Core

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Venkataramani, Vanchinathan Pathania, Anuj Shafique, Muhammad Mitra, Tulika Henkel, Joerg Natl Univ Singapore Sch Comp Singapore Singapore Karlsruhe Inst Technol Chair Embedded Syst Karlsruhe Germany Vienna Univ Technol TU Wien Inst Comp Engn Vienna Austria

ISBN: (纸本)9781538666890

Workloads from autonomous systems project an unprecedented processing demand onto their underlying embedded processors. Workload comprises of an ever-changing mix of multitudes of sequential and parallel tasks. Adaptive many-core processors with their immense yet flexible processing potential are up to the challenge. Adaptive many-core house together tens of base cores capable of forming more complex cores at run-time. Adaptive many-cores, therefore, can accelerate both sequential and parallel tasks whereas non-adaptive many-cores can only accelerate the latter. Adaptive many-cores can also reconfigure themselves to conform to the needs of any workload whereas non-adaptive many-cores - homogeneous or heterogeneous - are inherently limited given their immutable design. The accompanying qualitative schedule is the key to achieving the real potential of an adaptive many-core. The scheduler must move base cores between tasks on the fly to meet the goals of the overlying autonomous system. The scheduler also needs to scale up with the increase in the number of cores in adaptive many-cores without making compromises on the schedule quality. We present a near-optimal distributed scheduler for maximizing performance on adaptive many-cores. We also introduce an online performance prediction technique for adaptive many-cores that enable the proposed scheduler to operate without any task profiling.

关键词： Task analysis Dynamic scheduling multicore processing Adaptation models Out of order Benchmark testing

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Design of a Nonvolatile-Neural-Network-Accelerator-embedded Edge-IoT Device and Its Hardware Emulation 16

Design of a Nonvolatile-Neural-Network-Accelerator-Embedded ...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Sato, Ken Suzuki, Daisuke Univ Aizu Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9798350393613

Edge-IoT device with AI accelerator has advantages such as increased processing speed and more robust security, however, it has disadvantages such as limited resources and high power consumption during standby state caused by leakage current to retain internal data. To solve this issue, a nonvolatile-logic-based edge-IoT device which includes not only a nonvolatile AI accelerator but also a power management unit (PMU) and CPU is proposed and its functional behavior is emulated on a field-programmable gate array (FPGA). The use of the nonvolatile AI accelerator makes it possible to shorten the inference time and immediately fall into a power-off state without losing internal data, which results in great energy saving. The combination of the CPU with the PMU makes it possible to perform software-level management of the operation and power supply for the AI accelerator. As a typical design example, the proposed edge-IoT device which includes a binary convolutional neural network (BCNN) accelerator for digit recognition is designed and its function is emulated on a Digilent Basys3 FPGA board. The estimation result shows that the total energy for the periodical inference (1 image per 100 mu s) of the proposed edge-IoT device is reduced by 92% compared to that of a volatile edge-IoT device with a slight hardware overhead.

关键词： Nonvolatile logic FPGA Binary convolutional neural network IoT Edge computing

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Expandable chip Stacking Method for many-core Architectures Consisting of Tiny chips 9

Expandable Chip Stacking Method for Many-Core Architectures ...

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9th ieee international symposium on embedded multicore/manycore systems-on-chip (MCSoC)

作者： Nakahara, Hiroshi Ozaki, Tomoya Matsutani, Hiroki Koibuchi, Michihiro Amano, Hideharu Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informatcs Chiyoda Ku Tokyo Japan

ISBN: (纸本)9781479986705

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large system-on-chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling Thruchip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

关键词： multiprocessing systems system-on-chip NAS parallel benchmark SoC TCI deadlock-free routing design expandable chip stacking method inductive coupling thruchip interface interchip communication many-core architecture staggered stacking method Coils Network topology Routing Stacking system recovery Three-dimensional displays Topology Inductive coupling interconnect Interconnection network system-on-chip Stacking core construction three-dimensional displays system recovery Multiprocessing systems Haptocorrin Interconnection networks Computer chips Network topology Coils Network routing topology DNA Microarrays

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Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor 10

Optimizing Latencies and Customizing NoC of Time-Predictable...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Salcic, Zoran Nadeem, Muhammad Park, Heejong Teich, Juergen Univ Auckland Dept Elect & Comp Engn Auckland New Zealand Friedrich Alexander Univ Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781509035311

The Time-Predictable Heterogeneous multicore Processor (TP-HMP) is based on a NoC and fully implemented in a standard FPGA chip. The NoC uses TDMA-MIN interconnect with bounded latency, high throughput and low implementation cost. TP-HMP is used for execution of programs written in concurrent GALS language systemJ suited for both soft and hard real-time systems. It uses two types of cores in different configurations and is suitable for static analysis of schedules that implement the program control flow and concurrency. The configuration and number of cores of both types used to achieve specific performance measures can be tailored/optimized for a given application. In this paper we focus on optimization of latency of TDMA-MIN NoC, which also results in mapping of processor cores on physical ports of NoC and optimal TDMA round. We also analyze the performance of TP-HMP execution of the benchmark program used in industrial automation case study.

关键词： NoC optimal latency multicore FPGA systemJ

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On-chip Lifetime Prediction for Dependable many-Processor SoCs Based on Data Fusion 12

On-Chip Lifetime Prediction for Dependable Many-Processor So...

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ieee 12th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Ali, Ghazanfar Pathrose, Jerrin Kerkhoff, Hans G. Univ Twente CTIT Res Inst Testable Design & Test Integrated Syst TDT Grp Enschede Netherlands

ISBN: (纸本)9781538666890

The developments in technology and complexity of many-processor systems-on-chips emerge at a very rapid pace as is their introduction in safety-critical applications, for instance the transport sector. The inherent decrease in dependability of these complex nanosystems must be compensated by counter measures. One promising approach is the usage of IJTAG-compatible embedded instruments in and around cores, monitoring the "health" of target processors. It has been anticipated that these instruments will be (primarily) used for reducing the cost of final testing. In case of degradation during life time, however, they can be reused and counteractions like run-time remapping can be carried out. In this paper, the on-line data of two types of embedded instruments will be used for the prognostics, a slack-delay monitor and an IDDX monitor. Their (correlated) data is being fused which enables a more accurate life-time prediction as compared to a single monitor approach. However, the computational requirements for the embedded dependability manager will increase to enable handling embedded instrument data fusion and/or multi-parameter life-time prediction.

关键词： MPSoC Prognostics system awareness fusion IJTAG embedded instruments IDDX and slack-delay monitors test

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