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检索条件"任意字段=IEEE International Symposium on Embedded Multicore/Many-core System-on-Chip"

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An Automatic MPI Process Mapping Method Considering Locality and Memory Congestion on NUMA systems 13

An Automatic MPI Process Mapping Method Considering Locality...

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ieee 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Agung, Mulya Amrizal, Muhammad Alfian Egawa, Ryusuke Takizawa, Hiroyuki Tohoku Univ Grad Sch Informat Sci Sendai Miyagi Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi Japan Tohoku Univ Cybersci Ctr Sendai Miyagi Japan

ISBN: (纸本)9781728148823

MPI process mapping is an important step to achieve scalable performance on non-uniform memory access (NUMA) systems. Conventional approaches have focused only on improving the locality of communication. However, related studies have shown that on modern NUMA systems, the memory congestion problem could cause more severe performance degradation than the locality problem because a high number of processor cores in the systems can cause heavy congestion on shared caches and memory controllers. To optimize the process mapping, it is necessary to determine the communication behavior of the MPI processes. Previous methods rely on offline profiling to analyze the communication behavior, which incurs a high overhead and is potentially time-consuming. In this paper, we propose a method that automatically performs MPI process mapping for adapting to communication behaviors while considering both locality and memory congestion. Our method works at runtime during the execution of an MPI application. It does not require modifications to the application, previous knowledge of the communication behavior, or changes to the hardware and operating system. The proposed method has been evaluated with the NAS parallel benchmarks on a NUMA system. Experimental results show that our method can achieve performance close to an oracle-based mapping method with low overhead to the application execution. The performance improvement is up to 27.4% (13.4% on average) compared with the default mapping of the MPI runtime system.

关键词： NUMA process mapping MPI locality congestion multi-core

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Efficient resource shared RISC-V multicore processor 14

Efficient resource shared RISC-V multicore processor

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14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Islam, Md Ashraful Kise, Kenji Tokyo Inst Technol Sch Comp Tokyo Japan

ISBN: (纸本)9781665438605

Edge computing pushes the computational loads from the cloud to embedded devices, where data would be processed near the data source. Heterogeneous multicore architecture is believed to be a promising solution to fulfill the edge computational requirement. In FPGAs, the heterogeneous multicore is realized as multiple soft processor cores with custom processing elements. Since FPGA is a resource-constrained device, sharing the hardware resources among the soft processor cores can be advantageous. Some research has focused on the sharing resources among soft processors, but they do not study how much FPGA logic is minimized for a five-stage pipeline processor. This paper proposes the microarchitecture of a five-stage pipeline scalar processor that enables the sharing of functional units for execution among the multiple cores. We then investigate the performance and hardware resource utilization for a four-core processor. We find that sharing different functional units can save the LUT usage to 23.5% and DSP usage to 75%. We analyze the performance impact of sharing from the Embench benchmark program by simulating the same program in all four cores. Our simulation results indicate that based on the sharing configuration, the average performance drops from 2.9% to 22.3%.

关键词： Heterogeneous multicore RISC-V Microarchitecture Logic sharing

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Accelerating multicore Architecture Simulation Using Application Profile 10

Accelerating Multicore Architecture Simulation Using Applica...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Kimura, Keiji Taguchi, Gakuho Kasahara, Hironori Waseda Univ Dept Comp Sci & Engn Shinjuku Ku 3-4-1 Okubo Tokyo Japan

ISBN: (纸本)9781509035311

Architecture simulators play an important role in exploring frontiers in the early stages of the architecture design. However, the execution time of simulators increases with an increase the number of cores. The sampling simulation technique that was originally proposed to simulate single-core processors is a promising approach to reduce simulation time. Two main hurdles for multi/many-core are preparing sampling points and thread skewing at functional simulation time. This paper proposes a very simple and low-error sampling-based acceleration technique for multi/many-core simulators. For a parallelized application, an iteration of a large loop including a parallelizable program part, is defined as a sampling unit. We apply X-means method to a profile result of the collection of iterations derived from a real machine to form clusters of those iterations. Multiple iterations are exploited as sampling points from these clusters. We execute the simulation along the sampling points and calculate the number of total execution cycles. Results from a 16-core simulation show that our proposed simulation technique gives us a maximum of 443x speedup with a 0.52% error and 218x speedup with 1.50% error on an average.

关键词： many-core Simulator Compiler

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A Benes Based NoC Switching Architecture for Mixed Criticality embedded systems 10

A Benes Based NoC Switching Architecture for Mixed Criticali...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Kerrison, Steve May, David Eder, Kerstin Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9781509035311

Multi-core, Mixed Criticality embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect becomes a potential point of uncertainty, introducing major challenges in proving behaviour is always within specified constraints, limiting the means of growing system performance to add more tasks, or provide more computational resources to existing tasks. We present MCENoC, a Network-on-chip (NoC) switching architecture that provides innovations to overcome this with predictable, formally verifiable timing behaviour that is consistent across the whole NoC. We show how the fundamental properties of Benes networks benefit MCE applications and meet our architecture requirements. Using systemVerilog Assertions (SVA), formal properties are defined that aid the refinement of the specification of the design as well as enabling the implementation to be exhaustively formally verified. We demonstrate the performance of the design in terms of size, throughput and predictability, and discuss the application level considerations needed to exploit this architecture.

关键词： formal verification FPGA Mixed criticality network on chip non-blocking switches timing predictable

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A Lightweight Action Recognition Method for Deployable embedded Devices for Human-Computer Interaction 16

A Lightweight Action Recognition Method for Deployable Embed...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Hu, Nanjie Wang, Ningyu Lin, Jie Fu, Qinghao Tan, Benying Guilin Univ Elect Technol Sch Artificial Intelligence Guilin Peoples R China

ISBN: (纸本)9798350393613

In recent years, numerous researchers have proposed various solutions to address the challenges in action recognition. However, most existing approaches suffer from high computational requirements and significant memory usage, making them impractical for real-time deployment on embedded devices. This paper introduces a lightweight action recognition method suitable for deploying on embedded devices for human-computer interaction, denoted as LARMDED-HCI (Lightweight Action Recognition for Mobile and Deployable Human-Computer Interaction). Our method employs MobileNetV3 as the backbone network, significantly reducing computational load and parameter count. We incorporate the Temporal Shift Module (TSM) to model the temporal aspect of video frames, enabling the model to capture temporal features effectively. Additionally, a 1D temporal convolutional layer is introduced to enhance feature extraction in the temporal dimension, improving the model's ability to model temporal differences between adjacent frames. Experiments conducted on the Jester and Something-Something-V2 datasets demonstrate that our approach exhibits a noticeable competitive advantage in recognition accuracy compared to other methods. Furthermore, our method achieves satisfactory real-time performance when deployed on embedded devices, facilitating human-computer interaction on such platforms.

关键词： action recognition embedded devices human-computer interaction lightweight temporal modeling

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An Intelligent Plant Dissease Detection system for Smart Hydroponic using Convolutional Neural Network 14

An Intelligent Plant Dissease Detection System for Smart Hyd...

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14th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Musa, Aminu Hamada, Mohamed Aliyu, Farouq Muhammad Hassan, Mohammed Fed Univ Dutse Dept Comp Sci Dutse Nigeria Univ Aizu Software Engn Lab Aizu Wakamatsu Japan Yobe State Univ Dept Comp Sci Damaturu Nigeria Bayero Univ Kano Dept Software Engn Kano Nigeria

ISBN: (纸本)9781665438605

Recently, researchers proposed automation of hydroponic systems to improve efficiency and minimize manpower requirements. Thus increasing profit and farm produce. However, a fully automated hydroponic system should be able to identify cases such as plant diseases, lack of nutrients, and inadequate water supply. Failure to detect these issues can lead to damage of crops and loss of capital. This paper presents an Internet of Things-based machine learning system for plant disease detection using Deep Convolutional Neural Network (DCNN). The model was trained on a data set of 54,309 instances containing 38 different classes of plant disease. The images were retrieved from a plant village database. The system achieved an Accuracy of 98.0% and AUC precision score of 88.0%.

关键词： Hydroponic Raspberry pi Internet of Things convolutional neural network

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High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing 16

High-efficiency Reconfigurable Crypto Accelerator Utilizing ...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Le, Vu Trung Duong Pham, Hoai Luan Tran, Thi Hong Duong, Thi Sang Nakashima, Yasuhiko Nara Inst Sci & Technol 8916-5 Takayama Cho Ikoma Nara 6300192 Japan Osaka Metropolitan Univ Osaka 5588585 Japan

ISBN: (纸本)9798350393613

In decentralized IoT ecosystems, four cryptographic algorithms, including SHA256, BLAKE256, BLAKE2s, and Chacha20, are principal to ensure data integrity and confidentiality. However, existing cryptographic hardware is often limited to supporting a single algorithm and suffers from low performance, which falls short of meeting the diverse requirements of these systems. To address these limitations, we introduce a reconfigurable crypto accelerator (RCA) that offers high flexibility, superior performance, and optimal hardware efficiency. Our RCA includes three novel optimizations, specifically, a homogeneous multi-core architecture, a register-adder sharing approach, and a multi-level pipeline scheduler. The RCA was successfully verified and implemented at the system-on-chip level on a ZCU102 FPGA. The real-time performance evaluation of the RCA, during the execution of various cryptographic algorithms, demonstrates an energy efficiency ranging from 94.3-160.4 Mbps/W, which is 3.1-10.5 times higher compared to modern CPUs. Experiments conducted on several FPGAs show that the RCA is higher flexibility while still outperforming previous works by 1.63-31.65 times in throughput and 1.04-2.76 times in area efficiency. Furthermore, in ASIC synthesis, the RCA exhibits exceptional throughput (48.79-92.16 Gbps), area efficiency (66.2-102.31 Gbps/mm2), and energy efficiency (186.22-287.8 Gbps/W), surpassing other related ASICbased works.

关键词： Multi-core Cryptography FPGA ASIC SHA256 Homogeneous

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A Task Allocation Method for the DTTR Scheme based on the Parallelism of Tasks 10

A Task Allocation Method for the DTTR Scheme based on the Pa...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Saito, Hiroshi Imai, Masashi Yoneda, Tomohiro Univ Aizu Aizu Wakamatsu Fukushima Japan Hirosaki Univ Hirosaki Aomori Japan Natl Inst Informat Koganei Tokyo Japan

ISBN: (纸本)9781509035311

In this paper, we propose a task allocation method for multi-core systems with the Duplication with Temporary Triple Modular Redundancy and Reconfiguration (DTTR) scheme. The proposed method optimizes both performance and reliability by allocating copies of tasks (i.e., redundant tasks) based on the maximum parallelism of tasks in a give application. In the experimental results, we compare the average failure rate of task allocations obtained by the proposed method with the one obtained by a scheduling-based task allocation method and the one obtained by a task allocation method based on Simulated Annealing. The proposed method realizes both high performance and high reliability in the cases when enough cores to maximize parallel execution of tasks exist.

关键词： clique partitioning Multi-core systems reliability task allocation

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Hybrid Hardware-Software Architecture for Quantum Secure IoT embedded systems 16

Hybrid Hardware-Software Architecture for Quantum Secure IoT...

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16th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSoC)

作者： Li, Aobo Lu, Jiahao Liu, Dongsheng Li, Xiang Yang, Shuo Zhang, Jiaming Huang, Tianze Xiong, Siqi Huazhong Univ Sci & Technol Sch Integrated Circuits Wuhan Peoples R China

ISBN: (纸本)9798350393613

The Internet of Things (IoT) communication prevents information from being decrypted or tampered with by unauthorized third parties. Post-quantum cryptography ensures that the information exchange between IoT devices can resist potential quantum computer attacks, thereby enhancing the quantum security of the IoT. This paper presents a quantum-secure hardware-software architecture for embedded systems. An FPGA-based post-quantum cryptographic Kyber accelerator and an STM32 microcontroller with AES encryption are integrated into the system. Customized hardware structures such as hash and modular arithmetic unit provide faster calculation speed. The command exchange protocol bridges embedded software and FPGA hardware. The server handles key generation and decryption, while the client manages encryption. AES-256 encryption is utilized to ensure the confidentiality and integrity of the data and keys, with the Kyber algorithm encrypting the session keys. Compared to previous works, this implementation demonstrates better resource utilization as well as enhanced performance in key generation, encryption, and decryption. Hardware implementation operates at 100MHz on the Artix-7 FPGA platform, consuming 20,782 LUTs, 5,077 FFs, 7.5 BRAMs, and 8 DSPs. The architecture also achieves up to 1.5x speed improvements in encryption and similar enhancements in decryption across various security levels.

关键词： Post-quantum cryptography Hardware-software architecture Kyber AES Secure communication

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The Role of Self-Awareness and Hierarchical Agents in Resource Management for many-core systems 10

The Role of Self-Awareness and Hierarchical Agents in Resour...

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10th ieee international symposium on embedded multicore/many-core systems-on-chip (MCSOC)

作者： Gotzinger, Maximilian Rahmani, Amir M. Pongratz, Martin Liljeberg, Pasi Jantsch, Axel Tenhunen, Hannu Univ Turku Dept Informat Technol SF-20500 Turku Finland TU Wien Inst Comp Technol Vienna Austria

ISBN: (纸本)9781509035311

The future of Moore's Law is in jeopardy. The number of cores of many-core systems is steadily increasing for every technology node generation. Voltage scaling does not keep pace with the unabated decrease of transistor size. Higher leakage power and manufacturing variabilities are the consequences and lead to extremely critical power as well as thermal issues. These phenomena can downgrade the performance or endanger system's functionality as well as its reliability if they are not properly addressed. In near future, up to 90% of a many-core chip's area may have to remain inactive;this non-active area is termed Dark Silicon. These issues make the problem of resource management challenging. Future management systems need to be intelligent, anticipatory, and self-adaptive. They are supposed to integrate management of different aspects such as thermal, power, energy, performance, quality of service, process variability, occurrence of faults and aging effects, all in one. In this paper, we study the contributions in the literature focusing on techniques for dynamic resource management in multi-and many-core systems. We put emphasis on advanced approaches that exhibit learning, self-awareness, hierarchical monitoring and management. We categorize the existing approaches from a new perspective and argue that a self-aware hierarchical agent-based model is a proper methodology to monitor and management many-core systems, in particular when they need to deal with different competing goals. In addition, we evaluate the main objectives and trends in resource management of many-core systems in order to pave the way for designing future computer systems ranging from high-performance computers to embedded processors used in the era of Internet-of-Things.

关键词： Self-Awareness Hierarchical Agent-Based system many-core Dark Silicon Power- Thermal- and Reliability Management

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