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Research on Computer Vision-Based Environment Perception and Decision-Making system for Autonomous Vehicles

Research on Computer Vision-Based Environment Perception and...

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ieee international symposium on Information (IT) in Medicine and Education, ITME

作者： Ye Sun Li Shen Shuangnan Wu Hao Yan Feng Sheng Hunan Automotive Engineering Vocational University Zhuzhou China

ISBN: (数字)9798350356670

ISBN: (纸本)9798350356687

This paper delves into the design and implementation of autonomous vehicle systems, with a focus on the overall architecture, hardware platforms, software design, and system integration. The autonomous driving system captures environmental information through high-precision sensors, which is then processed in real-time and decisions are made by powerful computing units, leading to vehicle control actions. Throughout the design and implementation process, emphasis is placed on real-time performance, robustness, and safety considerations. system performance is continuously enhanced through algorithm optimizations, hardware advancements, and improvements in system integration strategies. The objective of this research is to provide a robust foundation for the advancement of autonomous vehicles, thereby propelling progress in smart transportation systems.

关键词： Software design system performance system integration Real-time systems Hardware Safety Smart transportation Vehicle dynamics Autonomous vehicles testing

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Taking Recoveries to Task: Recovery-Driven Development for Recipe-Based Robot Tasks 17th

Taking Recoveries to Task: Recovery-Driven Development for R...

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19th international symposium of Robotics Research (ISRR)

作者： Banerjee, Siddhartha Daruna, Angel Kent, David Liu, Weiyu Balloch, Jonathan Jain, Abhinav Krishnan, Akshay Rana, Muhammad Asif Ravichandar, Harish Shah, Binit Shrivatsav, Nithin Chernova, Sonia Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9783030954598;9783030954581

Robot task execution when situated in real-world environments is fragile. As such, robot architectures must rely on robust error recovery, adding non-trivial complexity to highly-complex robot systems. To handle this complexity in development, we introduce Recovery-Driven Development (RDD), an iterative task scripting process that facilitates rapid task and recovery development by leveraging hierarchical specification, separation of nominal task and recovery development, and situated testing. We validate our approach with our challenge-winning mobile manipulator software architecture developed using RDD for the FetchIt! Challenge at the ieee 2019 international Conference on Robotics and Automation. We attribute the success of our system to the level of robustness achieved using RDD, and conclude with lessons learned for developing such systems.

关键词： Failure recovery Robot architectures Mobile manipulation design and prototyping

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Fortified-Grid 3.0: Security by design for Smart Grid through Hardware Security Primitives

Fortified-Grid 3.0: Security by Design for Smart Grid throug...

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ieee international symposium on Smart Electronic systems (iSES)

作者： Giriraj Sharma Amit M. Joshi Saraju P. Mohanty Dept. of Electronics & communication Malaviya National Institute of Technology Jaipur India Dept. of comp science & Engg University of North Texas Texas USA

Traditional approaches to adding security measures and retrofitting them onto existing smart grid systems, have security flaw and vulnerability. Considering security from the beginning, potential vulnerabilities and risks can be identified and addressed early in the smart grid design process, leading to more robust and secure solutions. $S$ bD involves incorporating security considerations and features into the design and architecture of a system rather than adding them as an afterthought. This paper provides an extensive overview of hardware security and trust, examining threats, countermeasures, and design tools. Fortified-Grid 3.0 introduces the latest advancements in hardware security research, aiming to inspire hardware designers and smart grid developers to embrace the challenges and opportunities of integrating additional security measures into robust hardware design, testing, and verification. This paper also discusses security by design in smart grids, focusing on primitives like PUF and TPM. Our paper addresses various challenges, presents solutions, and conducts comparative analyses of prevalent Security-by-design approaches.

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Industrial Practices in Low-Power robust design 26

Industrial Practices in Low-Power Robust Design

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Ravikumar, C. P. Texas Instruments Inc Bagmane Tech Pk Bangalore 560093 Karnataka India

ISBN: (数字)9781728181875

ISBN: (纸本)9781728181875

Increasing amount of electronics is being embedded into automotives. We are witnessing the conversion of the automotive from a purely mechanical device to an electrical/electronic/ mechanical device. Purely electrical and hybrid-electrical vehicles are replacing the gasoline/diesel-driven vehicles. A variety of driver assistance systems are already available in modestly priced to high-end cars. Self-driven cars have been deployed in some cities on an experimental basis. The manufacturing sector is witnessing a similar revolution. Robots are being used in smart factories and warehouses. In a world where cyber-physical systems and life-forms will coexist, it is imperative that the electronics embedded into automotives and industrial systems has a long life and operates reliably in its environment. Reducing power and energy dissipation in these systems is important from many perspectives, including environmental impact, heating, and system reliability. In this paper, we survey the landscape of research and development towards the building of robust, low-power semiconductor for automotive and industrial applications.

关键词： Program processors Sensors Random access memory Reliability Automotive engineering Hardware Circuit faults

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Hardware Implementation of Double Pendulum Pseudo Random Number Generator

Hardware Implementation of Double Pendulum Pseudo Random Num...

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ieee international symposium on Embedded Multicore Socs (MCSoC)

作者： T. Hui Teo Maoyang Xiang Hen Rin Leao Keye Qian Jarrod Lim Tom Manuel Opalla Piccio Chua Min Jie Michelle Engineering Product Development Singapore University of Technology and Design Singapore Nano-Electronic Engineering and Design Singapore University of Technology and Design Singapore Chang Gung University Taiwan

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

This paper presents a novel pseudo-random number generator (PRNG) implemented on an FPGA for encryption and data security applications. The system leverages environmental data captured by sensors to generate seeds, which are processed using a chaotic double pendulum algorithm. The generated random numbers exhibit strong randomness, demonstrated by a histogram analysis of over one million data points with no discernible pattern. However, the algorithm's complexity posed resource limitations on the FPGA, prompting partial offloading to an Arduino. Despite these challenges, the method provides a robust solution for secure random number generation, with potential improvements to be explored in future work.

关键词： Visualization Statistical analysis Multicore processing Prototypes Generators Sensor systems Field programmable gate arrays Random number generation testing Microphones

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ZOBNN: Zero-Overhead Dependable design of Binary Neural Networks with Deliberately Quantized Parameters

ZOBNN: Zero-Overhead Dependable Design of Binary Neural Netw...

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ieee symposium on On-line testing (IOLTS)

作者： Behnam Ghavami Mohammad Shahidzadeh Lesley Shannon Steve Wilton University of British Columbia Canada Simon Fraser University Canada

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

Low-precision weights and activations in deep neural networks (DNNs) outperform their full-precision counterparts in terms of hardware efficiency. When implemented with low-precision operations, specifically in the extreme case where network parameters are binarized (i.e. BNNs), the two most frequently mentioned benefits of quantization are reduced memory consumption and a faster inference process. In this paper, we introduce a third advantage of very low-precision neural networks: improved fault-tolerance attribute. We investigate the impact of memory faults on state-of-the-art binary neural networks (BNNs) through comprehensive analysis. Despite the inclusion of floating-point parameters in BNN architectures to improve accuracy, our findings reveal that BNNs are highly sensitive to deviations in these parameters caused by memory faults. In light of this crucial finding, we propose a technique to improve BNN dependability by restricting the range of float parameters through a novel deliberately uniform quantization. The introduced quantization technique results in a reduction in the proportion of floating-point parameters utilized in the BNN, without incurring any additional computational overheads during the inference stage. The extensive experimental fault simulation on the proposed BNN architecture (i.e. ZOBNN) reveal a remarkable 5X enhancement in robustness compared to conventional floating-point DNN. Notably, this improvement is achieved without incurring any computational overhead. Crucially, this enhancement comes without computational overhead. ZOBNN excels in critical edge applications characterized by limited computational resources, prioritizing both dependability and real-time performance.

关键词： Fault tolerance Quantization (signal) Memory management Fault tolerant systems Artificial neural networks Reliability engineering robustness

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Soft Error Tolerance of Power-Supply-Noise Hardened Latches 26

Soft Error Tolerance of Power-Supply-Noise Hardened Latches

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Miura, Yukiya Kinoshita, Yuya Tokyo Metropolitan Univ Fac Syst Design Tokyo Japan Tokyo Metropolitan Univ Grad Sch Syst Design Tokyo Japan

ISBN: (纸本)9781728181875

As the shrink of a device size and the decrease in power supply voltage of VLSI circuits, their reliability has been degraded due to soft errors. In recent years, malfunctions caused by soft errors have become noticeable on the ground level, and their countermeasures are required. The authors have proposed power-supply-noise hardened FFs which have a partially redundant circuit structure. Focusing on the redundant structure of the latch circuits in those FFs, this paper evaluates their soft error tolerance. By using HSPICE circuit simulations, it is shown that the latch circuits are tolerant not only to power supply noise but also to soft errors. Finally, from those results, this paper shows that the proposed FFs have high reliability for these factors.

关键词： bit-flip crossed-loop flip-flops half-duplex latches soft error

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A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 system 26

A Comprehensive End-to-end Solution for a Secure and Dynamic...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Portolan, M. Feitoza, R. S. Tchendjou, G. T. Reynaud, V Kannan, K. S. Barragan, M. Simeu, E. Maistri, P. Anghel, L. Leveugle, R. Mir, S. Univ Grenoble Alpes TIMA Grenoble INP CNRS F-38000 Grenoble France

ISBN: (纸本)9781728181875

The disruptive potential of the ieee 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

关键词： Mixed-Signal testing ADCs Embedded Test Instruments Circuit Aging Secure Access Authentication Automated Test Environments

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PISA: Power-robust Multiprocessor design for Space Applications 26

PISA: Power-robust Multiprocessor Design for Space Applicati...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Simevski, Aleksandar Schrape, Oliver Benito, Carlos Krstic, Milos Andjelkovic, Marko IHP Leibniz Inst Innovat Mikroelekt Technol Pk 25 D-15236 Frankfurt Oder Germany Arquimea Deutschland GmbH Technol Pk 25 D-15236 Frankfurt Oder Germany Univ Potsdam August Bebel Str 89 D-14482 Potsdam Germany

ISBN: (纸本)9781728181875

Recently the conservative space industry driven by the requirements of novel applications decided to introduce multiprocessor systems. Following the same line of motivation we introduce the PISA multiprocessor chip with improved power robustness for space applications which is successfully produced and tested in IHP 130 nm technology. The paper brings several novelties in respect to the current state-of-the-art. The chip uses the Waterbear framework in which the multiprocessor cores can be dynamically put in one of three different operating modes according to the current application requirements regarding performance, power consumption and fault tolerance. The chip has special power supply architecture with 13 power domains and Adaptive Voltage Scaling (AVS) mechanism based on voltage regulators which imposes a non-standard IC design flow. The measurement results showed that the power supply of the multiprocessor cores can be reduced from the nominal 1,2 V downto 0,82V without compromising power integrity.

关键词： Space applications

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On the testing of special memories in GPGPUs 26

On the testing of special memories in GPGPUs

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Condia, Josie E. Rodriguez Reorda, Matteo Sonza Politecn Torino Dept Control & Comp Engn Turin Italy

ISBN: (纸本)9781728181875

Nowadays, data-intensive processing applications, such as multimedia, high-performance computing and safety-critical ones (e.g., in automotive) employ General Purpose Graphics Processing Units (GPGPUs) due to their parallel processing capabilities and high performance. In these devices, multiple levels of memories are employed in GPGPUs to hide latency and increase the performance during the operation of a kernel. Moreover, modern GPGPU architectures implement cutting-edge semiconductor technologies, reducing their size and power consumption. However, some studies proved that these technologies are prone to faults during the operative life of a device, so compromising reliability. In this work, we developed functional test techniques based on parallel Software-Based Self-Test routines to test memory structures in the memory hierarchy of a GPGPU (FlexGripPlus) implementing the G80 architecture of Nvidia.

关键词： General Purpose Graphics Processing Units (GPGPUs) Software-Based Self-Test (SBST) functional testing predicate register file address register file fault simulation

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