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检索条件"任意字段=IEEE International Symposium on On-Line Testing and Robust System Design"

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In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops 26

In-Circuit Mitigation Approach of Single Event Transients fo...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Azimi, Sarah De Sio, Corrado Sterpone, Luca Politecn Torino Dipartimento Automat & Informat Turin Italy

ISBN: (纸本)9781728181875

Nowadays, radiation-induced Single Event Transients are a leading cause of critical errors in CMOS nanometric integrated circuits. In this work, we propose a workflow for analyzing and mitigating nanometric CMOS integrated circuits to radiation-induced transient errors. The analysis phase starts with the developed Rad-Ray tool for mimicking the passage of the radiation particles through the silicon matter of the cells to identify the features of the generated transient pulses. The tool is integrated with an electrical simulator to evaluate the dynamic behavior of the transient pulses inserted and propagated in the circuit. A tunable mitigation solution is proposed by inserting the filtering block before the storage element, tuned based on the duration and amplitude of the expected transient pulse, identified in the analysis phase. Experimental results are achieved by applying the proposed approach on the 45 nm Flip-Flop component available in the FreePDK design kit, comparing the Dynamic Error Rate for the original Flip-Flop and the mitigated one which shows a reduction of sensitivity up to 56% with respect of the original version, with negligible degradation of performances.

关键词： Single Event Transient Flip-Flop Circuit design Mitigation

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A Secure Scan Controller for Protecting Logic Locking 26

A Secure Scan Controller for Protecting Logic Locking

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Quang-Linh Nguyen Valea, Emanuele Flottes, Marie-Lise Dupuis, Sophie Rouzeyre, Bruno Univ Montpellier LIRMM CNRS Montpellier France

ISBN: (纸本)9781728181875

The globalized supply chain in the Integrated Circuit (IC) industry raises several security concerns such as over-production, IP piracy and Hardware Trojan insertion. Logic locking has emerged as a potential countermeasure to address these issues. However, its efficiency is challenged by various attacks, especially oracle-guided attacks based on Boolean Satisfiability (SAT) solvers. These attacks rely on the possibility for an attacker to control and observe in the field the internal state of a functional IC, which acts as an oracle. This ability to control/observe the IC states is offered by scan chains, typically used for IC production testing. In this paper, we propose a method, complementary to logic locking, to prevent such attacks. This method introduces a scan chain controller with a key-based authentication mechanism, in order to prevent unauthorized access to the scan chains once the IC is deployed in the field. The solution can be coupled with any logic locking technique at the cost of negligible area overhead. Furthermore, it is secure against state-of-the-art attacks and supports full testing.

关键词： IP Piracy design-for-Security Logic Locking design-for-Trust Scan Chains

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Transmission line Based CDM ESD Current Target to Overcome Bandwidth Limitations

Transmission Line Based CDM ESD Current Target to Overcome B...

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ieee international symposium on Electromagnetic Compatibility - EMC Europe

作者： Gabriel Fellner David Pommerenke Lena Zeitlhoefler Friedrich Zur Nieden Institute of Electronics Graz University of Technology Austria Christian Doppler Laboratory for EMC Aware Robust Electronic Systems Austria Infineon Technologies AG Germany

ISBN: (数字)9798350307351

ISBN: (纸本)9798350343045

Reducing charged device model (CDM) electrostatic discharge (ESD) target levels for advanced integrated circuits (ICs) and systems on chip (SoCs) enables cost-effective manufacturing. Notably fast rise times, as low as 20 ps, have been observed for CDM events below 250 V. Previous investigations have highlighted fast rise times as critical parameters for damage in CDM testing of devices. These rapid rise times result in spectral frequency content exceeding 17.5 GHz, surpassing the bandwidth of existing CDM current targets employing disk resistors. To overcome this bandwidth limitation, a CDM current target comprised of parallel-connected transmission lines has been developed. Full-wave simulation results confirm the design of an initial prototype. Time-domain measurements conducted in an experimental setup exhibit exemplary results, with potential for further enhancement through de-embedding techniques.

关键词： Time-frequency analysis Voltage measurement Current measurement Simulation Electrostatic measurements Bandwidth Transmission line measurements Electrostatic discharges Electromagnetic compatibility Discharges (electric)

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Reduced Fault Coverage as a Target for design Scaffolding Security 26

Reduced Fault Coverage as a Target for Design Scaffolding Se...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Pomeranz, Irith Kundu, Sandip Purdue Univ Sch ECE W Lafayette IN 47907 USA Univ Massachusetts Dept ECE Amherst MA 01003 USA

ISBN: (数字)9781728181875

ISBN: (纸本)9781728181875

The hardware design process adds, at each level, scaffolding logic to aid test, debug and engineering changes. Fault injection attacks can place a design in a non-functional state where the scaffolding is utilized for obtaining information that is not intended for the user. To counter such security threats, this paper suggests to include in the design logic that will identify invalid state patterns, and reset or hold a sufficient part of the state to prevent useful computations from occurring. To support such a solution, the paper also suggests that the fault coverage of a scan-based test set in the presence of single stuck-at faults can be used for designing the reset and hold logic. Such a test set relies on the use of non-functional states for fault detection. Without using the reset and hold logic, the test set achieves a high fault coverage (over 80% in the experiments reported in this paper). When the reset and hold logic is used, the fault coverage of the same test set is reduced below a preselected target (30% in the experiments reported in this paper). The reduction in the fault coverage occurs because much of the non-functional state space is no longer available. This also eliminates the security risk associated with these states.

关键词： Circuit faults Security Hardware Clocks Trojan horses Integrated circuit modeling Fault detection

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Representing Gate-Level SET Faults by Multiple SEU Faults at RTL 26

Representing Gate-Level SET Faults by Multiple SEU Faults at...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Bagbaba, Ahmet Cagri Jenihhin, Maksim Ubar, Raimund Sauer, Christian Cadence Design Syst Munich Germany Tallinn Univ Technol Tallinn Estonia

ISBN: (纸本)9781728181875

The advanced complex electronic systems increasingly demand safer and more secure hardware parts. Correspondingly, fault injection became a major verification milestone for both safety- and security-critical applications. However, fault injection campaigns for gate-level designs suffer from huge execution times. Therefore, designers need to apply early design evaluation techniques to reduce the execution time of fault injection campaigns. In this work, we propose a method to represent gate-level Single-Event Transient (SET) faults by multiple Single-Event Upset (SEU) faults at the Register-Transfer Level. Introduced approach is to identify true and false logic paths for each SET in the flip-flops' fan-in logic cones to obtain more accurate sets of flip-flops for multiple SEUs injections at RTL. Experimental results demonstrate the feasibility of the proposed method to successfully reduce the fault space and also its advantage with respect to state of the art. It was shown that the approach is able to reduce the fault space, and therefore the fault-injection effort, by up to tens to hundreds of times.

关键词： SET SEU multiple faults functional safety hardware security fault injection

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Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs 26

Development and Application of Embedded Test Instruments to ...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Azais, F. Bernard, S. Comte, M. Deveautour, B. Dupuis, S. El Badawi, H. Flottes, M-L Girard, P. Kerzerho, V Latorre, L. Lefevre, F. Rouzeyre, B. Valea, E. Vayssade, T. Virazel, A. Univ Montpellier LIRMM CNRS Montpellier France NXP Semicond Caen France

ISBN: (纸本)9781728181875

systems on a chip have seen their surface area increased by a factor of 10 and their consumption multiplied by 5 during the last ten years. Each technological node that enabled this integration has also added new constraints challenging the overall system reliability. In addition, the integration of analog/RF blocks adds specific issues, in particular the high cost of the required test equipment. It is therefore necessary to improve test and reliability solutions in order to guarantee the production yield and the system life-time. Moreover, the massive increase in the use of communicating systems has introduced security as a cornerstone of their development. The entire hardware production flow is therefore subject to security and trust issues requiring the development of dedicated test solutions. In this paper, we focus on LIRMM contributions in the HADES project especially with details on Embedded Test Instruments (ETIs) for reliability of digital ICs, low-cost RF test based on indirect DC measurements or digital ATE capture, management of secure scan access.

关键词： ETI Fault tolerance AxC RF testing Machine Learning Security and test scan encryption

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Fast BCH 1-Bit Error Correction Combined with Fast Multi-Bit Error Detection 26

Fast BCH 1-Bit Error Correction Combined with Fast Multi-Bit...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Schulz-Hanke, Christian Univ Potsdam Potsdam Germany

ISBN: (数字)9781728181875

ISBN: (纸本)9781728181875

In this paper, an error correction is combined with additional detection using a BCH code. It is shown that a fast 1-bit correction can be efficiently combined with fast BCH multi-bit detection for all up to (2T - 1)-bits errors, where T can be specified. In the case of an error, the syndrome is calculated and both a speculative 1-bit correction and an error detection process are started in parallel. The proposed error detection process checks if the actual error syndrome components contradict the 1-bit error assumption. The corresponding determinants for 2-bit to T-bit errors are computed in ascending order up to the first determinant indicating an error larger than 1-bit. This differs from the classic approach where a sequence of corresponding determinants containing syndrome components in descending order from T to 2 is computed. For the classic approach, the first determinant not equal 0 in descending order indicates the number of errors. The presented approach allows to speed up the detection by simplifying the determinants using the results of previous iterations. Under the assumption of a 1-bit error, the determinants can be simplified to a constant size. The proposed approach speeds up the error detection considerably. This method is useful for error detection and error correction in safety critical applications where 100 percent of the multi-bit errors up to a certain multiplicity have to be detected.

关键词： Error correction codes Mathematical model Error correction testing robustness system analysis and design Safety

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Life-Time Prognostics of Dependable VLSI-SoCs using Machine-learning 26

Life-Time Prognostics of Dependable VLSI-SoCs using Machine-...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Bagheriye, Leila Ali, Ghazanfar Kerkhoff, Hans G. Univ Twente CTIT Res Inst Testable Design & Test Integrated Syst TDT Grp Enschede Netherlands

ISBN: (纸本)9781728181875

Recently, the usage of on-chip embedded instruments (EIs) to ensure dependable safety-critical systems is becoming inevitable. These EIs can help to provide self-awareness, and their feedback can be used in different applications, e.g. end-of-lifetime (EOL) predictions. However, inaccuracies present in data from these EIs, due to their resolution limitations, self-aging and quantization errors during digitization, can lead to an inaccurate EOL assessment. To address this challenge, a machine learning-based system-level approach for determining the EOL of a many-processor system-on-chip (MPSoC) is discussed. It is based on the synchronous data capture of different IJTAG compatible EIs. To this end, two different data fusion techniques have been used for enhancing the accuracy of lifetime prognostics of multiple EIs;use is made of Independent Component Analysis (ICA) and the auto-encoder (AE). Different combinations of fused EIs (based on ICA and AE) along with standalone EIs for four different critical paths (CPs) have been investigated. For lifetime prediction based on different EIs/fused EIs, a data-driven degradation model was derived, and nonlinear regression has been employed for parameter estimation. Results show that data fusion of different EIs helps in obtaining better estimation of the EOL as compared to using a standalone EI.

关键词： Dependability Reliability MPSoC Embedded Instruments (EIs) Data Fusion Data-driven Lifetime prediction EOL Machine Learning

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Machine Learning Clustering Techniques for Selective Mitigation of Critical design Features 26

Machine Learning Clustering Techniques for Selective Mitigat...

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26th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Lange, Thomas Balakrishnan, Aneesh Glorieux, Maximilien Alexandrescu, Dan Sterpone, Luca iRoC Technol Grenoble France Politecn Torino Dipartimento Informat & Automat Turin Italy Tallinn Univ Technol Dept Comp Syst Tallinn Estonia

ISBN: (纸本)9781728181875

Selective mitigation or selective hardening is an effective technique to obtain a good trade-off between the improvements in the overall reliability of a circuit and the hardware overhead induced by the hardening techniques. Selective mitigation relies on preferentially protecting circuit instances according to their susceptibility and criticality. However, ranking circuit parts in terms of vulnerability usually requires computationally intensive fault-injection simulation campaigns. This paper presents a new methodology which uses machine learning clustering techniques to group flip-flops with similar expected contributions to the overall functional failure rate, based on the analysis of a compact set of features combining attributes from static elements and dynamic elements. Fault simulation campaigns can then be executed on a per-group basis, significantly reducing the time and cost of the evaluation. The effectiveness of grouping similar sensitive flip-flops by machine learning clustering algorithms is evaluated on a practical *** clustering algorithms are applied and the results are compared to an ideal selective mitigation obtained by exhaustive fault-injection simulation.

关键词： Transient Faults Single-Event Upsets Selective Mitigation Selective Hardening Soft Error Protection

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Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor

Higher-order Hardware: Implementation and Evaluation of the ...

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ACM and ieee international Conference on Formal Methods and Models for Co-design (MEMOCODE)

作者： Jeremy Pope Carl-Johan H. Seger Henrik Valter Department of CSE Chalmers University of Technology Gothenburg Sweden

ISBN: (数字)9798350378023

ISBN: (纸本)9798350378030

A major challenge with the practical deployment of Internet-of-Things (IoTs) is how to develop the high-quality code needed in order to produce robust and secure IoT devices. In other domains, high-level programming languages have shown to be efficient vehicles towards this. However, the very limited compute power provided by IoT devices have made it difficult to apply the same approach to IoT devices. The Cephalopode processor is an attempt at implementing a low power hardware device directly aimed at running a high-level functional language. By integrating many resource-heavy tasks like garbage collection and arbitrary precision arithmetic into dedicated hardware, the Cephalopode processor explores the hypothesis that high-level functional languages can be used even for low-power IoT devices. This paper presents the implementation and evaluation of the Cephalopode processor. We discuss the approach taken, the compiler and the architecture of the processor. We also describe the design process and design considerations. After implementation and synthesis we compare the processor to a conventional RISC-V processor running a functional language software environment. We also compare Cephalopode with running handwritten C code on the RISC-V processor.

关键词： Computer languages Codes Computer architecture Benchmark testing Hardware Software Internet of Things system analysis and design Arithmetic

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