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检索条件"任意字段=IEEE International Symposium on On-Line Testing and Robust System Design"

共 809 条记录，以下是11-20 订阅

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2017 ieee 23rd international symposium on On-line testing and robust system design, IOLTS 2017

2017 IEEE 23rd International Symposium on On-Line Testing an...

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23rd ieee international symposium on on-line testing and robust system design, IOLTS 2017

ISBN: (纸本)9781538603512

The proceedings contain 60 papers. The topics discussed include: a new 3-bit burst-error correcting code;automating wafer-level test of uncooled infrared detectors using wafer-prober;deterministic network on chip for deploying real time applications on many-core processors;diagnosis with transition faults on embedded segments;design-time reliability evaluation for digital circuits;voltage margins identification on commercial x86-64 multicore microprocessors;a generic embedded sequence generator for constrained-random validation with weighted distributions;an effective functional safety infrastructure for system-on-chips;and in-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.

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Safety-Relevant AI-Based system robustification with Neural Network Ensembles 30

Safety-Relevant AI-Based System Robustification with Neural ...

引用

30th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Aldoma, Adria Brando, Axel Cazorla, Francisco J. Abella, Jaume Barcelona Supercomp Ctr BSC Barcelona Spain Univ Politecn Catalunya UPC Barcelona Spain

Functional safety requirements of AI-based safety-critical applications challenge AI models, whose accuracy can be limited. In this paper, we show how using several cooperative deep learning (DL) models helps to raise... 详细信息

ISBN: (纸本)9798350370560;9798350370553

关键词： Neural network models

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Assessing robustness of Smart systems via Multi-domain Analog Fault Simulation 30

Assessing Robustness of Smart Systems via Multi-domain Analo...

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30th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Tosoni, Francesco Dall'Ora, Nicola Fraccaroli, Enrico Vinco, Sara Fummi, Franco Univ Verona Dept Engn Innovat Med Verona Italy Politecn Torino Dept Control & Comp Engn Turin Italy

ISBN: (纸本)9798350370560;9798350370553

Smart systems contain digital and analog components of several physical domains, e.g., electrical and mechanical. During the design phase, the fault injection, which checks the system functionality following the guidelines of ISO standard 26262, enhances the system's robustness. Unfortunately, fault injection and simulation on the analog side are i) not fully standardized compared to their digital counterparts, ii) highly domain-dependent, and iii) performed separately from the digital. This article proposes to improve the design of smart systems by generating faulty scenarios through analog fault injection across several physical domains. By exploiting these faulty scenarios, it is possible to improve the robustness of the analog part and simultaneously improve the quality of the digital part that controls the system functionality.

关键词： Fault simulation design robustness

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Refinement and Empirical Side-Channel Analysis of Inner Product Masking with robust Error Detection 30

Refinement and Empirical Side-Channel Analysis of Inner Prod...

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30th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Maidl, Anton Gay, Mael Keren, Osnat Polian, Ilia German Aerosp Ctr DLR eV Inst Protect Maritime Infrastruct Bremerhaven Germany

ISBN: (纸本)9798350370560;9798350370553

Side-channel attacks represent a significant and persistent threat to hardware security. One effective strategy for safeguarding hardware components against these attacks involves the implementation of masking schemes. Among these schemes, Inner Product Masking (IPM) has received considerable attention and analysis in prior research. Inner Product Masking with Error Detection aims to extend the security provided by IPM to Fault-Injection attacks. This can be achieved by incorporating (linear) repetition code for fault detection (IPM-FD) or by integrating a non-linear robust error detection into the scheme (IPM-RED). IPM-RED can detect (with non-zero probability) every fault regardless the number of bits it flips. However, this robustness comes with a cost, a non-linear function may leak via the physical channels more information than a linear one. This paper shows that information leakage from IPM-RED is marginal. An improved IPM-RED masking scheme is also presented, and an empirical side-channel leakage analysis of the protected Advanced Encryption Standard (AES) design utilizing the Test Vector Leakage Assessment (TVLA).

关键词： Information leakage

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Radiation-Induced Errors in the Software Level of Real-Time Soft Processing system 29

Radiation-Induced Errors in the Software Level of Real-Time ...

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29th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： De Sio, Corrado Rizzieri, Daniele Portaluri, Andrea La Greca, Salvatore G. Azimi, Sarah Politecn Torino Dipartimento Automat & Informat DAUIN Turin Italy

ISBN: (纸本)9798350341355

FPGAs' and programmable hardware's high performance and flexibility have made them a reasonable choice for space-oriented applications, although susceptible to soft errors. This paper proposes a comprehensive analysis of the effects of microarchitectural faults on soft processors due to radiations, identifying the hardware sources of errors and how they propagate to software-level.

关键词： Fault Injection FreeRTOS FPGA Microblaze RTOS SEUs Software Exceptions Soft Processors

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Efficient Optimized testing of Resistive RAM Based Convolutional Neural Networks 30

Efficient Optimized Testing of Resistive RAM Based Convoluti...

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30th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Saha, Anurup Ma, Kwondo Amarnath, Chandramouli Chatterjee, Abhijit Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9798350370560;9798350370553

Resistive random access memory (RRAM) based memristive crossbar arrays enable low power and low latency inference for convolutional neural networks (CNNs), making them suitable for deployment in IoT and edge devices. However, RRAM cells within a crossbar suffer from conductance variations, making RRAM-based CNNs vulnerable to degradation of their classification accuracy. To address this, the classification accuracy of RRAM based CNN chips can be estimated using predictive tests, where a trained regressor predicts the accuracy of a CNN chip from the CNN's response to a compact test dataset. In this research, we present a framework for co-optimizing the pixels of the compact test dataset and the regressor. The novelty of the proposed approach lies in the ability to co-optimize individual image pixels, overcoming barriers posed by the computational complexity of optimizing the large numbers of pixels in an image using state-of-the-art techniques. The co-optimization problem is solved using a three step process: a greedy image down-selection followed by backpropagation driven image optimization and regressor fine-tuning. Experiments show that the proposed test approach reduces the CNN classification accuracy prediction error by 31% compared to the state of the art. It is seen that a compact test dataset with only 2-4 images is needed for testing, making the scheme suitable for built-in test applications.

关键词： Resistive Random-Access Memory (RRAM) Convolutional neural network (CNN) testing Predictive testing

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Hardware Accelerator for FIPS 202 Hash Functions in Post-Quantum Ready SoCs 30

Hardware Accelerator for FIPS 202 Hash Functions in Post-Qua...

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30th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Crescenzo, Diamante Simone Rodriguez, Rafael Carrera Alidori, Riccardo Bruguier, Florent Valea, Emanuele Benoit, Pascal Bosio, Alberto Univ Grenoble Alpes CEA List F-38000 Grenoble France Univ Montpellier CNRS LIRMM Montpellier France Ecole Cent Lyon Inst Nanotechnol Lyon Lyon France

ISBN: (纸本)9798350370560;9798350370553

In today's digital landscape, cryptography plays a vital role in ensuring communication security through encryption and authentication algorithms. While traditional cryptographic methods rely on hard mathematical problems for security, the rise of quantum computing threatens their effectiveness. Post-Quantum Cryptography (PQC) algorithms, like CRYSTALS-Kyber, aim to withstand quantum attacks. Recently standardized, CRYSTALS-Kyber is a lattice-based algorithm designed to resist quantum attacks. However, its implementation faces computational challenges, particularly with Keccak-based functions, which are crucial for security and upon which the FIPS 202 standard is based. Our paper addresses this technological challenge by designing a FIPS 202 hardware accelerator to enhance CRYSTALS-Kyber efficiency and security. We chose to implement the entire FIPS 202 standard in hardware in order to widen the applicability of the accelerator to all possible algorithms that rely on such hash functions, taking care to provide realistic assumptions on system-level integration inside a system-on-Chip (SoC). We provide results in terms of area, frequency, and clock cycles for both ASIC and FPGA targets. An area reduction of up to 22.3% is achieved with respect to state-of-the-art solutions. In addition, we integrated the accelerator inside a 32-bit RISC-V based security-oriented SoC, where we show a strong performance gain on CRYSTALS-Kyber execution. The design presented in this paper performs better in all Kyber1024 primitives, with an improvement up to 3.21x in Kyber-KeyGen.

关键词： system-on-chip

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SLM ISA and Hardware Extensions for RISC-V Processors 29

SLM ISA and Hardware Extensions for RISC-V Processors

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29th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Ghasemi, S. Maryam Meschkov, Sergej Krautter, Jonas Gnad, Dennis R. E. Tahoori, Mehdi B. Karlsruhe Inst Technol KIT Inst Comp Engn Karlsruhe Germany

ISBN: (纸本)9798350341355

Nowadays, RISC-V processors have attracted much attention due to their extendability, for targeting high performance applications with strict demands on functional safety. Silicon Lifecycle Management (SLM) is a new emerging concept aiming at functional safety among other features such as availability, maintainability, and lifetime extension. This concept helps to monitor the system health during its lifecycle, in the various timespans, to ensure that safety margins while running critical applications are not exceeded. Hence, enabling both the collection of chip parametrics as well as in-field testing will provide the means to fulfill this concept. In this work, we propose instruction set extensions for enabling SLM in a RISC-V based system. For this purpose, we introduce Path Transient Monitors (PTM) and Voltage Fluctuations Monitors (VFM) for monitoring path delay and voltage fluctuations. Using power wasters as a mean to inject voltage fluctuations in the FPGA system, we evaluate the abilities of this system to monitor chip degradation in early stages before system failure.

关键词： Silicon Lifecycle Management design-forTestability FPGA parametric testing in-field testing

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Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing design 29

Feedback-Tuned Fuzzing for Accelerating Quality Verification...

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29th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Honda, Yusei Masuda, Yutaka Ishihara, Tohru Nagoya Univ Nagoya Aichi Japan

ISBN: (纸本)9798350341355

This paper proposes a novel quality verification (q-verification) technique for approximate computing (AC) design, which explores the input patterns that violate the constraint of computational quality, e.g., image quality. The key component of the proposed technique is coverage-based grey-box fuzzing (CGF). For enhancing the efficacy of CGF, this work proposes a feedback tuning algorithm that controls the feedback information to the queue by referring to the computational quality. In a case study of approximate image processing design where the bit-width scaling is applied, we experimentally confirmed that the proposed method reduced the runtime required for q-verification by 1.92 times compared to the conventional q-verification method using CGF.

关键词： approximate computing (AC) quality verification (q-verification) coverage-based grey-box fuzzing (CGF) feedback tuning

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Proton Evaluation of Single Event Effects in the NVIDIA GPU Orin SoM: Understanding Radiation Vulnerabilities Beyond the SoC 30

Proton Evaluation of Single Event Effects in the NVIDIA GPU ...

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30th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Rodriguez-Ferrandez, Ivan Kosmidis, Leonidas Tali, Maris Steenari, David Hands, Alex Belanger-Champagne, Camille Univ Politecn Cataluna Barcelona Spain Barcelona Supercomp Ctr Barcelona Spain European Space Agcy Noordwijk Netherlands TRIUMF Vancouver BC Canada

ISBN: (纸本)9798350370560;9798350370553

In this paper, we investigate the single event effects under proton irradiation for the state-of-the-art embedded GPU NVIDIA Jetson Orin NX system-on-Module (SoM). designed for deployment across safety critical domains and in particularly automotive, this system represents a cutting-edge advancement in high performance embedded computing with functional safety features, which makes it an ideal candidate for use in space systems. Our study evaluates the Single-Event Effects (SEE) manifested within the SoM's central processing unit (CPU), graphics processing unit (GPU), and associated peripherals. Through our analysis, we aim to delineate the origins of Single Event Functional Interrupts (SEFI) occurring at the SoM level. Furthermore, we provide a detailed exposition on the errors observed within the GPU complex, elucidating the requisite conditions for their manifestation. Unlike previous works which treat embedded GPUs under irradiation as black box, we are able to identify the source of SEEs through ARM's RAS subsystem, and observe for the first time in literature GPU SEEs. Our investigation culminates in a comprehensive assessment of the SoM's susceptibility, identifying particularly sensitive components.

关键词： system-on-chip

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