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检索条件"任意字段=IEEE International Symposium on On-Line Testing and Robust System Design"

共 809 条记录，以下是41-50 订阅

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MaLT: Machine-Learning-Guided Test Case design and Fault Localization of Complex Software systems 22

MaLT: Machine-Learning-Guided Test Case Design and Fault Loc...

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22nd international Conference on Formal Methods and Models for system design

作者： Ji, Yi Mak, Simon Lekivetz, Ryan Morgan, Joseph JMP Stat Discovery LLC DOE & Reliabil Cary NC 27513 USA Duke Univ Dept Stat Sci Durham NC USA

ISBN: (纸本)9798350378030;9798350378023

Software testing is essential for the reliable and robust development of complex software systems. This is particularly critical for cyber-physical systems (CPS), which require rigorous testing prior to deployment. The complexity of these systems limits the use of formal verification methods. Furthermore, testing and fault localization can be very costly. To mitigate this cost, we outline in this work a holistic machine-learning-guided test case design and fault localization (MaLT) framework, which leverages recent probabilistic machine learning methods to accelerate the testing of complex software systems. MaLT consists of three steps: (i) the construction of a suite of test cases using a covering array for initial testing, (ii) the investigation of posterior root cause probabilities via a Bayesian fault localization procedure, then (iii) the use of such Bayesian analysis to guide selection of subsequent test cases via active learning. The proposed MaLT framework can thus facilitate efficient identification and subsequent diagnosis of software faults with limited test runs. This framework has potential for integration with an assertion-based test oracle approach, which may prove to be an efficient and cost-effective way of integrating light-weight formal methods with testing.

关键词： Active learning Bayesian modeling Combinatorial testing Fault localization Probabilistic machine learning

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2016 ieee 22nd international symposium on On-line testing and robust system design, IOLTS 2016

2016 IEEE 22nd International Symposium on On-Line Testing an...

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22nd ieee international symposium on on-line testing and robust system design, IOLTS 2016

ISBN: (纸本)9781509015061

The proceedings contain 57 papers. The topics discussed include: on the robustness of DCT-based compression algorithms for space applications;a fault-tolerant sequential circuit design for SAFs and PDFs soft errors;an soft error propagation analysis considering logical masking effect on re-convergent path;analysis of BTI aging of level shifters;cache-aware reliability evaluation through LLVM-based analysis and fault injection;resilient random modulo cache memories for probabilistically-analyzable real-time systems;statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation;variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode;how EDA can improve productivity in the assessment of functional safety;evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations;hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms;concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks;and on the influence of compiler optimizations in the fault tolerance of embedded systems.

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Non-uniform array design for robust LoS MIMO via convex optimization 34

Non-uniform array design for robust LoS MIMO via convex opti...

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ieee 34th Annual international symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Palaiologos, Michail Garcia, Mario H. Castaneda Kakkavas, Anastasios Stirling-Gallacher, Richard A. Caire, Giuseppe Huawei Technol Dusseldorf GmbH Munich Res Ctr D-80992 Munich Germany Tech Univ Munich Sch Computat Informat & Technol D-80333 Munich Germany Tech Univ Berlin Commun & Informat Theory Grp D-10623 Berlin Germany

ISBN: (纸本)9781665464833

The array design problem of multiple-input multiple-output (MIMO) systems in a line-of-sight (LoS) transmit environment is examined. As uniform array configurations at the transmitter (Tx) and receiver (Rx) are optimal at specific transmit distances only, they lead to reduced spectral efficiency over a range of transmit distances. To that end, the joint design of non-uniform Tx and Rx arrays towards maximizing the minimum capacity of a LoS MIMO system across a range of transmit distances is investigated in this paper. By introducing convex relaxation, the joint Tx and Rx array design is cast as a convex optimization problem, which is solved in a iterative manner. In addition, we also implement a local search to obtain a refined solution that achieves an improved performance. It is shown that the non-uniform configurations designed with our proposed approach outperform uniform and non-uniform array designs of the literature in terms of capacity and/or complexity.

关键词： LoS MIMO convex optimization array design

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design of Distributed Measurement Network Based on TD-LTE 4

Design of Distributed Measurement Network Based on TD-LTE

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4th international symposium on Computer Technology and Information Science, ISCTIS 2024

作者： Zhang, Baoguo Sun, Difeng Zhang, Min Liang, Xubin Cheng, Qianqian Yang, Jun Li, Jin Liu, Wenxiang Zhang, Dezhi Wu, Zutang Northwest Institute of Nuclear Technology Xi'an China

ISBN: (纸本)9798350354560

To address the challenges of management, control, and data transfer in wide-area distributed measurement systems during range testing, a four-layer architecture for a low-frequency wireless measurement network has been designed, leveraging TDLTE wireless broadband technology. This design incorporates a remote control system and a comprehensive status monitoring system, enabling mobile deployment, extensive coverage, remote operation, and unmanned functionality for the measurement network. It effectively tackles the issuance of remote control commands, real-time status monitoring, and large-scale concurrent data retrieval. Laboratory tests reveal peak uplink and downlink rates of 40 Mbps and 100 Mbps, respectively. In actual environments, at a distance of 2 km, the uplink and downlink rates reach 9 Mbps and 22 Mbps, respectively, surpassing the design specification of a 2 Mbps uplink rate at 2 km in line-of-sight scenarios. © 2024 ieee.

关键词： Velocity measurement

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design of Servo Drive system for Automatic Packaging/Wrapping line 15

Design of Servo Drive System for Automatic Packaging/Wrappin...

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15th international symposium on Industrial Electronics and Applications, INDEL 2024

作者： Milic, Zoran Mitic, Darko Nikolic, Sasa Lukac, Dusko University of Niš Faculty of Electronic Engineering Niš Serbia

ISBN: (纸本)9798350352320

The design of packaging and wrapping machines demands a high degree of automation to achieve fast and precise coordination of synchronized and dependent motions. Consequently, specially designed mechanical mechanisms are typically employed. However, these motion solutions have limited flexibility which makes them nonoptimal when motion changes are required. In such scenarios, it is often necessary to either install an entirely new mechanism or replace it with a servo drive, which can provide nonuniform motion. The decision to replace the entire mechanism with a servo drive system is widely and effectively implemented in packaging industry nowadays. In this paper the example of application of Siemens hardware and software tools in designing servo drive system for horizontal packaging and wrapping line is presented. The paper provides a brief overview of servo system design using currently available set of tools, which facilitate initial system demand planning, hardware specification, and final design. The process includes equipment defining, configuring, programming, and testing, through a case study of a packaging/wrapping machine designed for specific types of insulation building materials. © 2024 ieee.

关键词： Packaging machines

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Fortified-Grid 3.0: Security by design for Smart Grid through Hardware Security Primitives 9

Fortified-Grid 3.0: Security by Design for Smart Grid throug...

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9th ieee international symposium on Smart Electronic systems, iSES 2023

作者： Sharma, Giriraj Joshi, Amit M. Mohanty, Saraju P. Malaviya National Institute of Technology Dept. of Electronics & Communication Jaipur India University of North Texas Dept. of Comp Science & Engg TX United States

ISBN: (纸本)9798350383249

Traditional approaches to adding security measures and retrofitting them onto existing smart grid systems, have security flaw and vulnerability. Considering security from the beginning, potential vulnerabilities and risks can be identified and addressed early in the smart grid design process, leading to more robust and secure solutions. S bD involves incorporating security considerations and features into the design and architecture of a system rather than adding them as an afterthought. This paper provides an extensive overview of hardware security and trust, examining threats, countermeasures, and design tools. Fortified-Grid 3.0 introduces the latest advancements in hardware security research, aiming to inspire hardware designers and smart grid developers to embrace the challenges and opportunities of integrating additional security measures into robust hardware design, testing, and verification. This paper also discusses security by design in smart grids, focusing on primitives like PUF and TPM. Our paper addresses various challenges, presents solutions, and conducts comparative analyses of prevalent Security-by-design approaches. © 2023 ieee.

关键词： Hardware security

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Integrating an Interconnect BIST with Crosstalk Avoidance Hardware 27

Integrating an Interconnect BIST with Crosstalk Avoidance Ha...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Akhsham, Mahsa Navabi, Zainalabedin Univ Tehran Coll Engn Sch Elect & Comp Engn Tehran Iran

ISBN: (纸本)9781665433709

An online interconnect BIST for detecting and avoiding interconnect faults is proposed in this paper. This BIST structure is built upon a new shielding method, the required hardware of which is reutilized in transmitting redundant test data across the interconnect for testing it. Together, BIST and the shielding parts, provide an integrated and novel interconnect testing and crosstalk fault-avoidance platform that share the same hardware. Our proposed integrated technique is modeled in SPICE to evaluate its functionality in terms of avoiding crosstalk faults, and online detection of those that cannot be avoided. We show that faults due to crosstalk are reduced by 49%, and those that still remain are 100% detected.

关键词： Fault avoidance Online testing Interconnect testing Crosstalk noise Shielding

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MOZART: Masking Outputs with Zeros for Architectural robustness and testing of DNN Accelerators 27

MOZART: Masking Outputs with Zeros for Architectural Robustn...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Burel, Stephane Evans, Adrian Anghel, Lorena Univ Grenoble Alpes LIST CEA Grenoble France Univ Grenoble Alpes INAC Spintec Grenoble INP CEACNRS Grenoble France

ISBN: (纸本)9781665433709

Deep Neural Networks (DNNs) are increasingly used in safety critical autonomous systems. In this paper, we present MOZART, a DNN accelerator architecture which provides fault detection and fault tolerance. MOZART is a systolic architecture based on the Output Stationary (OS) variant, as it is the one that inherently limits fault propagation. In addition, MOZART achieves fault detection with on-line functional testing of the Processing Elements (PEs). Faulty PEs are swiftly taken off-line with minimal classification impact. The implementation of our approach on Squeezenet results in a loss of accuracy of less than 3% in the presence of a single faulty PE, compared to 15-33% without mitigation. The area overhead for the test logic does not exceed 8%. Dropout during training further improves fault tolerance, without a priori knowledge of the faults.

关键词： neural network accelerator robustness fault tolerance convolution

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Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method 27

Metallic Ratio Equivalent-Time Sampling: A Highly Efficient ...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Yamamoto, Shuhei Sasaki, Yuto Zhao, Yujie Wei, Jianglin Kuwana, Anna Sato, Keno Ishida, Takashi Okamoto, Toshiyuki Ichikawa, Tamotsu Nakatani, Takayuki Tran, Tri Minh Katayama, Shogo Hatayama, Kazumi Kobayashi, Haruo Gunma Univ Fac Sci & Technol Div Elect & Informat 1-5-1 Tenj Cho Kiryu Gumma 3768515 Japan ROHM Semicond Kouhoku Ku 2-4-8 Shin Yokohama Yokohama Kanagawa 2228575 Japan

ISBN: (纸本)9781665433709

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable;when the repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with the equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing.

关键词： equivalent-time sampling waveform acquisition golden ratio metallic ratio analog IC testing integer theory

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robust Adaptive Read Scheme for 7nm Configuration SRAMs 27

Robust Adaptive Read Scheme for 7nm Configuration SRAMs

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Saraswatula, Sree Rama K. C. Yachareni, Santosh Zhou, Shidong Pulipati, Narendra Chen, Joy Masina, Teja Xilinx Farb Design CPG Hyderabad India

ISBN: (纸本)9781665433709

This paper presents a new Adaptive Read scheme for Configuration SRAMs with a feedback mechanism to eliminate Read-Disturb, enhancing Read Margin, yield and performance. The proposed scheme is implemented on TSMC 7nm FinFETs for Configuration SRAMs in Xilinx FPGAs, and this idea is applicable to any distributed SRAM structures. The design has an intrinsic dynamic feedback mechanism to adjust the read address voltage effectively, based on the process, voltage and temperature (PVT), by using a special replica memory cell that emulates actual memory cells. The proposed Op-Amp based design with a memory cell emulating circuit in the negative feedback is shown to be working on silicon, which tunes pass-gate (PG) address voltage during read, with 2.7x improvement in read margin, and also avoids read-disturb.

关键词： 6T memory cell (MC) replica pass-gate & pull-down Adaptive Read Address voltage Read Margin Read-Disturb P-Input Op-Amp Keeper circuit Monte-Carlo analysis

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