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检索条件"任意字段=IEEE International Symposium on On-Line Testing and Robust System Design"

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A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay 27

A Method for Measuring Process Variations in the FPGA Chip C...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Miura, Yukiya Tsutsumi, Shingo Tokyo Metropolitan Univ Fac Syst Design Tokyo Japan Tokyo Metropolitan Univ Grad Sch Syst Design Tokyo Japan

ISBN: (纸本)9781665433709

FPGAs are integrated circuits that can be implemented arbitrary logic functions. In FPGAs, it is important to measure process variations with high accuracy because process variations have become noticeable. A ring oscillator is widely used as a process monitor circuit. In FPGA design, a design tool automatically determines logic blocks in the chip on which a circuit is implemented and wires between the logic blocks. designers can manually redesign/modify logic block parts, but not wire parts. Therefore, in order to measure process variations with high accuracy, it is necessary to clarify the effect of wire delay on an oscillation frequency. In this paper, ring oscillators with different wires between logic blocks are implemented on the FPGA chip and a method for measuring process variations with less effect of wire delay is considered.

关键词： FPGA Oscillation Frequency Process Variations Ring Oscillators Wire Delay

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A New Domains-based Isolation design Flow for Reconfigurable SoCs 27

A New Domains-based Isolation Design Flow for Reconfigurable...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Portaluri, Andrea De Sio, Corrado Azimi, Sarah Sterpone, Luca Politecn Torino Dipartimento Automat & Informat DAUIN Turin Italy

ISBN: (纸本)9781665433709

Reconfigurable SoCs are widely adopted in mission-critical tasks in aerospace and automotive. Though, one of their main drawbacks is the susceptibility to high-energy particles both in space and at sea level. Isolation design Flow is a promising implementation approach to improve the reliability of circuits. However, considering the high number of modules in a complex circuit, especially when redundant techniques are applied, IDF requires a complex floorplanning stage. In this paper, the benefits of using IDF are evaluated, both for plain and hardened-by-redundancy designs. We propose an implementation methodology to tackle the complexity of applying IDF to TMR-based circuits that usually make the implementation approach unfeasible. The impact of different design policies on the reliability of the system is evaluated through fault injection campaigns. The proposed method is applied to the TMR-hardened CORDIC core implemented on Zynq AP-SoC and compared with other possible solutions. The results report a significant improvement in the TMR effectiveness when the proposed domains-based IDF is applied.

关键词： Fault injection Isolation design flow Reliability Reconfigurable SoC SEU SRAM-based FPGA

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Towards Error Resilient and Power-Efficient Adaptive Multiprocessor system using Highly Configurable and Flexible Cross-Layer Framework 27

Towards Error Resilient and Power-Efficient Adaptive Multipr...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Veleski, Mitko Huebner, Michael Krstic, Milos Kraemer, Rolf BTU Cottbus Senftenberg Chair Comp Engn Cottbus Germany IHP Leibniz Inst Innovat Mikroelekt Frankfurt Germany Univ Potsdam Potsdam Germany

ISBN: (纸本)9781665433709

A typical multiprocessor system often needs to support a wide spectrum of applications. Today, error resilience and low power consumption are two crucial, but non-complementary requirements and meeting both simultaneously is difficult. Thus, adaptivity is becoming increasingly important feature for modern computing systems. In this regard, we integrate a highly-configurable framework with a set of cross-layer techniques efficient in improving error resilience / power consumption into a multiprocessor system. The framework intelligently interchanges methods such as Adaptive Voltage and Frequency Scaling (AVFS), Triple Modular Redundancy (TMR) and clock-gating while the system is on-line. Additionally, flexibility as an inherent multiprocessor feature enables dynamical adaptation of the system to the current requirements. Putting all together, a balanced level between the two key metrics is achieved. We conduct numerous experiments to show the advantages of the proposed approach. Finally, we use the results to confirm the benefits and the effectiveness of the framework.

关键词： Measurement Adaptive systems Power demand Redundancy Complexity theory system analysis and design Multiprocessing systems

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system-Level Test: State of the Art and Challenges 27

System-Level Test: State of the Art and Challenges

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Appello, D. Chen, H. H. Sauer, M. Polian, I Bernardi, P. Reorda, M. Sonza STMicroelect Srl Automot Prod Grp Geneva Switzerland MediaTek Inc Hsinchu Taiwan Advantest Europe Munich Germany Univ Stuttgart Stuttgart Germany Politecn Torino Turin Italy

ISBN: (纸本)9781665433709

system-level test (SLT) is gaining in importance in modern test flows. This paper summarizes recent industrial findings from three companies and discusses some of the still open questions. The first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. The third report explores the role of marginalities among SLT fails. The post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors.

关键词： system Level Test reliability quality ATE

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Radiation-Induced Errors in the Software Level of Real-Time Soft Processing system

Radiation-Induced Errors in the Software Level of Real-Time ...

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ieee symposium on On-line testing (IOLTS)

作者： Corrado De Sio Daniele Rizzieri Andrea Portaluri Salvatore G. La Greca Sarah Azimi Dipartimento di Automatica e Informatica (DAUIN) Politecnico di Torino Turin Italy

FPGAs' and programmable hardware's high performance and flexibility have made them a reasonable choice for space-oriented applications, although susceptible to soft errors. This paper proposes a comprehensive analysis of the effects of microarchitectural faults on soft processors due to radiations, identifying the hardware sources of errors and how they propagate to software-level.

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Transmission line Based CDM ESD Current Target to Overcome Bandwidth Limitations

Transmission Line Based CDM ESD Current Target to Overcome B...

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international symposium on Electromagnetic Compatibility (EMC Europe)

作者： Feltner, Gabriel Pommerenke, David Zeitlhoefler, Lena zur Nieden, Friedrich Graz Univ Technol Inst Elect Graz Austria Christian Doppler Lab EMC Aware Robust Elect Syst Graz Austria Infineon Technol AG Neubiberg Germany

ISBN: (纸本)9798350307351;9798350343045

Reducing charged device model (CDM) electrostatic discharge (ESD) target levels for advanced integrated circuits (ICs) and systems on chip (SoCs) enables cost-effective manufacturing. Notably fast rise times, as low as 20 ps, have been observed for CDM events below 250 V. Previous investigations have highlighted fast rise times as critical parameters for damage in CDM testing of devices. These rapid rise times result in spectral frequency content exceeding 17.5 GHz, surpassing the bandwidth of existing CDM current targets employing disk resistors. To overcome this bandwidth limitation, a CDM current target comprised of parallel-connected transmission lines has been developed. Full-wave simulation results confirm the design of an initial prototype. Time-domain measurements conducted in an experimental setup exhibit exemplary results, with potential for further enhancement through de-embedding techniques.

关键词： Electrostatic discharge charged device model (CDM) current measurement low voltage CDM

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TAURUM P2T: Advanced Secure CAN-FD Architecture for Road Vehicle 27

TAURUM P2T: Advanced Secure CAN-FD Architecture for Road Veh...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Oberti, Franco Sanchez, Ernesto Savino, Alessandro Parisi, Filippo di Carlo, Stefano Politecn Torino Control & Comp Engn Dept Turin Italy PUNCH Torino SpA Turin Italy

ISBN: (纸本)9781665433709

Interconnected devices are growing very fast in today's automotive market, providing new and complex features that cover very different domains. This vast and continuous requirement for new features brings to impact areas categorized as real-time safety-critical devices, opening the possibility to add potential vulnerabilities. By analyzing the security vulnerabilities within vehicle networks, this paper aims at proposing a new generation of a secure architecture based on Controller Area Network (CAN) called TAURUM P2T. This new architecture looks at mitigating the vulnerabilities found in the current network systems of road vehicles by introducing a low-cost and efficient solution based on the introduction of a Secure CAN network able to implement a novel key provisioning strategy. The proposed architecture has been implemented, resorting to a commercial Multi-Protocol Vehicle Interface module, and the obtained results experimentally demonstrate the approach's feasibility.

关键词： CAN-bus Rolling secret key Automotive Secure Embedded system Secure CAN Network ECC No secret key Infrastructure

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SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation 27

SafeTI: a Hardware Traffic Injector for MPSoC Functional and...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Sala, Oriol Alcaide, Sergi Cabo, Guillem Bas, Francisco Lorenzo, Ruben Benedicte, Pedro Trilla, David Gil, Guillermo Mazzocchetti, Fabio Abella, Jaume Barcelona Supercomp Ctr BSC Barcelona Spain Univ Politecn Catalunya UPC Barcelona Spain

ISBN: (纸本)9781665433709

Functional and timing validation of safety-related MPSoCs requires testing specific traffic patterns in the on-chip interconnects. Generally, testing needs to be performed by using software tests whose degree of control on the traffic generated is indirect, and limited to behavior that can be triggered by software, thus often unable to produce traffic generated by peripherals. Therefore, untested traffic scenarios can be abundant and, to a large extent, it is hard to know what traffic scenarios have been effectively tested. This paper presents the safe traffic injector, SafeTI, which allows injecting programmable traffic in AMBA AHB interconnects with high flexibility and degree of control, thus easing achieving high coverage in terms of traffic scenarios tested, and mitigating the uncertainty due to the difficulties to relate software tests with actual traffic scenarios tested. We also integrate successfully the SafeTI in an industrial MPSoC for the space domain proving the effectiveness of the proposed traffic injector.

关键词： Uncertainty Traffic control Aerospace electronics Software Hardware Timing system-on-chip

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Application of TVS Models for SEED Simulation of a Variety of TVS Devices

Application of TVS Models for SEED Simulation of a Variety o...

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Joint Asia-Pacific international symposium on Electromagnetic Compatibility / international Conference on Electromagnetic Interference and Compatibility (APEMC/INCEMIC)

作者： Shen, Li Xu, Yang Holland, Steffen Bub, Sergej Pommerenke, David Beetner, Daryl Missouri Univ Sci & Technol Missouri S&T EMC Lab Rolla MO 65409 USA Nexperia GmbH Hamburg Germany Graz Univ Technol SAL Graz EMC lab Graz Austria

ISBN: (纸本)9798350338348

Accurate models of transient voltage suppression (TVS) devices are important for determining the suitability of electrostatic discharge (ESD) protection strategies early in the design process. An improved TVS model is used in the following paper to represent a variety of TVS devices, including a snapback device, non-snapback device, and a varistor. The models include recent improvements to represent conductivity modulation and the overall shape of the TVS device's transient response. The models are tuned based on characterizations of these protection devices using a transmission line pulse (TLP), and are then used in a system efficient ESD design (SEED) simulation to predict the transient voltages and currents in a system consisting of an off-chip TVS, an IC with on-chip ESD protection, and a PCB trace in between. Simulated transient voltage and current waveforms closely match measurements both when testing the TVS devices by themselves and in SEED simulations. Peak and quasistatic currents through the TVS and on-chip diode were typically captured within about 10% or less across the devices tested while varying both the rise time and level of the injected TLP.

关键词： electrostatic discharge simulation system-level modeling transient voltage suppression

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design and Implementation of a Wireless Sensor Network Based on the ESP32 for IoT Applications 66

Design and Implementation of a Wireless Sensor Network Based...

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66th international symposium ELMAR, ELMAR 2024

作者： Sokol, Miroslav Galajda, Pavol Jurik, Patrik Pribula, Frederik Sokolova, Zuzana Technical University of Kosice Dept. of Electronics and Multimedia Telecommunications Kosice Slovakia

ISBN: (纸本)9798350375411

This paper provides a general description of the implementation of a sensor network based on the system-on-Chip (SoC) ESP32. The hardware, software solutions, and other components of the designed network are presented. The wireless sensor network consists of sensor nodes and central nodes, which communicate using Wi-Fi, ESP-NOW protocols, and the MQTT protocol designed specifically for IoT devices. The measured data from the nodes are visualized and monitored through the Home Assistant service. The design of the sensor network focuses on creating a robust, low-power, and user-friendly network without relying on third-party devices and solutions. As part of the functionality verification, testing and data visualization were carried out over several months. © 2024 ieee.

关键词： Sensor nodes

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