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检索条件"任意字段=IEEE International Symposium on On-Line Testing and Robust System Design"

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High-level Intellectual Property Obfuscation via Decoy Constants 27

High-level Intellectual Property Obfuscation via Decoy Const...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Aksoy, Levent Nguyen, Quang-Linh Almeida, Felipe Raik, Jaan Flottes, Marie-Lise Dupuis, Sophie Pagliarini, Samuel Tallinn Univ Technol Dept Comp Syst Tallinn Estonia Univ Montpellier LIRMM Montpellier France

ISBN: (纸本)9781665433709

This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as neural networks and filters, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoys. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account;an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) based attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants - instead of arbitrary circuit nodes - become key-protected.

关键词： hardware obfuscation reverse engineering IP obfuscation SAT attack digital FIR filter design

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On the Development of Prognostics and system Health Management (PHM) Techniques for ReRAM Applications

On the Development of Prognostics and System Health Manageme...

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ieee symposium on On-line testing (IOLTS)

作者： Jose Cayo Matias Melivilu Antonio Rubio Ioannis Vourkas Dept. of Electronic Engineering Universidad Tecnica Federico Santa Maria Valparaiso Chile Dept. of Electronic Engineering Universitat Politècnica de Catalunya Barcelona Spain

The resistive switching (RS) technology has many promising applications, but the inherent variability of RS devices has been an important obstacle for the progress towards mass production. Nonidealities of device switching performance have been widely modeled so far, and device degradation has been addressed through testing for fault diagnosis. However, online soft-error “prognosis” concerning both the progressive degradation and transition faults, has been given little consideration. In this direction, we present preliminary results towards the development of prognostics and system health management (PHM) techniques for resistive memory (ReRAM) applications. We propose addressing soft errors through a rich in context scheme used to encode binary information in form of resistance. In out simulations we assumed a ReRAM driver with multi-level READ capability and developed an enhanced progressive feedback-WRITE scheme to ensure not only successful WRITE and reliable READ operations, but also to permit the early online prognosis of potential device failure. Preliminary system-level simulation results validate the expected functionality and represent a reasonable approach towards the design of robust ReRAM controllers.

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Silent Data Corruptions in Computing: Understand and Quantify

Silent Data Corruptions in Computing: Understand and Quantif...

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ieee symposium on On-line testing (IOLTS)

作者： Thiago Macieira Sankar Gurumurthy Sudhanva Gurumurthi Amr Haggag George Papadimitriou Dimitris Gizopoulos Intel Corp Portland Oregon USA AMD Inc Austin Texas USA Arm Ltd San Fransisco California USA University of Athens Greece

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

Ensuring the reliability of hardware components is essential, particularly in large-scale installations that demand computing capabilities (cloud data centers, supercomputers, edge systems). Silent data corruptions (SDCs) due to latent defects, manufacturing testing escapes, aging, marginal defects present significant challenges to system integrity and performance. Such silicon defects are often subtle and intermittent, manifesting under specific conditions, thus complicating detection and diagnosis. In this paper, the views of the CPU design powerhouses (Intel, AMD, Arm) that deliver most of the computing power of our days at scale, are summarized. These industry giants share their insights on the challenges posed by SDCs and discuss the strategies and technologies they employ to mitigate these issues.

关键词： Industries Data centers Image edge detection Supercomputers Hardware Silicon system-on-chip

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Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing 27

Dynamic Verification of Approximate Computing Circuits using...

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27th ieee international symposium on on-line testing and robust system design (IOLTS)

作者： Yoshisue, Kazuki Masuda, Yutaka Ishihara, Tohru Nagoya Univ Nagoya Aichi Japan JST PRESTO Nagoya Aichi Japan

ISBN: (纸本)9781665433709

Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This paper proposes a novel dynamic verification methodology of the AC circuit. The key idea of the proposed methodology is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed methodology additionally embeds the design Under Test (DUT) mechanisms into the calculation part of computational quality. Thanks to the integration of CGF and DUT mechanism, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed methodology and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed methodology achieves the target coverage three times faster than the random test.

关键词： Approximate Computing (AC) Coverage-based Grey-box Fuzzing (CGF) design Under Test (DUT) mechanism verification computational quality

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ML-Based Online design Error Localization for RISC-V Implementations

ML-Based Online Design Error Localization for RISC-V Impleme...

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ieee symposium on On-line testing (IOLTS)

作者： Hardi Selg Maksim Jenihhin Peeter Ellervee Jaan Raik Computer Systems Tallinn University of Technology Estonia

The accelerated growth of computing systems' complexity makes comprehensive design verification challenging and time-consuming. In practice, hard-to-model complex environments are unfeasible to be simulated exhaustively within a reasonable time frame. Therefore, some corner-case conditions can be overlooked and design errors might escape to the final product. This means that it is imperative for the system to be able to detect and locate bugs to enable self-repair. This is particularly crucial during long-term remote missions in order to apply graceful degradation. This paper proposes a novel online design error localization methodology for microprocessors by immediate analysis of traced and buffered signals upon a failure detection event, using a pre-trained Neural Network (NN) and existing processor components, i.e. trace buffers and AI accelerators. An in-house Neural Architecture Search (NAS) framework is used to train a tailored Multi-Layer Perceptron (MLP) NN for error localization at the microprocessor module-level resolution. The proposed approach is validated by simulating a RISC-V implementation with different workload programs. It is demonstrated to be capable of localizing the microprocessor module of bug origin with 92.81% accuracy, on average.

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On Approaching Multivariate IC Pre-silicon Verification Using ML-based Adaptive Algorithms

On Approaching Multivariate IC Pre-silicon Verification Usin...

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ieee symposium on On-line testing (IOLTS)

作者： Alecsandra Rusu Emilian David Marina-Dana Ţopa Vasile Grosu Andi Buzo Georg Pelz Technical University of Cluj-Napoca Cluj-Napoca Romania Infineon Technologies Bucharest Romania “Gheorghe Asachi” Technical University Iasi Romania Infineon Technologies AG Neubiberg Germany

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

This paper introduces several solutions for multivariate extension of a previously designed single response adaptive pre-silicon integrated circuit verification approach employing machine learning algorithms. These techniques aim to achieve the most accurate identification of worst-case circuit behavior through simultaneously modeling multiple electrical parameters (EP). The effectiveness of the proposed methods was validated through extensive testing on a large and diverse set of synthetic test functions that intend to replicate the behavior of real circuits. The algorithms consistency and accuracy are also validated on a real Low Dropout Voltage Regulator (LDO) circuit.

关键词： Adaptation models Accuracy Regulators Machine learning algorithms Integrated circuit modeling Voltage control system analysis and design

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Can social media shape the security of next-generation connected vehicles?

Can social media shape the security of next-generation conne...

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ieee symposium on On-line testing (IOLTS)

作者： Nicola Scarano Luca Mannella Alessandro Savino Stefano Di Carlo Politecnico Di Torino Department of Control Computer Engineering Turin Italy

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

abstract-The increasing adoption of connectivity and electronic components in vehicles makes these systems valuable targets for attackers. While automotive vendors prioritize safety, there remains a critical need for comprehensive assessment and analysis of cyber risks. In this context, this paper proposes a Social Media Automotive Threat Intelligence (SOCMATI) framework, specifically designed for the emerging field of automotive cybersecurity. The framework leverages advanced intelligence techniques and machine learning models to extract valuable insights from social media. Four use cases illustrate The framework’s potential by demonstrating how it can significantly enhance threat assessment procedures within the automotive industry.

关键词： Industries Social networking (online) Shape Machine learning Threat assessment Safety system analysis and design

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Application of Feedforward Compensation in the design of Active Front-End Converters 31

Application of Feedforward Compensation in the Design of Act...

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ieee 31st international symposium on Industrial Electronics (ISIE)

作者： Jahromi, Mahda Simon Fraser Univ SEE Burnaby BC Canada BC Canada Vancouver BC Canada

ISBN: (纸本)9781665482400

A voltage-sourced inverter with a robust current control scheme is the building block of an Active Front-End converter (AFE). This paper presents a control method that improves the performance of voltage-sourced current controlled inverters. The proposed control method improves the undesirable start-up transients and disengages the dynamics of the inverter from those of the AC grid with which it interfaces. As AFEs are ever increasingly being used to condition the power for integration of intermittent renewables in conventional grids, these features allow the system to achieve better performance with greater longevity. A comparison study is provided to show the advantages and disadvantages of the proposed method with respect to conventional alternatives in the literature. The analytical results and the conclusions are validated by testing the proposed model in different scenarios. The enhanced control loop is also put to test on a quadrature model of a practical AFE that utilizes a 12 pulse Neutral Point Clamped inverter.

关键词： Active Front End Converters Voltage-Sourced Inverter Feedforward Compensation Current Controlled Inverters Neutral Point Clamped Bridges

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On the Reliability of Clock Monitoring Units for Safety Critical Applications’ Microcontrollers*

On the Reliability of Clock Monitoring Units for Safety Crit...

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ieee symposium on On-line testing (IOLTS)

作者： M. Zhupa M. Naldi M. Omaña C. Metra DEI University of Bologna Bologna Italy

ISBN: (数字)9798350370553

ISBN: (纸本)9798350370560

In multi-core microcontrollers adopted for safety critical applications, such as automotive, the frequency of clock signals is typically monitored by dedicated Clock Monitor Units (CMUs), whose correct operation is essential for the microcontroller correct operation and system’s safety. We analyse the effects of resistive bridging faults and transient faults possibly affecting a typical CMU. We will show that $39 \%$ of the considered CMU resistive bridging faults do not result in a CMU output error message, thus remaining latent. Depending on the value of their connecting resistance, up to the $49 \%$ of the latent bridging faults can make the CMU unable to indicate the presence of a monitored clock signal with an incorrect frequency, with potential catastrophic consequences for the microcontroller correct operation and system’s safety. Instead, as for transient faults, we will show that they can be reasonably considered to do not constitute a serious risk for system’s safety.

关键词： Resistance Microcontrollers Safety Reliability Transient analysis Monitoring system analysis and design

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Environmental Characterization of a Fluorescence Detecting Point of Care system 66

Environmental Characterization of a Fluorescence Detecting P...

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2023 ieee 66th international Midwest symposium on Circuits and systems, MWSCAS 2023

作者： Nguyen, Vi T. Christen, Jennifer Blain School of Biological and Health Systems Engineering Arizona State University TempeAZ United States School of Electrical Computer and Energy Engineering Arizona State University TempeAZ United States

ISBN: (纸本)9798350302103

Point of care (POC) systems are being developed as alternative methods for disease detection in low resource settings. POC systems have the potential to provide quick and accurate results comparable to traditional laboratory tests which can take days to receive results. Our group has developed a POC system called a reader that was tested in different environmental conditions to simulate and predict performance in the field. Different housing configurations for the reader were tested in various light settings including indoor lighting, outdoor shade, and sunlight. The findings help to drive future design iterations of the reader to optimize fluorescent detection of isothermal assays. Stability testing of the reader was also investigated at different temperatures. The reader was found to have robust performance at room temperature and temperatures optimal for running isothermal assays. © 2023 ieee.

关键词： environment fluorescence isothermal assay lighting nucleic acid point of care stability temperature

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