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检索条件"任意字段=IEEE International Symposium on Parallel and Distributed Processing with Applications"

共 16627 条记录，以下是151-160 订阅

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Automatic parallel Pattern Detection in the Algorithm Structure Design Space 30

Automatic Parallel Pattern Detection in the Algorithm Struct...

引用

30th ieee international parallel and distributed processing symposium (IPDPS)

作者： Huda, Zia Ul Atre, Rohit Jannesari, Ali Wolf, Felix Tech Univ Darmstadt Lab Parallel Programming Darmstadt Germany Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781509021406

parallel design patterns have been developed to help programmers efficiently design and implement parallel applications. However, identifying a suitable parallel pattern for a specific code region in a sequential application is a difficult task. Transforming an application according to support structures applicable to these parallel patterns is also very challenging. In this paper, we present a novel approach to automatically find parallel patterns in the algorithm structure design space of sequential applications. In our approach, we classify code blocks in a region according to the appropriate support structure of the detected pattern. This classification eases the transformation of a sequential application into its parallel version. We evaluated our approach on 17 applications from four different benchmark suites. Our method identified suitable algorithm structure patterns in the sequential applications. We confirmed our results by comparing them with the existing parallel versions of these applications. We also implemented the patterns we detected in cases in which parallel implementations were not available and achieved speedups of up to 14x.

关键词： parallelism parallel patterns task parallelism

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Blockchain-based Security Architecture for distributed Cloud Storage 15

Blockchain-based Security Architecture for Distributed Cloud...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Li, Jiaxing Liu, Zhusong Chen, Long Chen, Pinghua Wu, Jigang Guangdong Univ Technol Sch Comp Sci & Technol Guangzhou Guangdong Peoples R China

ISBN: (纸本)9781538637906

With the development of ICT industry, the volume of produced data is experiencing tremendous growth, which motivates more demands of storage capacity. Because of the limited storage capacity of users' terminals, more and more applications prefer to upload data to cloud platforms. However, it is well known that security should not be neglected in existing cloud storage architectures. Motivated by the increasing popularity of emerging blockchain technology, we propose a blockchain-based security architecture for distributed cloud storage. Moreover, we customize a genetic algorithm to solve the file block replica placement problem between multiple users and multiple data centers in the distributed cloud storage environment. Numerical experimental results show that the proposed architecture outperforms the traditional cloud storage architectures in terms of security, with acceptable network transmission delay.

关键词： cloud storage security blockchain architecture distributed

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A High-Performance Accelerator for Floating-Point Matrix Multiplication 15

A High-Performance Accelerator for Floating-Point Matrix Mul...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Jia, Xun Wu, Gunning Xie, Xianghui State Key Lab Math Engn & Adv Comp Wuxi 214125 Peoples R China

ISBN: (纸本)9781538637906

Matrix multiplication is a widely-used routine in science and engineering applications. Accelerating this routine is important, because applications with large-scale matrix multiplication are increasingly common, especially in the area of high-performance computing (HPC). However, existing computing platforms including CPU, GPGPU and FPGA suffer from unsatisfactory performance or efficiency for this routine. In this paper, we propose a high-performance accelerator for double-precision floating-point matrix multiplication, and build a performance model for design space exploration based on a memory access scheduling. Impact of architecture parameters on accelerator performance and efficiency are evaluated and analyzed. Experimental results show that our proposed accelerator with 256 processing elements (PEs) can achieve a maximum performance of 767.99 GFLOPS and an efficiency of 99.99% for large-scale matrix multiplication, which is well suited to the requirement of HPC applications.

关键词： matrix multiplication linear array accelerator high-performance architecture

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Evaluating Functional Memory-Managed parallel Languages for HPC using the NAS parallel Benchmarks

Evaluating Functional Memory-Managed Parallel Languages for ...

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37th ieee international parallel and distributed processing symposium (IPDPS)

作者： Wilkins, Michael Weil, Garrett Arnold, Luke Ilardavellast, Nikos Dindat, Peter Northwestern Univ Evanston IL 60208 USA

ISBN: (纸本)9798350311990

Functional, memory-managed parallel languages (FMPLs) are a recent innovative approach to shared-memory parallel programming. Despite their rising prevalence in other areas, FMPLs have yet to gain traction in HPC. In this work, we explore the utility of FMPLs for HPC by re-implementing the NAS parallel Benchmarks in an FMPL. For this study, we ported the benchmarks into the parallel ML language. We discuss the advantages and disadvantages of using parallel ML for HPC applications based on our development experience. We compare the performance of our parallel ML implementation to the existing C/OpenMP version. The FMPL implementations are 1.02x-5.76x slower compared to OpenMP. Our positive development experience combined with some competitive performance results suggest that FMPLs have the potential to become a viable choice for HPC applications. We conclude by describing our future work to automatically manage distributed memory within an FMPL, creating a compelling new programming model for HPC.

关键词： Application programming interfaces (API)

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Dynamic Frequency Scaling for Energy Consumption Reduction in Synchronous distributed applications 12

Dynamic Frequency Scaling for Energy Consumption Reduction i...

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12th ieee international symposium on parallel and distributed processing with applications (ISPA)

作者： Charr, Jean-Claude Couturier, Raphael Fanfakh, Ahmed Giersch, Arnaud Univ Franche Comte FEMTO ST Inst IUT Belfort Montbeliard F-90016 Belfort France

ISBN: (纸本)9781479942930

Dynamic Voltage Frequency Scaling (DVFS) can be applied to modern CPUs. This technique is usually used to reduce the energy consumed by a CPU while computing. Thus, decreasing the frequency reduces the power consumed by the CPU. However, it can also significantly affect the performance of the executed program if it is compute bound and if a low CPU frequency is selected. Therefore, the chosen scaling factor must give the best possible trade-off between energy reduction and performance. In this paper we present an algorithm that predicts the energy consumed with each frequency gear and selects the one that gives the best ratio between energy consumption reduction and performance. This algorithm works online without training or profiling and has a very small overhead. It also takes into account synchronous communications between the nodes that are executing the distributed algorithm. The algorithm has been evaluated over the SimGrid simulator while being applied to the NAS parallel benchmark programs. The results of the experiments show that it outperforms other existing scaling factor selection algorithms.

关键词： Benchmarktesting Degradation Energyconsumption Predictionalgorithms Programprocessors Time-frequencyanalysis Dynamicvoltagefrequencyscaling homogeneouscluster messagepassingprograms central processing units energy consumption Energy sources dynamic frequency deterioration Scale factor Energy conservation

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Secure Cloud Computing: Communication Protocol for Multithreaded Fully Homomorphic Encryption for Remote Data processing 15

Secure Cloud Computing: Communication Protocol for Multithre...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Oppermann, Alexander Toro, Federico Grasso Yurchenko, Artem Seifert, Jean-Pierre PTB Dept Metrol IT 8 5 Berlin Germany Tech Univ Berlin Secur Telecommun Berlin Germany

ISBN: (纸本)9781538637906

A significant disadvantage of fully homomorphic encryption is the long periods of time needed to process encrypted data, due to its complex and CPU-intensive arithmetic techniques. In this paper, a communication protocol is developed to ensure authenticity, integrity and privacy of measurement data across a distributed measuring system. The fully homomorphic encryption library LibScarab was extended by integer arithmetics, comparisons, decisions and multithreading to secure data processing. Furthermore, it enhances 32 and 64-bit arithmetic operations, improving them by a higher factor. This extension is integrated into a cloud computing architecture establishing privacy by design. The resulting parallelized algorithm solved the time constraint issues for smart meter gateway tariffs. Several tests were performed, fulfilling tariff specifications, where preserving privacy of accumulated data was necessary. It was concluded that this extension of the fully homomorphic encryption library meets the requirements of real world applications.

关键词： Libraries Encryption Cloud computing Protocols Servers

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parallel Huffman Decoding: Presenting a Fast and Scalable Algorithm for Increasingly Multicore Devices 15

Parallel Huffman Decoding: Presenting a Fast and Scalable Al...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Johnston, Beau McCreath, Eric C. Australian Natl Univ Res Sch Comp Sci Canberra ACT Australia

ISBN: (纸本)9781538637906

Huffman encoding provides a simple approach for lossless compression of sequential data. The length of encoded symbols varies and these symbols are tightly packed in the compressed data. Thus, Huffman decoding is not easily parallelisable. This is unfortunate since it is desirable to have a parallel algorithm which scales with the increased core count of modern systems. This paper presents a parallel approach for decoding Huffman codes which work by decoding from every location in the bit sequence then concurrently combining the results into the uncompressed sequence. Although requiring more operations than serial approaches the presented approach is able to produce results marginally faster, on sufficiently large data sets, then that of a simple serial implementation. This is achieved by using the large number of threads available on modern GPUs. A variety of implementations, primarily OpenCL, are presented to demonstrate the scaling of this algorithm on CPU and GPU hardware in response to cores available. As devices with more cores become available, the importance of such an algorithm will increase.

关键词： Decoding Program processors Hardware Partitioning algorithms Multicore processing Encoding Image coding

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parallel Subgraph Counting for Multicore Architectures 12

Parallel Subgraph Counting for Multicore Architectures

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12th ieee international symposium on parallel and distributed processing with applications (ISPA)

作者： Aparicio, David Ribeiro, Pedro Silva, Fernando Univ Porto CRACS P-4169007 Oporto Portugal Univ Porto INESC TEC LA Fac Ciencias P-4169007 Oporto Portugal

ISBN: (纸本)9781479942930

Computing the frequency of small subgraphs on a large network is a computationally hard task. This is, however, an important graph mining primitive, with several applications, and here we present a novel multicore parallel algorithm for this task. At the core of our methodology lies a state-of-the-art data structure, the g-trie, which represents a collection of subgraphs and allows for a very efficient sequential search. Our implementation was done using Pthreads and can run on any multicore personal computer. We employ a diagonal work sharing strategy to dynamically and effectively divide work among threads during the execution. We assess the performance of our Pthreads implementation on a set of representative networks from various domains and with diverse topological features. For most networks, we obtain a speedup of over 50 for 64 cores and an almost linear speedup up to 32 cores, showcasing the flexibility and scalability of our algorithm. This paves the way for the usage of such counting algorithms on larger subgraph and network sizes without the obligatory access to a cluster.

关键词： parallel Algorithms Adaptive Load Balancing Complex Networks Graph Mining G-Tries

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Fast GPU Implementation of Dumer's Algorithm Solving the Syndrome Decoding Problem 19

Fast GPU Implementation of Dumer's Algorithm Solving the Syn...

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19th ieee international symposium on parallel and distributed processing with applications (ieee ISPA)

作者： Narisada, Shintaro Fukushima, Kazuhide Kiyomoto, Shinsaku KDDI Res Inc Fujimino Japan

ISBN: (纸本)9781665435741

The syndrome decoding problem (SDP) is a security basis for code-based cryptographic algorithms such as the McEliece cryptosystem, which has been selected as a finalist for the third round of the post-quantum cryptography (PQC) standardization project organized by the National Institute of Standards and Technology (NIST). Information set decoding (ISD) is a general term for algorithms that efficiently solve SDPs based on combinatorial enumeration. In this paper, we focused on Dumer's algorithm, which is relatively lightweight among the ISD algorithms;and proposed a multi-parallel Dumer's algorithm optimized for computing devices that perform massively parallel processing. We implemented our algorithm on a GPU and tested it by solving some SDP instances in the decoding challenge hosted by Inria. We report that our algorithm first solved a 1161-dimensional SDP in the Goppa-McEliece setting in approximately 380 hours, which has a computational complexity of 2(52). Our results contribute to a more detailed security analysis for code-based cryptosystems.

关键词： Terms Syndrome Decoding Information Set Decoding Graphics processing Unit (GPU)

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ParaVis: A Library for Visualizing and Debugging parallel applications 33

ParaVis: A Library for Visualizing and Debugging Parallel Ap...

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33rd ieee international parallel and distributed processing symposium (IPDPS)

作者： Danner, Andrew Newhall, Tia Webb, Kevin C. Swarthmore Coll Comp Sci Dept Swarthmore PA 19081 USA

ISBN: (纸本)9781538655559

This paper presents ParaVis, a visualization library designed to aid programmers' understanding of their parallel programs and to help them identify bugs with parallelization. ParaVis is particularly targeted for programmers who are first learning parallel programming or learning a new parallel language. It provides easy-to-use C and C++ interfaces to create 2D animations of parallel computation that help programmers understand parallel data decomposition patterns. These visualizations are also helpful in illustrating errors in parallel programs. Additionally, because students often find visualization fun, the use of our library often results in students developing interesting extensions to problems, thus promoting a deeper understanding and richer experience with parallel computing. Currently we provide support and sample implementations for pthreads, OpenMP, CUDA, and sequential applications. To test its effectiveness for parallel computing education, we deployed ParaVis for lab assignments in both intermediate and upper level courses. We present example applications, and evaluate the use of the library across our undergraduate CS curriculum.

关键词： visualization library parallel computing CS Education CUDA pthreads OpenMP

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