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检索条件"任意字段=IEEE International Symposium on Parallel and Distributed Processing with Applications"

共 16627 条记录，以下是271-280 订阅

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Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators 36

Combined Application of Approximate Computing Techniques in ...

引用

36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Russo, Enrico Palesi, Maurizio Patti, Davide Lahdhiri, Habiba Monteleone, Salvatore Ascia, Giuseppe Catania, Vincenzo Univ Catania Catania Italy Niccolo Cusano Univ Rome Italy ESIEE Paris Noisy Le Grand France

ISBN: (纸本)9781665497473

This paper applies Approximate Computing (AC) techniques to the main elements which form a DNN hardware accelerator, namely, computation, communication, and memory subsystems. Specifically, approximate multipliers for computation, link voltage swing reduction for communication, voltage over-scaling for the internal SRAM memory, and lossy compression of the external DRAM memory are considered. The different AC techniques are applied in isolation as well as in conjunction with each other. A set of representative CNN models are mapped onto the approximated hardware accelerators and the trade-offs performance vs. energy vs. accuracy are derived for the execution of CNN inferences.

关键词： distributed processing Conferences Computational modeling Approximate computing Random access memory Voltage Hardware acceleration

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A Multi-Level parallel Algorithm for Detection of Single Scatterers in SAR Tomography 33

A Multi-Level Parallel Algorithm for Detection of Single Sca...

引用

33rd Euromicro international Conference on parallel, distributed, and Network-Based processing, PDP 2025

作者： Russo, Massimiliano Nisar, Mehwish Pauciullo, Antonio Imperatore, Pasquale Lapegna, Marco Romano, Diego University of Naples Federico II Dept. of Mathematics and Applications Naples Italy National Research Council Naples Italy Inst. for High Performance Computing and Networking National Research Council Naples Italy

ISBN: (纸本)9798331524937

Synthetic Aperture Radar (SAR) tomography is an advanced technique for monitoring deformations of the Earth's surface. However, the computational complexity of SAR tomography algorithms often restricts their application to large-scale datasets. To address this issue, we introduce a multi-level parallel implementation of a single scatterer detection algorithm specifically designed to exploit the capabilities of modern heterogeneous High-Performance Computing (HPC) systems. By efficiently distributing the computational workload at different levels across multiple processing units, our parallel approach significantly reduces processing time, facilitating the analysis of extensive SAR datasets. We assess the performance of our parallel implementation using real-world SAR data, showcasing its effectiveness in enhancing both the efficiency and scalability of SAR tomography. Our work contributes to advancing remote sensing techniques and offers valuable insights into the application of HPC for large-scale environmental monitoring. © 2025 ieee.

关键词： Light scattering

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ActIPP: Active Intellectual Property Protection of Edge-Level Graph Learning for distributed Vehicular Networks 22

ActIPP: Active Intellectual Property Protection of Edge-Leve...

引用

22nd ieee international symposium on parallel and distributed processing with applications, ISPA 2024

作者： Yang, Xiao Li, Gaolei Dong, Mianxiong Ota, Kaoru Zhang, Chaofeng Peng, Xiting Li, Jianhua Shanghai Jiao Tong University China Muroran Institute of Technology Japan Advanced Institute of Industrial Technology China Shenyang University of Technology China

ISBN: (纸本)9798331509712

Edge-Level Graph Learning System (EGLS) exhibits diverse applicability in management of distributed vehicular networks, e.g., flow prediction, route planning, and accident forecasting. For the EGLS training, expensive hardware resource consumption, traffic data collection, and dedicated training procedures make the learning algorithms become valuable intellectual property (IP) for the EGLS owner (e.g., Uber and Lyft), and they cannot tolerate the infringement act of their models' intellectual property. To enhance its IP protection, we present ActIPP, the first active IP protection methodology for EGLS, which incorporates a built-in access control function in the model to safeguard against unauthorized queries. Specifically, it is achieved via a creative edge backdoor mechanism, wherein the edge training samples are poisoned via user-specific access tokens to induce legal outputs from a well-trained EGLS model for authorized users. Moreover, related token regulating strategies were proposed to dynamically realize the addition and revocation of user tokens by model retraining to guarantee access control in EGLS. Additionally, a Graph Mutual Information-based adaptive token generation method is presented to augment the access control embedding. Based on experiments with various real-world datasets, ActIPP demonstrates high success rates of IP protection (accuracy drop © 2024 ieee.

关键词： Access control models

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A Scalable parallel Partition Tridiagonal Solver for Many-Core and Low B/F Processors 36

A Scalable Parallel Partition Tridiagonal Solver for Many-Co...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Mitsuda, Tatsuya Ono, Kenji Kyushu Univ Grad Sch Fukuoka Japan Kyushu Univ Fac Informat Sci & Elect Engn Fukuoka Japan Kyushu Univ Res Inst Informat & Technol Fukuoka Japan

ISBN: (纸本)9781665497473

Tridiagonal systems are among the most fundamental computations in science, engineering, and mathematics, and one solver used in such systems is Tree Partitioning Reduction (TPR), which is a divide-and-conquer method that solves large-scale linear equations by dividing them and then computing the parts in parallel within different local memory threads. Herein, we propose an improved TPR algorithm that has a parallel cyclic reduction flavor, with which we reduced the number of algorithm steps by approximately half while simultaneously increasing arithmetic intensity and cache reusability. A performance evaluation conducted on an Intel Skylake-SP microprocessor showed a high hit ratio for the L1 cache and that our solver was as much as 31 times faster on 32 threads for 262144 equations. In the case of a Nvidia Tesla P100 GPU, our method processed 10 MRow/s more than TPR and cuSPARSE.

关键词： Tridiagonal system GPU parallel computing Multi/many-core

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Hardware-in-the-Loop Implementation of distributed SDR Systems and Throughput-Optimal Coordinated Transmissions

Hardware-in-the-Loop Implementation of Distributed SDR Syste...

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ieee international symposium on Dynamic Spectrum Access Networks (ieee DySPAN)

作者： Sambrama Kantheti, Venkata Srirama Rohit Lin, Shih-Chun Chu, Liang C. Blasch, Erik N Carolina State Univ Raleigh NC 27695 USA Lockheed Martin Space Sunnyvale CA USA Air Force Res Lab Rome NY USA

ISBN: (纸本)9798350317657;9798350317640

Recent breakthroughs in wireless networks have promised scalable coordinated transmissions for future ubiquitous communications, such as non-terrestrial low-earth orbit (LEO) satellite networks, for emerging commercial and military applications. However, overcoming the data throughput issue with such distributed radio systems in practical field trials and electromagnetic contested environments is challenging. This paper develops novel hardware-in-the-loop (HIL) prototyping and evaluation of a distributed software-defined radio (SDR) system and the corresponding optimal signal reception combining technique for maximizing multi-radio throughput. A programmable in-lab testbed with multiple SDR-mounted aerial devices and a transmission control protocol (TCP) backhaul is built to emulate LEO satellite channels and satellite coordination. A distributed maximum ratio combining (d-MRC), is provided and implemented to process multi-radio receptions for optimal spectral efficiency. Comprehensive over-the-air tests with both bit-streams and image transmissions validate our designed approach's real-world feasibility and its superior performance compared to an individual SDR throughput. Thus, this work introduces a HIL system integrations with coordinated commercial-off-the-shelf SDRs, providing a reference implementation for extensive wireless aerial use cases.

关键词： Hardware-in-the-loop (HIL) testbed multi-node receiver diversity eigen-spatial signal processing TCP sockets multimedia communications and non-terrestrial systems

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IoTinuum: The IoT Computing Continuum 20

IoTinuum: The IoT Computing Continuum

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20th Annual international Conference on distributed Computing in Smart Sensor Systems and the Internet of Things (DCOSS-IoT)

作者： Kamienski, Carlos Zyrianoff, Ivan Bittencourt, Luiz Fernando Di Felice, Marco Fed Univ ABC Santo Andre SP Brazil Univ Bologna Bologna Italy Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9798350369458;9798350369441

IoT smart applications must deal with the inherently distributed nature of IoT infrastructures that may vary among different deployments. For example, in urban environments, some deployments may require distributed edge nodes to support the sensors and actuators, while others may skip this processing stage and go directly to the cloud. We propose the concept of an IoT Computing Continuum, or IoTinuum, with multiple computing stages spread over the distributed IoT infrastructure. We present the modeling and implementation of two urban use cases for a 6-stage IoTinuum: smart drone delivery and smart structural monitoring. In our experience, the IoTinuum improves the understanding of function placement in application development and reveals important performance tradeoffs.

关键词： edge computing fog computing IoT smart applications

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An Architectural Template for FPGA Overlays Targeting Data Flow applications

An Architectural Template for FPGA Overlays Targeting Data F...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Drewes, Anna Burtsev, Vitalii Gurumurthy, Bala Wilhelm, Martin Broneske, David Saake, Gunter Pionteck, Thilo Otto von Guericke Univ Magdeburg Germany

ISBN: (纸本)9798350364613;9798350364606

In this paper, we present a flexible and scalable architectural template for designing domain-specific FPGA overlays. The template can be parametrized in terms of number and size of tiles, communication topology and connectivity to external RAM. In addition to direct streaming connections between adjacent tiles for bulk data, it uses a novel lightweight packet based on-chip network for small data transfers. The tiles consist of configurable routing resources and the actual compute units, which are exchanged at runtime by means of dynamic partial reconfiguration. This allows the assembly of custom, varying data paths for processing data flow graphs in hardware. Since every connection within and at the edge of the template is AXI-Stream-compliant, it is highly extensible using standard IP cores and streaming-based High-Level Synthesis code, enabling plug-andplay deployment. The feasibility of our approach is demonstrated by means of an domain-specific overlay for analytical database query processing on a Xilinx Alveo U280 card. TPC-H queries and synthetic workloads are used as test cases. Insights from this demonstration system show that the resulting overlay does not affect the performance of the compute units and show the effectiveness of the lightweight packet-based on-chip network in saving routing resources.

关键词： FPGA Overlay Architectural Template Dynamic Partial Reconfiguration Data Flow Graphs Analytical Query processing

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Fully Dynamic Line Maintenance by Hybrid Programmable Matter 36

Fully Dynamic Line Maintenance by Hybrid Programmable Matter

引用

36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Nokhanji, Nooshin Flocchini, Paola Santoro, Nicola Carleton Univ Sch Comp Sci Ottawa ON Canada Univ Ottawa Sch Elect Engn & Comp Sci Ottawa ON Canada

ISBN: (纸本)9781665497473

Motivated by the manipulation of nanoscale materials, recent investigations have focused on hybrid systems where passive elements incapable of movement, called tiles, are manipulated by one or more mobile entities, called robots, with limited computational capabilities. Like in most self-organizing systems, the fundamental concern is with the (geometric) shapes created by the position of the tiles;among them, the line is perhaps the most important. The existing investigations have focused on formation of the shape, but not on its reconfiguration following the failure of some of the tiles. In this paper, we study the problem of maintaining a line formation in presence of fully dynamic failures: any tile can stop functioning at any time. We show how this problem can be solved by a group of very simple robots, with the computational power of deterministic finite automata.

关键词： Shape formation fault-tolerance hybrid programmable matter line maintenance distributed algorithms self-assembly

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Towards Accelerating k-NN with MPI and Near-Memory processing

Towards Accelerating k-NN with MPI and Near-Memory Processin...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Ahn, Hooyoung Kim, Seonyoung Park, Yoomi Han, Woojong Contini, Nick Ramesh, Bharath Abduljabbar, Mustafa Panda, Dhabaleswar K. Elect & Telecommun Res Inst Supercomp Technol Res Ctr Daejeon South Korea Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9798350364613;9798350364606

Message Passing Interface (MPI) is a common parallel programming model in High-Performance Computing fields. Recently, it has been widely used in Artificial Intelligence (Al) applications. However, the performance of those applications is limited by the memory wall problem, which is the performance gap between the processor and memory. To address these problems, we propose a novel computing architecture for accelerating k-NN query, which is the key operation of AI applications. The proposed computing architecture involves two or more computing nodes within a rack using the memory of an NMP device as a communication buffer and the accelerator of the NMP device for MPI collective communication. The superiority of the proposed method is that it reduces data copying during local computation and eliminates the network cost of gathering local computation results for global computation. Furthermore, it can enhance performance by processing data in the device's memory through near-memory processing. However, since these NMP devices are still in development, with no commercially available products currently, we have undertaken the task of developing them ourselves. Despite these circumstances, to demonstrate the feasibility of our proposed approach, we have implemented it in a single-node environment without making any unreasonable assumptions and have compared it with conventional approaches. Although we are using a single-node environment, we have designed a more sophisticated architecture, analyzed the time complexity, and compared the estimated performance of both the conventional and proposed approaches. We can conclude that the proposed computing architecture is feasible, and we anticipate an even more performance enhancement in a multi-node environment.

关键词： k-Nearest Neighbor Message Passing Interface Near-Memory processing Heterogeneous Computing

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POCA: a PYNQ Offloaded Cryptographic Accelerator on Embedded FPGA-based Systems

POCA: a PYNQ Offloaded Cryptographic Accelerator on Embedded...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Bertolini, Roberto A. Carloni, Filippo Conficconi, Davide Santambrogio, Marco Domenico Politecn Milan Dipartimento Elettron Informat & Bioingn Milan Italy

ISBN: (纸本)9798350364613;9798350364606

The pervasiveness of embedded systems across edge and connected devices is challenging their design, as sharing data securely via AES encryption is computationally intensive. This work proposes POCA, an FPGA-accelerated HW/SW library that performs AES cryptographic primitives with different modes and the most used key sizes. The HW/SW approach of POCA showcases the benefits of accelerated cryptographic primitives and the flexibility of a unified platform interface across different embedded systems by exploiting the Python PYNQ framework. POCA matches the multicore ARM crypto extensions on an Ultrascale+ ZU3EG while overwhelming SW performance.

关键词： HW/SW Library parallel AES FPGA

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