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检索条件"任意字段=IEEE International Symposium on Parallel and Distributed Processing with Applications"

共 16627 条记录，以下是281-290 订阅

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Automatic Detection of parallel applications Computation Phases

Automatic Detection of Parallel Applications Computation Pha...

引用

23rd ieee international parallel and distributed processing symposium

作者： Gonzalez, Juan Gimenez, Judit Labarta, Jesus UPC BSC Barcelona Spain

ISBN: (纸本)9781424437511

Analyzing parallel programs has become increasingly difficult due to the immense amount of information collected on large systems. The use of clustering techniques has been proposed to analyze applications. However while the objective of previous works is focused on identifying groups of processes with similar characteristics, we target a much finer granularity in the application behavior. In this paper, we present a tool that automatically characterizes the different computation regions between communication primitives in message-passing applications. This study shows how some of the clustering algorithms which may be applicable at a coarse grain are no longer adequate at this level. Density-based clustering algorithms applied to the performance counters offered by modern processors are more appropriate in this context. This tool automatically generates accurate displays of the structure of the application as well as detailed reports on a broad range of metrics for each individual region detected.

关键词： Message passing

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Vector prefix and reduction computation on coarse-grained, distributed-memory parallel machines 1

Vector prefix and reduction computation on coarse-grained, d...

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1st Merged international parallel processing symposium/symposium on parallel and distributed processing (IPPS/SPDP 1998)

作者： Bae, S Kim, D Ranka, S ETRI Parallel Programming Sect Taejon South Korea

ISBN: (纸本)0818684038

Vector prefix and reduction are collective communication primitives in which all processors must cooperate. We present two parallel algorithms, the direct algorithm and the split algorithm, for vector prefix and reduction computation on coarse-grained, distributed-memory parallel machines. Our algorithms are relatively architecture independent and can be used effectively in many applications such as Pack/Unpack, Array Prefix/Reduction Functions, and Array Combining Scatter Functions, which are defined in Fortran 90 and in High Performance Fortran. Experimental results on the CM-5 are presented.

关键词： parallel processing systems

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TATA: Throughput-Aware TAsk Placement in Heterogeneous Stream processing with Deep Reinforcement Learning 19

TATA: Throughput-Aware TAsk Placement in Heterogeneous Strea...

引用

19th ieee international symposium on parallel and distributed processing with applications (ieee ISPA)

作者： Huang, Xiao Jiang, Yu Fan, Hao Tang, Huayun Wang, Yiping Jin, Jin Wan, Hai Zhao, Xibin Tsinghua Univ Beijing Peoples R China ChinaBond Finance & Informat Technol Co Ltd Beijing Peoples R China Maple Growth Res Club Inst Toronto ON Canada

ISBN: (纸本)9781665435741

Data Stream processing (DSP) applications, which generate real-time analytics on continuous data flows, have become prevalent recently. For the deployment of DSP applications, task placement is an important and essential part. As determining the optimal task placement is an NP-hard problem, several efficient heuristics have been designed and Deep Reinforcement Learning (DRL) was used to train the scheduling agent. Current DRL-based approach assumes all resources including CPU, memory and networking are homogeneous. However, the available computation and network resources are heterogeneous in many scenarios. To deal with it, we devise a general DRL-based resource-aware framework, which models resources using graph embedding and attention mechanism to predict the placement. Furthermore, in order to accelerate the training process and improve the throughput, we propose an efficient throughput estimation tool, which can estimate the throughput with high accuracy. We integrated our scheduling heuristic framework into Apache Flink and conducted comprehensive testings using multiple synthetic and real DSP applications. The experimental results show that our framework increases the throughput by 64%, 42%, 29% on average respectively compared with three state-of-the-art strategies.

关键词： Data stream processing Task placement Throughput Deep reinforcement learning Heterogeneous resources

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How well do CPU, GPU and Hybrid Graph processing Frameworks Perform? 32

How well do CPU, GPU and Hybrid Graph Processing Frameworks ...

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27th international Heterogeneity in Computing Workshop in conjunction with 32nd ieee international parallel and distributed processing symposium (IPDPS)

作者： Aasawat, Tanuj Kr Reza, Tahsin Ripeanu, Matei Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781538655559

The importance of high-performance graph processing to solve big data problems targeting high-impact applications is greater than ever before. Recent graph processing frameworks target different hardware platforms (e.g., shared memory systems, accelerators such as GPUs, and distributed systems) and differ with respect to the programming model they adopt (e.g., based on linear algebra formulations of graph algorithms or enabling direct access to the graph structure). To better understand the impact of these choices, this paper, presents a comparative study of five state-of-the-art graph processing frameworks: two CPU-only frameworks - GraphMat and Galois, two GPU-based frameworks - Nvgraph and Gunrock;and Totem, a hybrid (CPU+GPU) framework. We use three popular graph algorithms (PageRank, Single Source Shortest Path, and Breadth-First Search), and massive scale graphs with up to billions of edges. Our evaluation focuses on three performance metrics: (i) execution time, (ii) scalability and (iii) energy consumption.

关键词： Graph processing CPU GPU Hybrid Systems Performance Evaluation PageRank SSSP BFS

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Balanced Coloring for parallel Computing applications 29

Balanced Coloring for Parallel Computing Applications

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29th ieee international parallel and distributed processing symposium (IPDPS)

作者： Lu, Hao Halappanavar, Mahantesh Chavarria-Miranda, Daniel Gebremedhin, Assefaw Kalyanaraman, Ananth Washington State Univ Pullman WA 99164 USA Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781479986484

Graph coloring is used to identify subsets of independent tasks in parallel scientific computing applications. Traditional coloring heuristics aim to reduce the number of colors used as that number also corresponds to the number of parallel steps in the application. However, if the color classes produced have a skew in their sizes, utilization of hardware resources becomes inefficient, especially for the smaller color classes. Equitable coloring is a theoretical formulation of coloring that guarantees a perfect balance among color classes, and its practical relaxation is referred to as balanced coloring. In this paper, we revisit the problem of balanced coloring in the context of parallel computing. The goal is to achieve a balanced coloring of an input graph without increasing the number of colors that an algorithm oblivious to balance would have used. We propose and study multiple heuristics that aim to achieve such a balanced coloring, present parallelization approaches for multi-core and manycore architectures, and cross-evaluate their effectiveness with respect to the quality of balance achieved and performance. Furthermore, we study the impact of the proposed balanced coloring heuristics on a concrete application - viz. parallel community detection, which is an example of an irregular application. The thorough treatment of balanced coloring presented in this paper from algorithms to application is expected to serve as a valuable resource to parallel application developers who seek to improve parallel performance of their applications using coloring.

关键词： Balanced coloring Tilera manycore architecture community detection graph algorithms

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A Fast Repair Code Based on Regular Graphs for distributed Storage Systems

A Fast Repair Code Based on Regular Graphs for Distributed S...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Wang, Yan Wang, Xin Fudan Univ Sch Comp Sci Shanghai Key Lab Intelligent Informat Proc Shanghai 200433 Peoples R China

ISBN: (纸本)9780769546766

distributed storage systems (DSS) play an important role in data storage applications, since they provide high reliability for huge data storage requirement. As node failures are frequent in a large distributed storage system, the performance of repairing node failure causes many researchers' interests. In this paper, we propose a distributed storage code to minimize the coding complexity during the repairing process, at a cost of inducing larger redundancy. Our code construction is based on regular graphs and exploits simple look-up repair. We analyze the performance of the proposed code, and compare them with existing distributed storage codes. Analytical results show that the proposed code outperforms the others in terms of low repair complexity and disk I/O overhead.

关键词： distributed storage systems Erasure codes Regenerating codes

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DAG Scheduling Considering parallel Execution for High-Load processing on Clustered Many-core Processors 26

DAG Scheduling Considering Parallel Execution for High-Load ...

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26th ieee/ACM international symposium on distributed Simulation and Real Time applications (DS-RT)

作者： Okamura, Ryo Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan

ISBN: (数字)9781665497992

ISBN: (纸本)9781665497992

In recent years, high computational power has been required for computer platforms to support complex systems such as self-driving systems. Clustered many-core processors and directed acyclic graphs (DAGs), which can represent dependencies and parallelism of task processing, have attracted much attention as solutions to this problem. Previous studies on scheduling DAGs on multi-core processors have attempted to reduce the makespan (i.e., time it takes for a task to complete) by increasing the number of processes that can be executed in parallel. However, in self-driving systems, such as those utilizing clustered many-core processors, it is impossible to sufficiently increase the utilization of processor cores due to high-load processing. In this paper, a scheduling method is proposed to improve the utilization of processor cores by parallel executing high-load processes in parallel across multiple cores. The proposed method can reduce the makespan of DAGs performing high-load processing on clustered many-core processors.

关键词： clustered many-core processors DAG work-conserving schedule list scheduling

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OLAP Aggregation Based on Dimension-oriented Storage

OLAP Aggregation Based on Dimension-oriented Storage

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Zhao Jing-hua Song Ai-mei Song Ai-bo Shandong Univ Sci & Technol Coll Informat Sci & Engn Qingdao Peoples R China Southeast Univ Sch Comp Sci & Engn Nanjing Peoples R China

ISBN: (纸本)9780769546766

OLAP (online analytical processing) applications are based on a variety of aggregate queries on large-scale data. As aggregation is always performed on columns, traditional row-oriented storage, in which all the columns of a data row are stored together, has seriously restricted its performance. This paper proposes a dimension-oriented storage model based on HBase, and a new parallel aggregation technique, which accomplishes aggregation operations with parallel MapReduce jobs. Finally, compared with Hive on standard TPC-H data set, our technique is demonstrated to improve performance of core aggregate operations significantly.

关键词： OLAP (online analytical processing) dimension-oriented storage aggregation MapReduce

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A Load-Balanced parallel and distributed Sorting Algorithm Implemented with PGX.D 31

A Load-Balanced Parallel and Distributed Sorting Algorithm I...

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31st ieee international parallel and distributed processing symposium Workshops (IPDPS)

作者： Khatami, Zahra Hong, Sungpack Lee, Jinsoo Depner, Siegfried Chafi, Hassan Ramanujam, J. Kaiser, Hartmut Oracle Labs Belmont CA 94002 USA Louisiana State Univ Ctr Computat & Technol Baton Rouge LA 70803 USA

ISBN: (纸本)9780769561493

Sorting has been one of the most challenging studied problems in different scientific researches. Although many techniques and algorithms have been proposed on the theory of having efficient parallel sorting implementation, however achieving desired performance on different types of the architectures with large number of processors is still a challenging issue. Maximizing parallelism level in applications can be achieved by minimizing overheads due to load imbalance and waiting time due to memory latencies. In this paper, we present a distributed sorting algorithm implemented in PGX.D, a fast distributed graph processing system, which outperforms the Spark's distributed sorting implementation by around 2x-3x by hiding communication latencies and minimizing unnecessary overheads. Furthermore, it shows that the proposed PGX.D sorting method handles dataset containing many duplicated data entries efficiently and always results in keeping balanced workloads for different input data distribution types.

关键词： distributed sorting method PGX.D distributed graph framework Graph

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A Reconfigurable High Performance ASIP Engine for Image Signal processing

A Reconfigurable High Performance ASIP Engine for Image Sign...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Liao, Hsuanchun Asri, Mochamad Isshiki, Tsuyoshi Li, Dongju Kunieda, Hiroaki Tokyo Inst Technol Dept Commun & Integrated Syst Tokyo 152 Japan

ISBN: (纸本)9780769546766

Emerging digital television applications and the conventional MPSoC architectures encounter drastically increasing performance and flexibility requirement. To display high quality of images on the display devices, several image processing has to be performed. However, these algorithms are nonstandard and change case by case. It is difficult to achieve real time processing by using general purpose processor or DSP. In this paper, we present a reconfigurable Application Specific Instruction-set Processor (ASIP) which can perform several image processing algorithms by using the same datapath. It can complete several 1D filtering processing within 8 cycle/pixel;performing 16 times higher performance compare to conventional RISC processor. the performance of this ASIP can achieve the requirement of FullHD(1920x1080) application.

关键词： ASIP Image processing

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