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检索条件"任意字段=IEEE International Symposium on Parallel and Distributed Processing with Applications"

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APC-SCA: A Fully-parallel Annealing Algorithm with Autonomous Pinning Effect Control 36

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomou...

引用

36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Okonogi, Daiki Jimbo, Satoru Ando, Kota Thiem Van Chu Yu, Jaehoon Motomura, Masato Kawamura, Kazushi Tokyo Inst Technol AI Comp Res Unit Yokohama Kanagawa Japan

ISBN: (纸本)9781665497473

Annealing computation has recently attracted attention as it can efficiently solve various combinatorial optimization problems using an Ising model. Stochastic cellular automata annealing (SCA) is a promising algorithm that can realize fast spin-update by utilizing its parallel computing capability. However, in SCA, preparing an appropriate control of the pinning parameter is a hard task, which degrades its usability. This paper proposes a novel approach called APC-SCA (Autonomous Pinning effect Control SCA) where the spin pinning parameter can be controlled autonomously by observing individual spin flips. The evaluation results using max-cut and N-queen problems demonstrate that the proposed approach can obtain better solutions than the conventional approach with a grid search of optimal pinning parameter control.

关键词： combinatorial optimization cellular automata stochastic algorithm parallel annealing Ising model

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Optimization of Compiler-Generated OpenCL CNN Kernels and Runtime for FPGAs 36

Optimization of Compiler-Generated OpenCL CNN Kernels and Ru...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Chung, Seung-Hun Abdelrahman, Tarek S. Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781665497473

We translate frozen CNN models into OpenCL kernels with the TVM compiler and then use Intel's OpenCL SDK to compile to an FPGA bitstream. We improve the performance of the generated base hardware with optimizations that increase parallelism, reduce memory access latency, and save on-chip resources. We automate these optimizations in TVM and evaluate them by generating accelerators for LeNet-5, MobileNetVl and ResNet-34 on an Intel Stratix 10SX. The optimizations improve the performance of the generated accelerators by up to 846 x over the base ones. The optimized accelerators are up to 4.57 x faster than TensorFlow on CPU, 3.83x faster than single-threaded TVM and are only 0.34x slower than TVM with 56 threads. Our optimized kernels also outperform ones generated by similar approaches that use high-level synthesis, but they underperform ones that utilize hand-optimized designs. Thus, our approach is most useful in environments that benefit from increased performance and fast prototyping, realizing the benefits of FPGAs without hardware design expertise.

关键词： distributed processing Runtime Conferences parallel processing Hardware System-on-chip Kernel

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parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System 24

Parallel and Heterogeneous Timing Analysis: Partition, Algor...

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33rd ACM international symposium on Physical Design (ISPD)

作者： Huang, Tsung-Wei Zhang, Boyang Lin, Dian-Lun Chiu, Cheng-Hsiang Univ Wisconsin Madison Dept Elect & Comp Engn Madison WI 53706 USA

ISBN: (纸本)9798400704178

Static timing analysis (STA) is an integral part in the overall design flow because it verifies the expected timing behaviors of a circuit. However, as the circuit complexity continues to enlarge, there is an increasing need for enhancing the performance of existing STA algorithms using emerging heterogeneous parallelism that comprises manycore central processing units (CPUs) and graphics processing units (GPUs). In this paper, we introduce several state-of-the-art STA techniques, including task-based parallelism, task graph partition, and GPU kernel algorithms, all of which have brought significant performance benefits to STA applications. Motivated by these successful results, we will introduce a task-parallel programming system to generalize our solutions to benefit broader scientific computing applications.

关键词： Static timing analysis high-performance computing task parallelism heterogeneous parallelism

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Practical Tie-Breaking for parallel/distributed Simulations 27

Practical Tie-Breaking for Parallel/Distributed Simulations

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27th ieee/ACM international symposium on distributed Simulation and Real Time applications, DS-RT 2023

作者： Piccione, Andrea Pellegrini, Alessandro Huawei Munich Research Center Tor Vergata University of Rome Italy

ISBN: (纸本)9798350337846

In this paper, we discuss a tie-breaking strategy based on a bitwise comparison of event payload that allows parallel and distributed discrete-event simulations to observe a deterministic order in the execution of events, even in the presence of event ties. This approach provides practical usability whenever model-assisted tie-breaking is unavailable, thus ensuring that multiple simulation executions provide deterministic behaviour and repeatable results. Moreover, it ensures that the selected order of events is also consistent with sequential executions. We discuss the theory behind this strategy and experimentally show that the performance drop is imputable to event queue management when relying on tie-breaking strategies like the ones discussed in this work. © 2023 ieee.

关键词： Discrete event simulation

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APPFIS: An Advanced parallel Programming Framework for Iterative Stencil Based Scientific applications in HPC Environments 21

APPFIS: An Advanced Parallel Programming Framework for Itera...

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21st ieee international symposium on parallel and distributed Computing (ISPDC)

作者： Sharif, Md Bulbul Ghafoor, Sheikh Tennessee Technol Univ Dept Comp Sci Cookeville TN 38505 USA

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488020

Developing performant parallel applications for the distributed environment is challenging and requires expertise in both the HPC system and the application domain. We have developed a C++-based framework called APPFIS that hides the system complexities by providing an easy-to-use interface for developing performance portable structured grid-based stencil applications. APPFIS's user interface is hardware agnostic and provides partitioning, code optimization, and automatic communication for stencil applications in distributed HPC environment. In addition, it offers straightforward APIs for utilizing multiple GPU accelerators, shared memory, and node-level parallelizations with automatic optimization for computation and communication overlapping. We have tested the functionality and performance of APPFIS using several applications on three platforms (Stampede2 at Texas Advanced Computing Center, Bridges-2 at Pittsburgh Supercomputing Center, and Summit Supercomputer at Oak Ridge National Laboratory). Experimental results show comparable performance to hand-tuned code with an excellent strong and weak scalability up to 4096 CPUs and 384 GPUs.

关键词： GPU MPI parallel Programming Framework Structured Grid Iterative Stencil Summit Stampede2 Bridges-2

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parallel Vertex Cover Algorithms on GPUs 36

Parallel Vertex Cover Algorithms on GPUs

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Yamout, Peter Barada, Karim Jaljuli, Adnan Mouawad, Amer E. El Hajj, Izzat Amer Univ Beirut Beirut Lebanon

ISBN: (纸本)9781665481069

Finding small vertex covers in a graph has applications in numerous domains such as scheduling, computational biology, telecommunication networks, artificial intelligence, social science, and many more. Two common formulations of the problem include: Minimum Vertex Cover (MVC), which finds the smallest vertex cover in a graph, and Parameterized Vertex Cover (PVC), which finds a vertex cover whose size is less than or equal to some parameter k. Algorithms for both formulations involve traversing a search tree, which grows exponentially with the size of the graph or the value of k. parallelizing the traversal of the vertex cover search tree on GPUs is challenging for multiple reasons. First, the search tree is a narrow binary tree which makes it difficult to extract enough sub-trees to process in parallel to fully utilize the GPU's massively parallel execution resources. Second, the search tree is highly imbalanced which makes load balancing across a massive number of parallel GPU workers especially challenging. Third, keeping around all the intermediate state needed to traverse many sub-trees in parallel puts high pressure on the GPU's memory resources and may act as a limiting factor to parallelism. To address these challenges, we propose an approach to traverse the vertex cover search tree in parallel using GPUs while handling dynamic load balancing. Each thread block traverses a different sub-tree using a local stack, however, we use a global worklist to balance the load to ensure that all blocks remain busy. Blocks contribute branches of their sub-trees to the global worklist on an as-needed basis, while blocks that finish their subtrees pick up new ones from the global worklist. We use degree arrays to represent intermediate graphs so that the representation is compact in memory to avoid limiting parallelism, but selfcontained which is necessary for the load balancing process. Our evaluation shows that compared to approaches used in prior work, our hybrid approa

关键词： Limiting Processor scheduling Instruction sets Heuristic algorithms Social sciences Memory management Graphics processing units

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HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA processing 36

HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA PROCESSING

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Adavally, Shashank Weaver, Alex Vasireddy, Pranathi Kavi, Krishna Mehta, Gayatri Gulur, Nagendra Univ North Texas Denton TX 76203 USA

ISBN: (纸本)9781665497473

Sparse matrices are very common types of information used in scientific and machine learning applications including deep neural networks. Sparse data representations lead to storage efficiencies by avoiding storing zero values. However, sparse representations incur metadata computational overheads - software first needs to find row/column locations of non-zero values before performing necessary computations. Such metadata accesses involve indirect memory accesses (of the form a[b[i] ] where a[.] and b[.] are large arrays) and they are cache and prefetch-unfriendly, resulting in frequent load stalls. In this paper, we will explore a dedicated hardware for a memory-side accelerator called Hardware Helper Thread (HHT) that performs all the necessary index computations to fetch only the nonzero elements from sparse matrix and sparse vector and supply those values to the primary core, creating heterogeneity within a single CPU core. We show both performance gains and energy savings of HHT for sparse matrix-dense vector multiplication (SpMV) and sparse matrixsparse vector multiplication (SpMSpV). The ASIC HHT shows average performance gains ranging between 1.7 and 3.5 depending on the sparsity levels, vector-widths used by RISCV vector instructions and if the Vector (in Matrix-Vector multiplication) is sparse or dense. We also show energy savings of 19% on average when ASIC HHT is used compared to baseline (for SpMV), and the HHT requires 38.9% of a RISCV core area.

关键词： Sparse matrices DNN Hardware Accelerators RISCV

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Sequre: a high-performance framework for rapid development of secure bioinformatics pipelines 36

Sequre: a high-performance framework for rapid development o...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Smajlovic, Haris Shajii, Ariya Berger, Bonnie Cho, Hyunghoon Numanagic, Ibrahim Univ Victoria Victoria BC Canada MIT Cambridge MA 02139 USA Broad Inst MIT & Harvard Cambridge MA 02142 USA

ISBN: (纸本)9781665497473

Genomic data leaks are irreversible. Leaked DNA cannot be changed, stays disclosed indefinitely, and affects the owner's family members as well. The recent large-scale genomic data collections [1], [2] render the traditional privacy protection mechanisms, like the Health Insurance Portability and Accountability Act (HIPAA), inadequate for protection against the novel security attacks [3]. On the other hand, data access restrictions hinder important clinical research that requires large datasets to operate [4]. These concerns can be naturally addressed by the employment of privacy-enhancing technologies, such as a secure multiparty computation (MPC) [5]–[10]. Secure MPC enables computation on data without disclosing the data itself by dividing the data and computation between multiple computing parties in a distributed manner to prevent individual computing parties from accessing raw data. MPC systems are being increasingly adopted in fields that operate on sensitive datasets [11]–[13], such as computational genomics and biomedical research [14]–[22].

关键词： distributed processing Data privacy Pipelines Employment distributed databases Genomics Insurance

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parallel and Batch Multiple Replica Auditing Protocol for Edge Computing 21

Parallel and Batch Multiple Replica Auditing Protocol for Ed...

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21st ieee international symposium on parallel and distributed processing with applications, 13th ieee international Conference on Big Data and Cloud Computing, 16th ieee international Conference on Social Computing and Networking and 13th international Conference on Sustainable Computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Li, Yi Zheng, Wenying Pandi, Vijayakumar Bhuiyan, Md Zakirul Alam Thamilarasi, C. Nanjing University of Information Science and Technology School of Computer Science Nanjing China Zhejiang Sci-Tech University School of Computer Science and Technology Hangzhou China University College of Engineering Tindivanam Anna University Chennai Department of Computer Science and Engineering Melpakkam India Fordham University Department of Computer and Information Sciences BronxNY United States P.S.V College of Enfgineering and Technoogy Department of Electronics and Communication Engineering Krishnagiri India

ISBN: (纸本)9798350329223

The edge computing architecture exposes data transmission and storage to unauthorized access, compromising data integrity. Users typically employ multiple data backups to ensure data reliability and availability, enhancing data redundancy and recovery capabilities. Nevertheless, verifying the integrity of multiple backup data under edge computing entails computational and communication overhead. In response, we present a parallel and batch multiple replica auditing protocol tailored for edge computing. Contributions include an efficient multiple replica construction method based on RSA, minimizing computational overhead, and a parallel data integrity verification approach that reduces communication overhead. A prototype implementation is evaluated in a real edge computing environment and compared to existing multiple replica auditing approaches. © 2023 ieee.

关键词： Edge computing

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Etudes for parallel Programmers 33

Etudes for Parallel Programmers

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33rd Euromicro international Conference on parallel, distributed, and Network-Based processing, PDP 2025

作者： Marzolla, Moreno Center for Inter-Department Industrial Research ICT Bologna Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524937

Mini-applications are widely used in parallel computing for testing and benchmarking purposes. However, many existing mini-applications are not suitable for teaching, since they require advanced knowledge of algebra, numerical analysis or physics to be fully understood, which might be beyond the reach of beginners. In this paper we describe a set of programming assignments, called parallel etudes, that have been used in the last years for teaching High Performance Computing at the undergraduate level. These applications are self-contained, self-documenting, and short. They are drawn from more familiar domains such as 3D rendering, simulation, image processing and simple physics models, to be more accessible to students without a strong mathematical background. The mini-applications target shared-memory, distributed-memory and GPU programming. The analysis of the students' feedback and final grades provides indirect support for the effectiveness of the etudes. © 2025 ieee.

关键词： parallel programming

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