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30th ieee international parallel and distributed processing symposium (IPDPS)

作者： Goodarzi, Bahareh Burtscher, Martin Goswami, Dhrubajyoti Concordia Univ Dept Comp Sci Montreal PQ Canada Texas State Univ Dept Comp Sci San Marcos TX USA

ISBN: (纸本)9781509036820

Graph partitioning has important applications in multiple areas of computing, including scheduling, social networks, and parallel processing. In recent years, GPUs have proven successful at accelerating several graph algorithms. However, the irregular nature of the real-world graphs poses a problem for GPUs, which favor regularity. In this paper, we discuss the design and implementation of a parallel multilevel graph partitioner for a CPU-GPU system. The partitioner aims to overcome some of the challenges arising due to memory constraints on GPUs and maximizes the utilization of GPU threads through suitable load-balancing schemes. We present a lock-free shared-memory scheme since fine-grained synchronization among thousands of threads imposes too high a performance overhead. The partitioner, implemented in CUDA, outperforms serial Metis and parallel MPI-based ParMetis. It performs similar to the shared-memory CPU-based parallel graph partitioner mt-metis.

关键词： graph partitioning coarsening un-coarsening refinement GPU

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A distributed Filesystem Framework for Transparent Accessing Heterogeneous Storage Services

A Distributed Filesystem Framework for Transparent Accessing...

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23rd ieee international parallel and distributed processing symposium

作者： Lu, Yutong Mao, Huajian Shen, Jie Natl Univ Def & Technol Changsha Hunan Peoples R China

ISBN: (纸本)9781424437511

This paper introduces an extensible distributed file system framework, YaFS, using heterogeneous online storage services as its back-ends. It provides a configurable solution for simplifying the usage of multiple storage resources and accessing data ubiquitously and safely. YaFS is POSIX compliant, so that it could support most of the existing applications seamlessly. An of line mode is used to cope with the challenged unreliable network environment. We implement a storage abstraction layer and a plug-in mechanism for uniformly accessing different storage services transparently, and it makes the system expanded easily. YaFS could effectively support for storing large object to size limited services and achieving high aggregate bandwidth by striping data on multiple servers with bandwidth-saving method. The evaluation on a prototype implementation with email services as its storage back-end shows that the performance and usability of the framework is viable.

关键词： Abstracting

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ECCH: Erasure Coded Consistent Hashing for distributed Storage Systems 19

ECCH: Erasure Coded Consistent Hashing for Distributed Stora...

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19th ieee international symposium on parallel and distributed processing with applications (ieee ISPA)

作者： Xiong, Yinglong Zhou, Jiang Su, Lin Wang, Weiping Chen, Yong Chinese Acad Sci Inst Informat Engn Beijing Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing Peoples R China Texas Tech Univ Dept Comp Sci Lubbock TX 79409 USA

ISBN: (纸本)9781665435741

In this paper, we propose ECCH, an Erasure Coded Consistent Hashing scheme to make better data placement in distributed storage systems. It combines the inherent advantages of consistent hashing together with the storage-efficiency of erasure coding technology. Specifically, ECCH divides data block stream of files into groups according to block IDs. In each group, it encoded data blocks with additional parity blocks by erasure coding. All encoded blocks in the same group are stored on different nodes with consistent hashing distribution. For node failure or data loss, ECCH locates required data through the ID of missing block in a same group for fast recovery. To deal with node changes, ECCH introduces a design of multi-version hash rings to manage data layout. It can prevent the impact of data migration on erasure coding, while achieving data balance with little data movement. We have implemented ECCH on the Sheepdog, a distributed object-based storage system. Evaluation results show that ECCH can greatly improve the space utilization of hashing-based storage systems, while achieving efficient fault tolerance.

关键词： Consistent hashing erasure coding replication data distribution fault tolerance

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Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA 34

Performance Evaluation of Pipelined Communication Combined w...

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34th ieee international parallel and distributed processing symposium (IPDPS)

作者： Fujita, Norihisa Kobayashi, Ryohei Yamaguchi, Yoshiki Ueno, Tomohiro Sano, Kentaro Boku, Taisuke Univ Tsukuba Ctr Computat Sci Tsukuba Ibaraki Japan Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki Japan RIKEN Ctr Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9781728174457

In recent years, much High Performance Computing (HPC) researchers attract to utilize Field Programmable Gate Arrays (FPGAs) for HPC applications. We can use FPGAs for communication as well as computation thanks to FPGA's I/O capabilities. HPC scientists cannot utilize FPGAs for their applications because of the difficulty of the FPGA development, however High Level Synthesis (HLS) allows them to use with appropriate costs. In this study, we propose a Communication Integrated Reconfigurable CompUting System (CIRCUS) to enable us to utilize high-speed interconnection of FPGAS from OpenCL. CIRCUS makes a fused single pipeline combining the computation and the communication, which hides the communication latency by completely overlapping them. In this paper, we present the detail of the implementation and the evaluation result using two benchmarks: pingpong benchmark and allreduce benchmark.

关键词： FPGA OpenCL HLS parallel computing inter-connection

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Fault Modeling of Extreme Scale applications using Machine Learning 30

Fault Modeling of Extreme Scale Applications using Machine L...

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30th ieee international parallel and distributed processing symposium (IPDPS)

作者： Vishnu, Abhinav van Dam, Hubertus Tallent, Nathan R. Kerbyson, Darren J. Hoisie, Adolfy Pacific Northwest Natl Lab Richland WA 99352 USA Brookhaven Natl Lab Upton NY 11973 USA

ISBN: (纸本)9781509021406

Faults are commonplace in large scale systems. These systems experience a variety of faults such as transient, permanent and intermittent. Multi-bit faults are typically not corrected by the hardware resulting in an error. This paper attempts to answer an important question: Given a multi-bit fault in main memory, will it result in an application error and hence a recovery algorithm should be invoked - or can it be safely ignored? We propose an application fault modeling methodology to answer this question. Given a fault signature (a set of attributes comprising of system and application state), we use machine learning to create a model which predicts whether a multi-bit permanent/transient main memory fault will likely result in error. We present the design elements such as the fault injection methodology for covering important data structures, the application and system attributes which should be used for learning the model, the supervised learning algorithms (and potentially ensembles), and important metrics. We use three applications - NWChem, LULESH and SVM - as examples for demonstrating the effectiveness of the proposed fault modeling methodology.

关键词： applications Exascale Fault Machine Learning Modeling

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Near-optimal all-to-all broadcast in multidimensional all-port meshes and tori

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ieee TRANSACTIONS ON parallel AND distributed SYSTEMS 2002年第2期13卷 128-141页

作者： Yang, YY Wang, JC SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA DataTreasury Corp Melville NY 11747 USA

All-to-all communication is one of the most dense collective communication patterns and occurs in many important applications in parallel and distributed computing. In this paper, we present a new all-to-all broadcast algorithm in multidimensional all-port mesh and torus networks. We propose a broadcast pattern which ensures a balanced traffic load in all dimensions in the network so that the all-to-all broadcast algorithm can achieve a very tight near-optimal transmission time. The algorithm also takes advantage of overlapping of message switching time and transmission time, and the total communication delay asymptotically matches the lower bound of all-to-all broadcast. Finally, the algorithm is conceptually simple and symmetrical for every message and every node so that it can be easily implemented in hardware and achieves the near-optimum in practice.

关键词： parallel computing collective communication all-to-all communication all-to-all broadcast gossip broadcast tree routing interprocessor communication mesh torus

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A Load-Balanced parallel and distributed Sorting Algorithm Implemented with PGX.D 31

A Load-Balanced Parallel and Distributed Sorting Algorithm I...

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31st ieee international parallel and distributed processing symposium Workshops (IPDPS)

作者： Khatami, Zahra Hong, Sungpack Lee, Jinsoo Depner, Siegfried Chafi, Hassan Ramanujam, J. Kaiser, Hartmut Oracle Labs Belmont CA 94002 USA Louisiana State Univ Ctr Computat & Technol Baton Rouge LA 70803 USA

ISBN: (纸本)9780769561493

Sorting has been one of the most challenging studied problems in different scientific researches. Although many techniques and algorithms have been proposed on the theory of having efficient parallel sorting implementation, however achieving desired performance on different types of the architectures with large number of processors is still a challenging issue. Maximizing parallelism level in applications can be achieved by minimizing overheads due to load imbalance and waiting time due to memory latencies. In this paper, we present a distributed sorting algorithm implemented in PGX.D, a fast distributed graph processing system, which outperforms the Spark's distributed sorting implementation by around 2x-3x by hiding communication latencies and minimizing unnecessary overheads. Furthermore, it shows that the proposed PGX.D sorting method handles dataset containing many duplicated data entries efficiently and always results in keeping balanced workloads for different input data distribution types.

关键词： distributed sorting method PGX.D distributed graph framework Graph

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A Novel N-Retry Transactional Memory Model for Multi-thread Programming 15

A Novel <i>N</i>-Retry Transactional Memory Model for Multi-...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Lu, Kun Yan, Changhao Zhou, Hai Zhou, Dian Zeng, Xuan Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL 60208 USA Univ Texas Dallas Dept Elect Engn Richardson TX 75083 USA

ISBN: (纸本)9781538637906

Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel programming paradigm. Transaction memory maintains Atomicity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform.

关键词： multi-thread programming transaction memory intel Transactional Synchronization Extensions (TSX) transactional locking 2

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Balanced Coloring for parallel Computing applications 29

Balanced Coloring for Parallel Computing Applications

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29th ieee international parallel and distributed processing symposium (IPDPS)

作者： Lu, Hao Halappanavar, Mahantesh Chavarria-Miranda, Daniel Gebremedhin, Assefaw Kalyanaraman, Ananth Washington State Univ Pullman WA 99164 USA Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781479986484

Graph coloring is used to identify subsets of independent tasks in parallel scientific computing applications. Traditional coloring heuristics aim to reduce the number of colors used as that number also corresponds to the number of parallel steps in the application. However, if the color classes produced have a skew in their sizes, utilization of hardware resources becomes inefficient, especially for the smaller color classes. Equitable coloring is a theoretical formulation of coloring that guarantees a perfect balance among color classes, and its practical relaxation is referred to as balanced coloring. In this paper, we revisit the problem of balanced coloring in the context of parallel computing. The goal is to achieve a balanced coloring of an input graph without increasing the number of colors that an algorithm oblivious to balance would have used. We propose and study multiple heuristics that aim to achieve such a balanced coloring, present parallelization approaches for multi-core and manycore architectures, and cross-evaluate their effectiveness with respect to the quality of balance achieved and performance. Furthermore, we study the impact of the proposed balanced coloring heuristics on a concrete application - viz. parallel community detection, which is an example of an irregular application. The thorough treatment of balanced coloring presented in this paper from algorithms to application is expected to serve as a valuable resource to parallel application developers who seek to improve parallel performance of their applications using coloring.

关键词： Balanced coloring Tilera manycore architecture community detection graph algorithms

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Formal Modeling and Verification of Scalable Process-aware distributed IoT applications 17

Formal Modeling and Verification of Scalable Process-aware D...

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ieee Int Conf on parallel and distributed processing with applications, Big Data and Cloud Computing, Sustainable Computing and Communications, Social Computing and Networking (ISPA/BDCloud/SocialCom/SustainCom)

作者： Jain, Rakesh Klai, Kais Tata, Samir IBM Almaden Res Ctr San Jose CA 95120 USA Univ Paris 13 CNRS UMR 7030 LIPN Villetaneuse France LG Silicon Valley Lab Santa Clara CA USA

ISBN: (纸本)9781728143286

IoT applications are distributed over multiple IoT computing and communicating resources across the network including but not limited to small devices, machines, and public clouds. These IoT applications are composed of clearly separated and communicating fragments that can be modeled as large scale business processes. Process fragments can be unique, deployed in one location such as the cloud. They can also be replicated over multiple locations, such as different rooms in a smart building. Formal modeling and verification of such business processes composed of replicated fragments is a challenging task. In this paper we present a formal approach of modeling and verification of IoT applications that takes into account the scalability and repeatability properties of process-aware IoT applications. We propose a concise way of modeling and a general framework for the verification that simplifies the burden of IoT application modeling and deployment.

关键词： Internet of Things Colored Petri Nets Business Process distributed Deployment Node-RED Formal Method

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