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On the Vulnerabilities of Landmark-based Data Location Approaches: Threats, Solutions, and Challenges 15

On the Vulnerabilities of Landmark-based Data Location Appro...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Irain, Malik Jorda, Jacques Mammeri, Zoubir Univ Toulouse IRIT Toulouse France

ISBN: (纸本)9781538637906

Nowadays, many companies, administrations, and individuals are outsourcing the storage of their data to large-scale Cloud Service Providers (CSPs). Unfortunately, the modern cloud infrastructure virtualization results in the difficulty or the impossibility for data owners to know the location where their data are stored. Data location verification is required due to legal, privacy, and performance constraints. Recently "Where are my data located in the Cloud?" has become a challenge and solutions have been proposed to verify data location. Even in case of the establishment of a strong Service-Level Agreement, which includes an initial guarantee regarding data location, the CSP may then move the data in another location, like another country, in order to cut the costs or for any other reasons. This paper considers landmark-based verification approaches, which are flexible and low cost compared to other location verification approaches. The objective is the identification of vulnerabilities relating to the main proposed landmark-based location verification approaches when malicious CSPs are involved and the proposal of some countermeasures against CSP's attacks. We present, to the best of our knowledge, the most comprehensive literature survey on vulnerabilities of landmark-based data location approaches.

关键词： Cloud computing Data location verification Landmark-based approaches Threats

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Automated Performance Modeling Based on Runtime Feature Detection and Machine Learning 15

Automated Performance Modeling Based on Runtime Feature Dete...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Sun, Jingwei Zhan, Shiyan Sun, Guagnzhong Chen, Yong Univ Sci & Technol China Sch Comp Sci & Technol Hefei Anhui Peoples R China Texas Tech Univ Dept Comp Sci Lubbock TX 79409 USA

ISBN: (纸本)9781538637906

Automated performance modeling and performance prediction of parallel programs are highly valuable in many use cases, such as in guiding task management and job scheduling, offering insights of application behaviors, assisting resource requirement estimation, etc. The performance of parallel programs is affected by numerous factors, including but not limited to hardware, system software, applications, algorithms, and input parameters, thus an accurate performance prediction is often a challenging and daunting task. In this study, we focus on automatically predicting the execution time of parallel programs (more specifically, MPI programs) with different inputs, at different scale, and without domain knowledge. We model the correlation between the execution time and domain-independent runtime features. These features include values of variables, counters of branches, loops, and MPI communications. Through automatically instrumenting an MPI program, each execution of the program will output a feature vector and its corresponding execution time. After collecting data from executions with different inputs, a random forest machine learning approach is used to build an empirical performance model, which can predict the execution time of the program with a new input. Our experiments and analyses of three parallel programs, Graph500, GalaxSee and SMG2000, on three different systems show that our method performs well, with less than 20% error in predictions on average.

关键词： Predictive models Analytical models Instruments Computational modeling Feature extraction Data models Runtime

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Using the Translation Lookaside Buffer to Map Threads in parallel applications Based on Shared Memory

Using the Translation Lookaside Buffer to Map Threads in Par...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Cruz, Eduardo H. M. Diener, Matthias Navaux, Philippe O. A. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9780769546759

The communication latency between the cores in multiprocessor architectures differs depending on the memory hierarchy and the interconnections. With the increase of the number of cores per chip and the number of threads per core, this difference between the communication latencies is increasing. Therefore, it is important to map the threads of parallel applications taking into account the communication between them. In parallel applications based on the shared memory paradigm, the communication is implicit and occurs through accesses to shared variables. For this reason, it is difficult to detect the communication pattern between the threads. Traditional approaches use simulation to monitor the memory accesses performed by the application, requiring modifications to the source code and drastically increasing the overhead. In this paper, we introduce a new light-weight mechanism to detect the communication pattern of threads using the Translation Lookaside Buffer (TLB). Our mechanism relies entirely on hardware features, which makes the thread mapping transparent to the programmer and allows it to be performed dynamically by the operating system. Moreover, no time consuming task, such as simulation, is required. We evaluated our mechanism with the NAS parallel Benchmarks (NPB) and achieved an accurate representation of the communication patterns. Using the detected communication patterns, we generated thread mappings using a heuristic method based on the Edmonds graph matching algorithm. Running the applications with these mappings resulted in performance improvements of up to 15.3%, reducing the number of cache misses by up to 31.1%.

关键词： Thread mapping parallel applications Shared memory TLB Translation Lookaside Buffer Interconnections Cache Misses

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distributed V2V Computing Offloading Method Based on Delay and Fairness Awareness 19

Distributed V2V Computing Offloading Method Based on Delay a...

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19th ieee international symposium on parallel and distributed processing with applications (ieee ISPA)

作者： Yang, Guoliang Xiong, Mengqi Feng, Guangsheng Liu, Yuzheng Huang, Yun Harbin Engn Univ Coll Comp Sci & Technol Harbin Peoples R China China Aerosp Sci & Ind Corp Res Inst 2 Beijing Peoples R China

ISBN: (纸本)9781665435741

The roadside Basic unit (RSU) can relieve the heavy computing and analysis pressure required by vehicles'computing tasks. Due to the mobility of vehicles and limited computing resources, it is difficult to deal extensive vehicle tasks in time. Therefore, we consider the computation task offloading problem between the vehicles, as well as the dynamic topology caused by the vehicle movement and the randomness of task arrival, and propose an online offloading method based on fairness awareness, which can be ensured tolerable delays and the requirement of the quality of experience (QoE) between vehicles by introducing delay-aware and price-constrained virtual queues. By Lyapunov optimization technology, the objective function is transformed into a drift-plus-penalty profit minimum bound problem, achieveing all the offloading decisions by the realtime resource requirements and topology state. Finally, extensive simulations are performed to demonstrate the efficiency of the proposed algorithm.

关键词： Mobile computing offloading vehicle-to-vehicle communication delay tolerance fairness Lyapunov optimization

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Stream processing on Multi-Cores with GPUs: parallel Programming Models' Challenges 33

Stream Processing on Multi-Cores with GPUs: Parallel Program...

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33rd ieee international parallel and distributed processing symposium (IPDPS)

作者： Rockenbach, Dinei A. Stein, Charles M. Griebler, Dalvan Mencagli, Gabriele Torquati, Massimo Danelutto, Marco Fernandes, Luiz G. Tres De Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Pontifical Catholic Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Univ Pisa UNIPI Comp Sci Dept Pisa Italy

ISBN: (纸本)9781538655559

The stream processing paradigm is used in several scientific and enterprise applications in order to continuously compute results out of data items coming from data sources such as sensors. The full exploitation of the potential parallelism offered by current heterogeneous multi-cores equipped with one or more GPUs is still a challenge in the context of stream processing applications. In this work, our main goal is to present the parallel programming challenges that the programmer has to face when exploiting CPUs and GPUs' parallelism at the same time using traditional programming models. We highlight the parallelization methodology in two use-cases (the Mandelbrot Streaming benchmark and the PARSEC's Dedup application) to demonstrate the issues and benefits of using heterogeneous parallel hardware. The experiments conducted demonstrate how a high-level parallel programming model targeting stream processing like the one offered by SPar can be used to reduce the programming effort still offering a good level of performance if compared with state-of-the-art programming models.

关键词： Graphics processing units parallel processing parallel programming Kernel Instruction sets Computational modeling

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A Reconfigurable High Performance ASIP Engine for Image Signal processing

A Reconfigurable High Performance ASIP Engine for Image Sign...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Liao, Hsuanchun Asri, Mochamad Isshiki, Tsuyoshi Li, Dongju Kunieda, Hiroaki Tokyo Inst Technol Dept Commun & Integrated Syst Tokyo 152 Japan

ISBN: (纸本)9780769546766

Emerging digital television applications and the conventional MPSoC architectures encounter drastically increasing performance and flexibility requirement. To display high quality of images on the display devices, several image processing has to be performed. However, these algorithms are nonstandard and change case by case. It is difficult to achieve real time processing by using general purpose processor or DSP. In this paper, we present a reconfigurable Application Specific Instruction-set Processor (ASIP) which can perform several image processing algorithms by using the same datapath. It can complete several 1D filtering processing within 8 cycle/pixel;performing 16 times higher performance compare to conventional RISC processor. the performance of this ASIP can achieve the requirement of FullHD(1920x1080) application.

关键词： ASIP Image processing

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Minimal Aggregated Shared Memory Messaging on distributed Memory Supercomputers 30

Minimal Aggregated Shared Memory Messaging on Distributed Me...

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30th ieee international parallel and distributed processing symposium (IPDPS)

作者： Jamroz, Benjamin F. Dennis, John M. Natl Ctr Atmospher Res Computat Informat Syst Lab Boulder CO 80301 USA

ISBN: (纸本)9781509021406

Many high-performance distributed memory applications rely on point-to-point messaging using the Message Passing Interface (MPI). Due to the latency of the network, and other costs, this communication can limit the scalability of an application when run on high node counts of distributed memory supercomputers. Communication costs are further increased on modern multi- and many-core architectures, when using more than one MPI process per node, as each process sends and receives messages independently, inducing multiple latencies and contention for resources. In this paper, we use shared memory constructs available in the MPI 3.0 standard to implement an aggregated communication method to minimize the number of inter-node messages to reduce these costs. We compare the performance of this Minimal Aggregated SHared Memory (MASHM) messaging to the standard point-to-point implementation on large-scale supercomputers, where we see that MASHM leads to enhanced strong scalability of a weighted Jacobi relaxation. For this application, we also see that the use of shared memory parallelism through MASHM and MPI 3.0 can be more efficient than using Open Multi-processing (OpenMP). We then present a model for the communication costs of MASHM which shows that this method achieves its goal of reducing latency costs while also reducing bandwidth costs. Finally, we present MASHM as an open source library to facilitate the integration of this efficient communication method into existing distributed memory applications.

关键词： Scalability parallel Algorithms parallel Programming

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How well do CPU, GPU and Hybrid Graph processing Frameworks Perform? 32

How well do CPU, GPU and Hybrid Graph Processing Frameworks ...

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27th international Heterogeneity in Computing Workshop in conjunction with 32nd ieee international parallel and distributed processing symposium (IPDPS)

作者： Aasawat, Tanuj Kr Reza, Tahsin Ripeanu, Matei Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781538655559

The importance of high-performance graph processing to solve big data problems targeting high-impact applications is greater than ever before. Recent graph processing frameworks target different hardware platforms (e.g., shared memory systems, accelerators such as GPUs, and distributed systems) and differ with respect to the programming model they adopt (e.g., based on linear algebra formulations of graph algorithms or enabling direct access to the graph structure). To better understand the impact of these choices, this paper, presents a comparative study of five state-of-the-art graph processing frameworks: two CPU-only frameworks - GraphMat and Galois, two GPU-based frameworks - Nvgraph and Gunrock;and Totem, a hybrid (CPU+GPU) framework. We use three popular graph algorithms (PageRank, Single Source Shortest Path, and Breadth-First Search), and massive scale graphs with up to billions of edges. Our evaluation focuses on three performance metrics: (i) execution time, (ii) scalability and (iii) energy consumption.

关键词： Graph processing CPU GPU Hybrid Systems Performance Evaluation PageRank SSSP BFS

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Dynamic detection of academic team communities based on temporal coauthor network 15

Dynamic detection of academic team communities based on temp...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Wan, Wencong Huang, Fang Wang, Xiangqian Zhang, Yuchen Zhang, Chengyuan Cent South Univ Sch Informat Sci & Engn Changsha 410083 Hunan Peoples R China

ISBN: (纸本)9781538637906

As the status of team members and relationships between them change over time, the importance of membership nodes in the academic team also change, so that the academic team organizational structure evolves. The changes caused by the core members of the team led to the evolution of the team structure. Therefore, this paper presents a dynamic community discovery algorithm based on temporal coauthor network. By detecting the importance of nodes, the strength of relative edges, and its variation of persistence with time, the proposed algorithm implements creation, extension, shrink, division and disappearance operations on the communities in order to achieve the purpose of dynamic community discovery. In addition, for assessing the quality of community division, the paper proposes a method based on the interest similarity of Chinese key characters feature of academic teams. In experiment, a public document record dataset and several synthetic dataset are used to verify the effectiveness our algorithm.

关键词： evolution of academic team temporal coauthor network importance of node similarity of character feature

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OPTZ: a Hardware Isolation Architecture of Multi-tasks Based on TrustZone Support 15

OPTZ: a Hardware Isolation Architecture of Multi-tasks Based...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Chen, Kang Dai, Hongjun Shandong Univ Dept Comp Sci & Technol Jinan Shandong Peoples R China

ISBN: (纸本)9781538637906

In order to improve the safety of existing embedded system, make user data more secure, we propose an implementation of multitasking hardware isolation based on TrustZone named OPTZ (Open TrustZone). ARM TrustZone technology can implement the hardware isolation to improve the security of the software without additional hardware chips outside. In this paper we designed a complete trusted execution environment (TEE) and implemented the multitasking hardware isolation between normal world and secure world. Moreover, the multitasks in the secure memory are also separated from each other. Our architecture includes a secure operating system running in secure world, an normal operating system from normal world, secure services and communication mechanism. At last, we have done some experiments of physical memory access to test and verify the correctness of our architecture. Client application(CA) runs in normal world cannot access the secure world's physical address. The trusted application(TA) can communicate with each other but not access. The experiment results show that multitasking hardware isolation worked well, and the memory isolation can reach the hardware level.

关键词： TrustZone trust security multitasking physical isolation

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