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Accelerating Deep Learning based Identification of Chromatin Accessibility from noisy ATAC-seq Data 36

Accelerating Deep Learning based Identification of Chromatin...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Chaudhary, Narendra Misra, Sanchit Kalamkar, Dhiraj Heinecke, Alexander Georganas, Evangelos Ziv, Barukh Adelman, Menachem Kaul, Bharat Intel Parallel Comp Lab Bangalore Karnataka India Intel Corp Parallel Comp Lab Santa Clara CA USA Intel Corp Haifa Israel

ISBN: (纸本)9781665497473

Identifying accessible chromatin regions is a fundamental problem in epigenomics with ATAC-seq being a commonly used assay. Exponential rise in ATAC-seq experiments has made it critical to accelerate processing of ATAC-seq data that can have a low signal-to-noise ratio for various reasons including low coverage or low cell count. To denoise and identify accessible chromatin regions from noisy ATAC-seq data, use of deep learning on 1D data - using large filter sizes, long tensor widths, and/or dilation - has recently been proposed. Convolutions over 1D data consume a majority of the runtime in these methods. However, existing implementations of the 1D convolution layer for CPUs and GPUs fail to efficiently use the underlying architecture especially in the case of large filter sizes, long tensor widths, and dilation. Here, we present ways to accelerate the end-toend training performance of these deep learning based methods. We evaluate our approach on the recently released AtacWorks toolkit using modern CPUs. Compared to AtacWorks running on an Nvidia DGX-1 box with 8 V100 GPUs, we get up to 2.27 x speedup using just 16 CPU sockets. To achieve this, we build an efficient 1D dilated convolution layer and demonstrate reduced precision (BFloatl6) training and nearly linear scaling from 1 to 16 sockets.

关键词： chromatin accessibility ATAC-seq single cell analysis deep learning 1D convolutions architecture-aware optimizations SIMD BF16

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REGAL : Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM 56

REGAL : Reprogrammable Engines for Genome Analysis on LPDDR4...

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56th ieee international symposium on Circuits and Systems (ISCAS)

作者： Sinha, Aman Fang, Yuhao Lai, Bo-Cheng Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu Taiwan

ISBN: (纸本)9781665451093

Genomic big data analysis pipelines are bottlenecked with massive data movement between CPU and memory hierarchy. Recently developed Stacked Embedded DRAM (SEDRAM) with high density hybrid bonding offers not only high bandwidth concurrent data accesses, but also highly parallel distributed data processing on the logic layer. However, the complex logical flow and data dependencies pose challenges to existing Near-DRAM processing (NDP) solutions for analysis such as string pattern matching using FM-Index. In this work, we propose REGAL, a highly scalable and re-programmable solution on SEDRAM memory system. REGAL architecture maximizes intra-query parallelism and enhances occupancy of all components. The efficient data layout and mapping minimizes round-trip communications between processing engines. The programmability of REGAL further enables effective prefetching to support variations in data characteristics and involved algorithms. REGAL demonstrates up-to 17.3x and 70.6x speedup and energy reductions compared to multithreaded CPU implementation for FM-Index queries, while achieving performance comparable to state-of-the-art fixed-function NDP implementation.

关键词： FM-Index Near-DRAM processing SEDRAM RISC-V NoC processing-In-Memory Genome analysis

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distributed Aerial 3D Object Mapping Reconstruction Using Message Passing Interface 26

Distributed Aerial 3D Object Mapping Reconstruction Using Me...

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26th international Electronics symposium (IES) on Shaping the Future - Society 5.0 and Beyond

作者： Arissabarno, Cahyo Winarno, Idris Sukaridhoto, Sritrusta Politekn Elekt Negeri Surabaya Dept Informat & Comp Engn Surabaya Indonesia

ISBN: (纸本)9798350392005;9798350391992

Aerial reconstruction of 3D object mapping involves utilizing drones or Unmanned Aerial Vehicles (UAVs) equipped with cameras to capture images for high-resolution 3D model reconstruction of various objects and terrains. This technique is applicable across various fields, such as Urban Planning, Vehicle Navigation, Environmental Studies, Civil Engineering, and Cultural Heritage Conservation. Drones capture hundreds of overlapping aerial photos, which are then processed to generate photorealistic 3D representations of topographic surfaces using photogrammetry software. However, the reconstruction process is time-consuming and computationally intensive, especially when processing large datasets. This research addresses these challenges by employing parallel computing using the Message Passing Interface (MPI) to distribute the computational workload across multiple nodes. By utilizing MPI, the computational tasks are efficiently divided among four nodes, significantly reducing processing time and alleviating the burden on individual CPUs. The study demonstrates that parallel computing with MPI reduces the reconstruction time from 74 minutes to 27 minutes, achieving a speedup of 2.74 times. This research demonstrates a novel application of MPI to the domain of aerial 3D reconstruction, achieving a specific and substantial reduction in processing time. Additionally, it provides insights into future enhancements, such as parallel texture reconstruction and automation of translation processes.

关键词： Message Passing Interface parallel Computing MPI 3D Reconstruction Aerial 3D Object Mapping

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Towards distributed 2-Approximation Steiner Minimal Trees in Billion-edge Graphs 36

Towards Distributed 2-Approximation Steiner Minimal Trees in...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Reza, Tahsin Sanders, Geoffrey Pearce, Roger Lawrence Livermore Natl Lab LLNL Ctr Appl Sci Comp CASC Livermore CA 94550 USA

ISBN: (纸本)9781665481069

Given an edge-weighted graph and a set of known seed vertices of interest, a network scientist often desires to understand the graph relationships to explain connections between the seed vertices. If the size of the seed set is 2, shortest path calculations are an attractive computational kernel to explore the connections between the two vertices. When the seed set is 3 or larger (say up to 1,000s) Steiner minimal tree - min-weight acyclic connected subgraph (of the input graph) that contains all the seed vertices - is an attractive generalization of shortest weighted paths. In general, computing a Steiner minimal tree is NP-hard, but decades ago several polynomial-time algorithms were designed and proven to yield Steiner trees whose total weight is bounded within 2 times the minimal Steiner tree. Despite its rich theoretical literature, works related to parallel Steiner minimal tree computation and their scalable implementations are rather scarce. In this paper, we present a parallel 2-approximation Steiner minimal tree algorithm (with theoretical guarantees) and its MPI-based distributed implementation. In place of distance computation between all pairs of seed vertices, an expensive phase in many approximation algorithms, the solution we employ, exploits Voronoi cell computation. Also, this approach has higher parallel efficiency than others that involve minimum spanning tree computation on the entire graph. Furthermore, our distributed design exploits asynchronous processing and a message prioritization scheme to accelerate convergence of distance computation, employs techniques to avoid inefficient distributed spanning tree computation on the entire graph, and harnesses a combination of vertex and edge centric processing to offer fast time-to-solution. We demonstrate scalability and performance of our solution using real-world graphs with up to 128 billion edges and 512 compute nodes (8K processes), show the ability to find Steiner trees with up to 10K seed ver

关键词： Steiner trees distributed processing Scalability Approximation algorithms Computational efficiency Kernel Convergence

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"Smarter" NICs for faster molecular dynamics: a case study 36

"Smarter" NICs for faster molecular dynamics: a case study

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Karamati, Sara Hughes, Clayton Hemmert, K. Scott Grant, Ryan E. Schonbein, W. Whit Levy, Scott Conte, Thomas M. Young, Jeffrey Vuduc, Richard W. Georgia Inst Technol Atlanta GA 30332 USA Sandia Natl Labs POB 5800 Albuquerque NM 87185 USA Queens Univ Kingston ON Canada

ISBN: (纸本)9781665481069

This work evaluates the benefits of using a "smart" network interface card (SmartNIC) as a compute accelerator for the example of the MiniMD molecular dynamics proxy application. The accelerator is NVIDIA's BlueField-2 card, which includes an 8-core Arm processor along with a small amount of DRAM and storage. We test the networking and data movement performance of these cards compared to a standard Intel server host using microbenchmarks and MiniMD. In MiniMD, we identify two distinct classes of computation, namely core computation and maintenance computation, which are executed in sequence. We restructure the algorithm and code to weaken this dependence and increase task parallelism, thereby making it possible to increase utilization of the BlueField-2 concurrently with the host. We evaluate our implementation on a cluster consisting of 16 dual-socket Intel Broadwell host nodes with one BlueField-2 per host-node. Our results show that while the overall compute performance of BlueField-2 is limited, using them with a modified MiniMD algorithm allows for up to 20% speedup over the host CPU baseline with no loss in simulation accuracy.

关键词： distributed processing Heuristic algorithms Clustering algorithms Random access memory parallel processing Maintenance engineering Servers

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Bounding the Flow Time in Online Scheduling with Structured processing Sets 36

Bounding the Flow Time in Online Scheduling with Structured ...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Canon, Louis-Claude Dugois, Anthony Marchal, Loris Univ Franche Comte FEMTO ST Inst Besancon France ENS Lyon INRIA LIP Lyon France ENS Lyon INRIA CNRS LIP Lyon France

ISBN: (纸本)9781665481069

Replication in distributed key-value stores makes scheduling more challenging, as it introduces processing set restrictions, which limits the number of machines that can process a given task. We focus on the online minimization of the maximum response time in such systems, that is, we aim at bounding the latency of each task. When processing sets have no structure, Anand et al. (Algorithmica, 2017) derive a strong lower bound on the competitiveness of the problem: no online scheduling algorithm can have a competitive ratio smaller than Omega(m), where m is the number of machines. In practice, data replication schemes are regular, and structured processing sets may make the problem easier to solve. We derive new lower bounds for various common structures, including inclusive, nested or interval structures. In particular, we consider fixed sized intervals of machines, which mimic the standard replication strategy of key-value stores. We prove that EFT (Earliest Finish Time) scheduling is (3 - 2/k)-competitive when optimizing max-flow on disjoint intervals of size k. However, we show that the competitive ratio of EFT is at least m - k + 1 when these intervals overlap, even when unit tasks are considered. We compare these two replication strategies in simulations and assess their efficiency when popularity biases are introduced, i.e., when some machines are accessed more frequently than others because they hold popular data. Even though overlapping intervals suffer from a bad worst-case in theory, they enable clusters to reach a maximum load that is up to 50% higher than with disjoint sets.

关键词： Flow Time Lower Bound Restricted Assignment processing Set Restrictions Replication Key-Value Stores

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Cepheus: Accelerating Datacenter applications with High-Performance RoCE-Capable Multicast 30

Cepheus: Accelerating Datacenter Applications with High-Perf...

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30th ieee international symposium on High-Performance Computer Architecture (HPCA)

作者： Li, Wenxue Zhang, Junyi Liu, Yufei Zeng, Gaoxiong Wang, Zilong Zeng, Chaoliang Zhou, Pengpeng Wang, Qiaoling Chen, Kai Hong Kong Univ Sci & Technol ISING Lab Hong Kong Peoples R China Huawei Shenzhen Peoples R China Univ Sci & Technol China Hefei Peoples R China

ISBN: (纸本)9798350393132;9798350393149

Modern datacenter applications widely exhibit multicast communication patterns. Meanwhile, RDMA is emerging as the de-facto networking architecture to meet the stringent performance requirement of applications. However, existing multicast approaches fail to efficiently collaborate multicast with commodity RDMA transport, either causing inefficient multicast traffic transmission or being trapped in the insufficient end-host transport protocol. In this paper, we propose Cepheus, which delivers performance gains from both multicast (i.e., traffic reduction and transmission hop minimization) and RDMA transport (i.e., ultra-low latency, high throughput and low CPU overhead). Cepheus reuses RoCE as its transport layer and provides a RoCE-capable multicast primitive via in-network assistance. At its core, Cepheus builds on and goes beyond the native multicast architecture by exploiting more switch functionalities to tackle the incompatibilities between multicast flow structure and RoCE processing logic. We prototype Cepheus on an FPGA board, as a building block attached to an Ethernet switch. Extensive experiments demonstrate Cepheus inter-operates with commodity RoCE protocol and outperforms existing RDMA multicast schemes, e.g., 5.2x faster multicast communication and 2.7x higher replication throughput for distributed storage.

关键词： Multicast RDMA RoCE

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GPU Acceleration using CUDA for Computational Electromagnetics

GPU Acceleration using CUDA for Computational Electromagneti...

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international Applied-Computational-Electromagnetics-Society symposium (ACES)

作者： Sideris, Constantine Univ Southern Calif Los Angeles CA 90089 USA

ISBN: (纸本)9781733509671;9798350362978

Although initially designed for graphics rendering applications, Graphics processing Units (GPUs), due to their massively parallel many-core nature, have seen widespread use in accelerating many computationally expensive algorithms in recent years. In particular, GPUs have revolutionized the field of machine learning, enabling training deep neural network models which are multiple orders of magnitude larger than previously possible. Even consumer-grade GPUs, which have become very affordable and can be found in personal workstations (e.g., the NVIDIA GeForce RTX 4090), can achieve upwards of 80 TeraFLOPS computing performance. © 2024 The Applied Computational Electromagnetics Society.

关键词： Graphics processing unit

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ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control applications 56

ColibriES: A Milliwatts RISC-V Based Embedded System Leverag...

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56th ieee international symposium on Circuits and Systems (ISCAS)

作者： Rutishauser, Georg Hunziker, Robin Di Mauro, Alfio Bian, Sizhen Benini, Luca Magno, Michele Swiss Fed Inst Technol Dept Informat Technol & Elektrotech Zurich Switzerland Univ Bologna Dipartimento Ingn Energia Elettr & Informaz Bologna Italy

ISBN: (纸本)9781665451093

End-to-end event-based computation has the potential to push the envelope in latency and energy efficiency for edge AI applications. Unfortunately, event-based sensors (e.g., DVS cameras) and neuromorphic spike-based processors (e.g., Loihi) have been designed in a decoupled fashion, thereby missing major streamlining opportunities. This paper presents ColibriES, the first-ever neuromorphic hardware embedded system platform with dedicated event-sensor interfaces and full processing pipelines. ColibriES includes event and frame interfaces and data processing, aiming at efficient and long-life embedded systems in edge scenarios. ColibriES is based on the Kraken system-on-chip and contains a heterogeneous parallel ultra-low power (PULP) processor, frame-based and event-based camera interfaces, and two hardware accelerators for the computation of both event-based spiking neural networks and frame-based ternary convolutional neural networks. This paper explores and accurately evaluates the performance of event data processing on the example of gesture recognition on ColibriES, as the first step of full-system evaluation. In our experiments, we demonstrate a chip energy consumption of 7.7 mJ and latency of 164.5 ms of each inference with the DVS Gesture event data set as an example for closed-loop data processing, showcasing the potential of ColibriES for battery-powered applications such as wearable devices and UAVs that require low-latency closed-loop control.

关键词： Embedded systems

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ParaDiS: a parallel and distributed framework for Significant pattern mining 23

ParaDiS: a Parallel and Distributed framework for Significan...

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23rd ieee/ACM international symposium on Cluster, Cloud and Internet Computing (CCGrid)

作者： Jyoti Kailasam, Sriram Buzmakov, Aleksey Indian Inst Technol Mandi Sch Comp & Elect Engn Mandi Himachal Prades India Natl Inst Technol Warangal Dept Comp Sci & Engn Warangal Telangana India Natl Res Univ Higher Sch Econ Perm Russia

ISBN: (纸本)9798350302080

Mining patterns having a high association with a class label is a supervised data mining technique, frequently used in many applications. As we test many patterns using statistical tests to find all interesting patterns, a certain association is likely achieved by chance. The state-of-the-art TopKWY algorithm mines the top-k interesting patterns while controlling the family-wise-error rate (FWER) in the result set. TopKWY is a sequential algorithm that internally uses compute-intensive closed pattern mining. Moreover, it tests several patterns against thousands of permuted class labels to control FWER. To the best of our knowledge, no parallel/distributed implementation exists to address the scalability challenges faced by TopKWY. The tree formed by the explored patterns in TopKWY is inherently irregular and the search strategy used for exploration, namely, the best-first search is non-trivial to emulate in a distributed setup. This paper designs and implements ParaDiS, a novel parallel and distributed framework for mining the top-k statistically significant patterns. We compare its performance with the sequential TopKWY algorithm for real-world datasets and observe a significant reduction in execution time. We further show that our framework achieves good speedup, minimal communication overhead, and faster pruning of non-promising branches by efficient sharing of significance threshold.

关键词： significant pattern discovery distributed best-first search irregular structure dynamic load balancing scalable family-wise-error rate closed pattern

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