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Self-Adaptive Heterogeneous Cluster with Wireless Network

Self-Adaptive Heterogeneous Cluster with Wireless Network

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Niu, Xinyu Tsoi, Kuen Hung Luk, Wayne Imperial Coll London Dept Comp Sch Engn London England

ISBN: (纸本)9780769546766

The high performance computing (HPC) community has been exploring novel platforms to push performance forward. Field Programmable Logic Arrays (FPGAs) and Graphics processing Units (GPUs) have been widely used as accelerators for computational intensive applications. Heterogeneous cluster is one of the promising platforms as it combines characteristics of multiple processing elements, to meet requirements of various applications. In this work, we build a self-adaptive framework for heterogeneous clusters, coupled with a customised wireless network. A runtime cluster model is implemented to predict throughput, power and thermal merits for heterogeneous clusters. Cluster configurations are scheduled to improve cluster power efficiency, as well as to reduce peak temperature of processing elements. Results show that, for monitoring operations upon heterogeneous clusters, the customised wireless network provides stable and scalable performance for negligible overhead. A high performance application is developed under the proposed framework. Experiments show that this approach can improve both power efficiency and energy efficiency of N-body simulation for more than 15 times, while reducing device peak temperature by up to 12 degrees C.

关键词： Wireless networks peak temperature dynamic efficiency N-body simulation self-adaptive Accelerators High Performance Computing processing Element Energy efficiency

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Auto-tuning Parameter Choices in HPC applications using Bayesian Optimization 34

Auto-tuning Parameter Choices in HPC Applications using Baye...

引用

34th ieee international parallel and distributed processing symposium (IPDPS)

作者： Menon, Harshitha Bhatele, Abhinav Gamblin, Todd Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA Univ Maryland Dept Comp Sci College Pk MD 20742 USA

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168760

High performance computing applications, runtimes, and platforms are becoming more configurable to enable applications to obtain better performance. As a result, users are increasingly presented with a multitude of options to configure application-specific as well as platform-level parameters. The combined effect of different parameter choices on application performance is difficult to predict, and an exhaustive evaluation of this combinatorial parameter space is practically infeasible. One approach to parameter selection is a user-guided exploration of a part of the space. However, such an ad hoc exploration of the parameter space can result in suboptimal choices. Therefore, an automatic approach that can efficiently explore the parameter space is needed. In this paper, we propose HiPerBOt, a Bayesian optimization based configuration selection framework to identify application and platform-level parameters that result in high performing configurations. We demonstrate the effectiveness of HiPerBOt in tuning parameters that include compiler flags, runtime settings, and application-level options for several parallel codes, including, Kripke, Hypre, LULESH, and OpenAtom.

关键词： parameter selection autotuning transfer learning performance

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Communication-efficient Massively distributed Connected Components 36

Communication-efficient Massively Distributed Connected Comp...

引用

36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Lamm, Sebastian Sanders, Peter Karlsruhe Inst Technol Inst Theoret Informat Karlsruhe Germany

ISBN: (纸本)9781665481069

Finding the connected components of an undirected graph is one of the most fundamental graph problems. Connected components are used in a wide spectrum of applications including VLSI design, machine learning and image analysis. Sequentially, one can easily find all connected components in linear time using breadth-first traversal. However, in a massively distributed setting, finding connected components in a scalable way becomes much harder due to data irregularities and the overhead associated with the increased need for communication. In this work, we present a communication-efficient distributed graph algorithm for finding connected components that scales to massively parallel machines. Our algorithm is based on a recent linear-work shared-memory parallel algorithm by Blelloch et al. [1] and refines it for a distributed memory setting. This includes a communication-efficient graph contraction procedure, as well as a distributed variant of the low diameter decomposition by Miller et al. [2]. We tackle the data irregularities introduced by high degree vertices by using an efficient procedure for distributing their incident edges. Our experimental evaluation on up to 16 384 cores indicates a good weak scaling behavior that outperforms current state-of-the-art algorithms.

关键词： graph algorithms distributed algorithms communication efficiency graph connectivity

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A parallel Algorithm for Instruction Dependence Graph Analysis based on Multithreading 16

A Parallel Algorithm for Instruction Dependence Graph Analys...

引用

16th ieee ISPA / 17th ieee IUCC / 8th ieee BDCloud / 11th ieee SocialCom / 8th ieee SustainCom

作者： Wang, Lei Deng, Yu Gong, Rui Shi, Wei Zhao, Zhenyu Dou, Qiang Natl Univ Def Technol Coll Comp Changsha Hunan Peoples R China

ISBN: (纸本)9781728111414

Microprocessor design space exploration is an inevitable stage in the early stages of microprocessor design. In work [1], a critical path analysis based design space exploration method is proposed. Critical path analysis on the instruction dependence graph is often used in the research of the micro-architecture of the instruction pipeline of the microprocessor. Previous analysis method must process the huge log file serially and the analysis time was very long. In this paper, a parallel analysis algorithm based on multithreading was presented. By partitioning the log file into multiple blocks and using multiple threads to process them in parallel, this algorithm achieved a nearly linear speedup according to the number of thread.

关键词： Critical Path Analysis Dependency Graph Design Space Exploration parallel processing

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Modifying HMMER3 to Run Efficiently on the Cori Supercomputer using OpenMP Tasking 32

Modifying HMMER3 to Run Efficiently on the Cori Supercompute...

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32nd ieee international parallel and distributed processing symposium (IPDPS)

作者： Arndt, William Lawrence Berkeley Natl Lab Natl Energy Res Sci Comp Ctr Berkeley CA 94720 USA

ISBN: (纸本)9781538655559

HMMER3 is biological sequence search suite used in significant volume on systems hosted at the National Energy Research Scientific Computing Center. This heavy usage has revealed ways that HMMER3 underutilizes the resources available in an HPC environment such as the Manycore architecture Knights Landing processors available in the Cori supercomputer. After rigorous performance analysis it was determined that the thread architecture of HMMER3 is the most promising optimization target to increase throughput and efficiency. A refactoring effort introduced an OpenMP task based threading design, the ability to respond to imbalanced computation with work stealing, and input buffering to eliminate a large amount of redundant parsing. These efforts have been implemented and in production on Cori for over a year. In that time they have simplified the best practice for use of HMMER3 in workflows and conserved hundreds of thousands of CPU hours.

关键词： Multithreading Multicore processing OpenMP High Performance Computing Bioinformatics

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Multi-path Routing for Energy Efficient Mobile Offloading in Software Defined Networks 15

Multi-path Routing for Energy Efficient Mobile Offloading in...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Hou, Haixiang Jin, Hai Liao, Xiaofei Zeng, Deze Huazhong Univ Sci & Technol Sch Comp Sci & Technol Serv Comp Technol & Syst Lab Cluster & Grid Comp Lab Wuhan Hubei Peoples R China China Univ Geosci Sch Comp Sci Beijing Peoples R China

ISBN: (纸本)9781538637906

In Software Defined Network (SDN), rule space is an unavoidable restriction caused by Ternary Content Addressable Memory (TCAM). When offloading becomes more popular, a sharp increase in the number of flows influences the link scheduling and the Quality of Service (QoS) for customers. Thus, the link scheduling in SDN must consider the constraints about rule space, bandwidth, and QoS. To optimize the energy consumption in mobile computing, we build a model to understand the relationships among offloading decisions, latency, and energy consumption. We implement a two-phase algorithm to schedule links by the usage of rule space in the switches and the usage of bandwidth in links. Through comparative evaluation, we verify the feasibility of the algorithm. When the usage of rule space in SDN network is not full, the algorithm can archive more than 90% energy efficiency compared to the optimal solution.

关键词： Software Defined Network Multi-Path Routing Rule Placement Optimization

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Accelerating Large Scale Image Analyses on parallel, CPU-GPU Equipped Systems

Accelerating Large Scale Image Analyses on Parallel, CPU-GPU...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Teodoro, George Kurc, Tahsin M. Pan, Tony Cooper, Lee A. D. Kong, Jun Widener, Patrick Saltz, Joel H. Emory Univ Ctr Comprehens Informat Atlanta GA 30322 USA

ISBN: (纸本)9780769546759

The past decade has witnessed a major paradigm shift in high performance computing with the introduction of accelerators as general purpose processors. These computing devices make available very high parallel computing power at low cost and power consumption, transforming current high performance platforms into heterogeneous CPU-GPU equipped systems. Although the theoretical performance achieved by these hybrid systems is impressive, taking practical advantage of this computing power remains a very challenging problem. Most applications are still deployed to either GPU or CPU, leaving the other resource under-or un-utilized. In this paper, we propose, implement, and evaluate a performance aware scheduling technique along with optimizations to make efficient collaborative use of CPUs and GPUs on a parallel system. In the context of feature computations in large scale image analysis applications, our evaluations show that intelligently co-scheduling CPUs and GPUs can significantly improve performance over GPU-only or multi-core CPU-only approaches.

关键词： Image analysis In Silico Microscopy CPU-GPU systems

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Large-Scale Stochastic Learning using GPUs 31

Large-Scale Stochastic Learning using GPUs

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31st ieee international parallel and distributed processing symposium Workshops (IPDPS)

作者： Parnell, Thomas Dunner, Celestine Atasu, Kubilay Sifalakis, Manolis Pozidis, Haris IBM Res Zurich Saumerstr 4 Ruschlikon Switzerland

ISBN: (纸本)9780769561493

In this work we propose an accelerated stochastic learning system for very large-scale applications. Acceleration is achieved by mapping the training algorithm onto massively parallel processors: we demonstrate a parallel, asynchronous GPU implementation of the widely used stochastic coordinate descent/ascent algorithm that can provide up to 35x speedup over a sequential CPU implementation. In order to train on very large datasets that do not fit inside the memory of a single GPU, we then consider techniques for distributed stochastic learning. We propose a novel method for optimally aggregating model updates from worker nodes when the training data is distributed either by example or by feature. Using this technique, we demonstrate that one can scale out stochastic learning across up to 8 worker nodes without any significant loss of training time. Finally, we combine GPU acceleration with the optimized distributed method to train on a dataset consisting of 200 million training examples and 75 million features. We show by scaling out across 4 GPUs, one can attain a high degree of training accuracy in around 4 seconds: a 20x speed-up in training time compared to a multi-threaded, distributed implementation across 4 CPUs.

关键词： Asynchronous Learning distributed Computing GPU Machine Learning

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System Noise Revisited: Enabling Application Scalability and Reproducibility with SMT 30

System Noise Revisited: Enabling Application Scalability and...

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30th ieee international parallel and distributed processing symposium (IPDPS)

作者： Leon, Edgar A. Karlin, Ian Moody, Adam T. Lawrence Livermore Natl Lab Livermore Comp Livermore CA 94550 USA

ISBN: (纸本)9781509021406

Despite significant advances in reducing system noise, the scalability and performance of scientific applications running on production commodity clusters today continue to suffer from the effects of noise. Unlike custom and expensive leadership systems, the Linux ecosystem provides a rich set of services that application developers utilize to increase productivity and to ease porting. The cost is the overhead that these services impose on a running application, negatively impacting its scalability and performance reproducibility. In this work, we propose and evaluate a simple yet effective way to isolate an application from system processes by leveraging Simultaneous Multi-Threading (SMT), a pervasive architectural feature on current systems. Our method requires no changes to the operating system or to the application. We quantify its effectiveness on a diverse set of scientific applications of interest to the U.S. Department of Energy showing performance improvements of up to 2.4 times at 16,384 tasks for a high-order finite elements shock hydrodynamics application. Finally, we provide guidance to system and application developers on how to best leverage SMT under different application characteristics and scales.

关键词： system noise jitter simultaneous multithreading SMT scalability reproducibility parallel performance

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DECISION: Distributing OpenVX applications on CPUs, GPUs and FPGAs using OpenCL 36

DECISION: Distributing OpenVX Applications on CPUs, GPUs and...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Kalms, Lester Haering, Tim Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781665497473

The demand for computer vision systems and algorithms is steadily increasing. However, users often have to deal with different or new languages, architectures and tools. Furthermore, there is often no linkage between vendors, defined standards, or model-based modularization to connect everything. We propose a modularized framework for distributing applications on heterogeneous systems consisting of CPUs, GPUs, and FPGAs. The user builds an OpenVX-compliant application without knowledge of the underlying hardware. The middleend automatically schedules and maps the nodes to the available OpenCL devices. Benefits of FPGA acceleration, such as pipelining and running multiple nodes in parallel, are taken into account. The backend generates a program including memory management, synchronization mechanisms and data transfers, even between vendors. This is executed in our parallelized OpenCL based runtime system with minimal overhead. We achieved speedups of 1.63 for a heterogeneous schedule in comparison to a single GPU design when limiting the FPGA resources. Without this limitation a speedup of 13.39 is achieved for the same application.

关键词： OpenVX OpenCL Framework Scheduling Mapping Computer Vision FPGA GPU CPU

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